stm32mp13: addition of i2c and ltdc support for the stm32mp135f-dk

boards/st/stm32mp135f_dk/stm32mp135f_dk.dts

@@ -8,6 +8,7 @@
 
 #include <st/mp13/stm32mp135.dtsi>
 #include <st/mp13/stm32mp135faex-pinctrl.dtsi>
+#include "zephyr/dt-bindings/display/panel.h"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
@@ -19,6 +20,7 @@
 		zephyr,sram = &ddr_data;
 		zephyr,console = &uart4;
 		zephyr,shell-uart = &uart4;
+		zephyr,display = &ltdc;
 	};
 
 	gpio_keys {
@@ -35,14 +37,24 @@
 		compatible = "gpio-leds";
 
 		blue_led_1: led_1 {
-			gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
 			label = "LD3";
 		};
 
 		red_led_2: led_2 {
-			gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
 			label = "LD4";
 		};
+
+		green_led_3: led_3 {
+			gpios = <&mcp23017 14 GPIO_ACTIVE_HIGH>;
+			label = "LD7";
+		};
+
+		orange_led_4: led_4 {
+			gpios = <&mcp23017 15 GPIO_ACTIVE_HIGH>;
+			label = "LD6";
+		};
 	};
 
 	aliases {
@@ -91,3 +103,64 @@
 	current-speed = <115200>;
 	status = "okay";
 };
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_scl_pd12 &i2c1_sda_pe8>;
+	status = "okay";
+
+	mcp23017: pinctrl@21 {
+		compatible = "microchip,mcp23017";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4_scl_pe15 &i2c4_sda_pb9>;
+	status = "okay";
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_scl_pd1 &i2c5_sda_ph6>;
+	status = "okay";
+};
+
+&ltdc {
+	pinctrl-0 = <&ltdc_r2_pg7 &ltdc_r3_pb12
+			&ltdc_r4_pd14 &ltdc_r5_pe7 &ltdc_r6_pe13 &ltdc_r7_pe9
+			&ltdc_g2_ph13 &ltdc_g3_pf3
+			&ltdc_g4_pd5 &ltdc_g5_pg0 &ltdc_g6_pc7 &ltdc_g7_pa15
+			&ltdc_b2_pd10 &ltdc_b3_pf2
+			&ltdc_b4_ph14 &ltdc_b5_pe0 &ltdc_b6_pb6 &ltdc_b7_pf1
+			&ltdc_de_ph9 &ltdc_clk_pd9 &ltdc_hsync_pc6 &ltdc_vsync_pg4>;
+	pinctrl-names = "default";
+	disp-on-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+
+	width = <480>;
+	height = <272>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		hsync-len = <41>;
+		vsync-len = <10>;
+		hback-porch = <13>;
+		vback-porch = <2>;
+		hfront-porch = <32>;
+		vfront-porch = <2>;
+	};
+	def-back-color-red = <0xFF>;
+	def-back-color-green = <0xFF>;
+	def-back-color-blue = <0xFF>;
+};

drivers/clock_control/clock_stm32_ll_mp13.c

@@ -70,6 +70,25 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 		case LL_APB1_GRP1_PERIPH_UART4:
 			*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
 			break;
+		case LL_APB1_GRP1_PERIPH_I2C1:
+		case LL_APB1_GRP1_PERIPH_I2C2:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_CLKSOURCE);
+			break;
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_APB6:
+		switch (pclken->enr) {
+		case LL_APB6_GRP1_PERIPH_I2C3:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C3_CLKSOURCE);
+			break;
+		case LL_APB6_GRP1_PERIPH_I2C4:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C4_CLKSOURCE);
+			break;
+		case LL_APB6_GRP1_PERIPH_I2C5:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C5_CLKSOURCE);
+			break;
 		default:
 			return -ENOTSUP;
 		}

drivers/display/display_stm32_ltdc.c

@@ -94,7 +94,7 @@ static void stm32_ltdc_global_isr(const struct device *dev)
 			data->front_buf = data->pend_buf;
 
 			LTDC_LAYER(&data->hltdc, LTDC_LAYER_1)->CFBAR = (uint32_t)data->front_buf;
-			__HAL_LTDC_RELOAD_CONFIG(&data->hltdc);
+			__HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(&data->hltdc);
 
 			k_sem_give(&data->sem);
 		}

dts/arm/st/mp13/stm32mp13.dtsi

@@ -11,6 +11,7 @@
 
 #include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/reset/stm32mp13_reset.h>
 
@@ -166,6 +167,71 @@
 				      <8 1>, <9 1>, <10 1>, <11 1>,
 				      <12 1>, <13 1>, <14 1>, <15 1>;
 		};
+
+		i2c1: i2c@40012000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21)>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c2: i2c@40013000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22)>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c3: i2c@4c004000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4c004000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB6, 4)>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c4: i2c@4c005000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4c005000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB6, 5)>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c5: i2c@4c006000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4c006000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB6, 6)>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
 	};
 
 	gic: gic@A0021000 {

dts/arm/st/mp13/stm32mp135.dtsi

@@ -9,5 +9,16 @@
 / {
 	soc {
 		compatible = "st,stm32mp135", "st,stm32mp13", "simple-bus";
+
+		ltdc: display-controller@5a001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x1000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "ltdc", "ltdc_er";
+			clocks = <&rcc STM32_CLOCK(APB4_NS, 0)>;
+			resets = <&rctl STM32_RESET(APB4, 0)>;
+			status = "disabled";
+		};
 	};
 };

include/zephyr/dt-bindings/clock/stm32mp13_clock.h

@@ -13,6 +13,7 @@
 #define STM32_CLOCK_BUS_APB2    0x708
 #define STM32_CLOCK_BUS_APB3    0x710
 #define STM32_CLOCK_BUS_APB4    0x728
+#define STM32_CLOCK_BUS_APB4_NS	0x738
 #define STM32_CLOCK_BUS_APB5    0x740
 #define STM32_CLOCK_BUS_APB6    0x748
 #define STM32_CLOCK_BUS_AHB2    0x750

modules/Kconfig.stm32

@@ -117,6 +117,17 @@ config USE_STM32_HAL_DCMI_EX
 	  Enable STM32Cube Extended Digital camera interface (DCM) HAL module
 	  driver
 
+config USE_STM32_HAL_DCMIPP
+	bool
+	help
+	  Enable STM32Cube Digital Camera Interface Pixel Pipeline (DCMIPP) HAL module
+	  driver
+
+config USE_STM32_HAL_DDR
+	bool
+	help
+	  Enable STM32Cube DDR-SDRAM HAL module driver
+
 config USE_STM32_HAL_DFSDM
 	bool
 	help

west.yml

@@ -243,7 +243,7 @@ manifest:
       groups:
         - hal
     - name: hal_stm32
-      revision: 237391328ba97f70240cd30b24cffeca6152f86f
+      revision: fcd37242dcaa19a05b014a378c592e257083fe72
       path: modules/hal/stm32
       groups:
         - hal