diff --git a/arch/rx/core/CMakeLists.txt b/arch/rx/core/CMakeLists.txt index a45a6d9acc983..524704ab6e131 100644 --- a/arch/rx/core/CMakeLists.txt +++ b/arch/rx/core/CMakeLists.txt @@ -13,6 +13,7 @@ zephyr_library_sources( isr_exit.S fatal.c reboot.c + nmi.c ) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) diff --git a/arch/rx/core/nmi.c b/arch/rx/core/nmi.c new file mode 100644 index 0000000000000..f4b637a8f1955 --- /dev/null +++ b/arch/rx/core/nmi.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#define NMI_NMIST_MASK 0x01 +#define NMI_OSTST_MASK 0x02 +#define NMI_IWDTST_MASK 0x08 +#define NMI_LVD1ST_MASK 0x10 +#define NMI_LVD2ST_MASK 0x20 + +#define NMIER_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMIER) +#define NMISR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMISR) +#define NMICLR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMICLR) +#define REG(addr) *((uint8_t *)(addr)) + +struct nmi_vector_entry _nmi_vector_table[NMI_TABLE_SIZE] = { + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* NMI Pin Interrupt */ + {(nmi_callback_t)0xFFFFFFFFU, + (void *)0xFFFFFFFFU}, /* Oscillation Stop Detection Interrupt */ + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* IWDT Underflow/Refresh Error */ + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* Voltage Monitoring 1 Interrupt */ + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* Voltage Monitoring 2 Interrupt */ +}; + +void nmi_enable(uint8_t nmi_vector, nmi_callback_t callback, void *arg) +{ + if (nmi_vector >= NMI_TABLE_SIZE) { + return; + } + + _nmi_vector_table[nmi_vector].callback = callback; + _nmi_vector_table[nmi_vector].arg = arg; + + switch (nmi_vector) { + /* NMI Pin Interrupt */ + case 0: + REG(NMIER_BASE_ADDRESS) |= (1 << 0); + break; + /* Oscillation Stop Detection Interrupt */ + case 1: + REG(NMIER_BASE_ADDRESS) |= (1 << 1); + break; + /* IWDT Underflow/Refresh Error */ + case 2: + REG(NMIER_BASE_ADDRESS) |= (1 << 3); + break; + /* Voltage Monitoring 1 Interrupt */ + case 3: + REG(NMIER_BASE_ADDRESS) |= (1 << 4); + break; + /* Voltage Monitoring 2 Interrupt */ + case 4: + REG(NMIER_BASE_ADDRESS) |= (1 << 5); + break; + default: + break; + } +} + +int get_nmi_request(void) +{ + uint8_t nmi_status = REG(NMISR_BASE_ADDRESS); + + if (nmi_status & NMI_NMIST_MASK) { + return 0; + } else if (nmi_status & NMI_OSTST_MASK) { + return 1; + } else if (nmi_status & NMI_IWDTST_MASK) { + return 2; + } else if (nmi_status & NMI_LVD1ST_MASK) { + return 3; + } else if (nmi_status & NMI_LVD2ST_MASK) { + return 4; + } + + return NMI_TABLE_SIZE; +} + +void handle_nmi(uint8_t nmi_vector) +{ + if (nmi_vector >= NMI_TABLE_SIZE) { + return; + } + + _nmi_vector_table[nmi_vector].callback(_nmi_vector_table[nmi_vector].arg); + + switch (nmi_vector) { + case 0: + REG(NMICLR_BASE_ADDRESS) |= (1 << 0); + break; + case 1: + REG(NMICLR_BASE_ADDRESS) |= (1 << 1); + break; + case 2: + REG(NMICLR_BASE_ADDRESS) |= (1 << 3); + break; + case 3: + REG(NMICLR_BASE_ADDRESS) |= (1 << 4); + break; + case 4: + REG(NMICLR_BASE_ADDRESS) |= (1 << 5); + break; + default: + break; + } +} diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c index ff0154475fdcb..c43d8acf98852 100644 --- a/arch/rx/core/vects.c +++ b/arch/rx/core/vects.c @@ -8,7 +8,10 @@ #include #include #include -#include +#include +#ifndef CONFIG_SOC_SERIES_RX62N +#include +#endif typedef void (*fp)(void); extern void _start(void); @@ -19,20 +22,22 @@ extern void z_rx_irq_exit(void); #define CONFIG_GEN_IRQ_START_VECTOR 0 #endif +#ifndef SOC_RX_MDE +#define SOC_RX_MDE (0xFFFFFFFFUL) +#endif +#ifndef SOC_RX_OFS0 +#define SOC_RX_OFS0 (0xFFFFFFFFUL) +#endif +#ifndef SOC_RX_OFS1 +#define SOC_RX_OFS1 (0xFFFFFFFFUL) +#endif + #define EXVECT_SECT __attribute__((section(".exvectors"))) #define RVECT_SECT __attribute__((section(".rvectors"))) #define FVECT_SECT __attribute__((section(".fvectors"))) #define __ISR__ __attribute__((interrupt, naked)) -#define SET_OFS1_HOCO_BITS(reg, freq) \ - ((reg) & ~(0b11 << 12)) | ((((freq) == 24000000 ? 0b10 \ - : (freq) == 32000000 ? 0b11 \ - : (freq) == 48000000 ? 0b01 \ - : (freq) == 64000000 ? 0b00 \ - : 0b11) \ - << 12)) - static ALWAYS_INLINE void REGISTER_SAVE(void) { __asm volatile( @@ -106,9 +111,9 @@ static void __ISR__ INT_Excep_FloatingPoint(void) static void __ISR__ INT_NonMaskableInterrupt(void) { REGISTER_SAVE(); - ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); - ISR_DIRECT_FOOTER(1); + int nmi_vector = get_nmi_request(); + + handle_nmi(nmi_vector); REGISTER_RESTORE_EXIT(); } @@ -430,12 +435,10 @@ INT_DEMUX(255); const void *FixedVectors[] FVECT_SECT = { /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ /* Reserved for OFSM */ + (fp)SOC_RX_MDE, (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)(SET_OFS1_HOCO_BITS( - 0xFFFFFFFF, - (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(hoco), clock_frequency, 32000000)))), - (fp)0xFFFFFFFF, + (fp)SOC_RX_OFS1, + (fp)SOC_RX_OFS0, /* Reserved area */ (fp)0xFFFFFFFF, (fp)0xFFFFFFFF, @@ -490,10 +493,10 @@ const FVECT_SECT void *resetVector = _start; */ const void *ExceptVectors[] EXVECT_SECT = { /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ + (fp)SOC_RX_MDE, (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, + (fp)SOC_RX_OFS1, + (fp)SOC_RX_OFS0, (fp)0xFFFFFFFF, (fp)0xFFFFFFFF, (fp)0xFFFFFFFF, diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts index 0c30d47cd257c..4473713f38c71 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130.dts +++ b/boards/renesas/rsk_rx130/rsk_rx130.dts @@ -52,6 +52,7 @@ led0 = &led1; led1 = &led3; sw0 = &sw1; + watchdog0 = &iwdt; }; }; @@ -72,6 +73,10 @@ status = "okay"; }; +&iwdtlsclk { + status = "okay"; +}; + &cmt { clock-frequency = <4000000>; status = "okay"; @@ -145,3 +150,9 @@ pinctrl-names = "default"; status = "okay"; }; + +&iwdt { + window-start = <0x3000>; + window-end = <0x0300>; + status = "okay"; +}; diff --git a/drivers/watchdog/CMakeLists.txt b/drivers/watchdog/CMakeLists.txt index 2c048d041c8a4..38565d2726f89 100644 --- a/drivers/watchdog/CMakeLists.txt +++ b/drivers/watchdog/CMakeLists.txt @@ -63,6 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_ANDES_ATCWDT200 wdt_andes_atcwdt200.c) zephyr_library_sources_ifdef(CONFIG_WDT_NXP_FS26 wdt_nxp_fs26.c) zephyr_library_sources_ifdef(CONFIG_WDT_SHELL wdt_shell.c) zephyr_library_sources_ifdef(CONFIG_WDT_RENESAS_RA wdt_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_WDT_RENESAS_RX_IWDT wdt_renesas_rx_iwdt.c) zephyr_library_sources_ifdef(CONFIG_WDT_NXP_EWM wdt_nxp_ewm.c) zephyr_library_sources_ifdef(CONFIG_WDT_TI_RTI wdt_ti_rti.c) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 72a51e644da2a..322dc2c7d71a8 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -153,6 +153,8 @@ source "drivers/watchdog/Kconfig.rts5912" source "drivers/watchdog/Kconfig.renesas_ra" +source "drivers/watchdog/Kconfig.renesas_rx" + source "drivers/watchdog/Kconfig.wch" source "drivers/watchdog/Kconfig.nxp_ewm" diff --git a/drivers/watchdog/Kconfig.renesas_rx b/drivers/watchdog/Kconfig.renesas_rx new file mode 100644 index 0000000000000..dcea97a028fee --- /dev/null +++ b/drivers/watchdog/Kconfig.renesas_rx @@ -0,0 +1,41 @@ +# Renesas RX Watchdog configuration + +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config WDT_RENESAS_RX_IWDT + bool "Renesas RX Series Independent Watchdog Driver" + default y + depends on DT_HAS_RENESAS_RX_IWDT_ENABLED + select HAS_WDT_DISABLE_AT_BOOT if WDT_RENESAS_RX_IWDT_REGISTER_START_MODE + select USE_RX_RDP_IWDT + help + Enable Renesas RX series watchdog driver. + +if WDT_RENESAS_RX_IWDT + +config WDT_RENESAS_RX_IWDT_USE_NMI + bool "Non-maskable interrupt for IWDT" + default y + help + Enable NMI for IWDT. + +choice + prompt "IWDT Start Mode" + default WDT_RENESAS_RX_IWDT_REGISTER_START_MODE + help + Select the IWDT start mode. + - WDT_RENESAS_RX_IWDT_AUTO_START_MODE: Counting automatically starts after a reset + (auto-start mode), controlled by option function select register 0 (OFS0). + - WDT_RENESAS_RX_IWDT_REGISTER_START_MODE: Counting is started by refreshing the counter. + (controlled by the IWDT registers) + +config WDT_RENESAS_RX_IWDT_AUTO_START_MODE + bool "Start IWDT automatically on reset" + +config WDT_RENESAS_RX_IWDT_REGISTER_START_MODE + bool "IWDT Start Mode Select" + +endchoice + +endif # WDT_RENESAS_RX_IWDT diff --git a/drivers/watchdog/wdt_renesas_rx_iwdt.c b/drivers/watchdog/wdt_renesas_rx_iwdt.c new file mode 100644 index 0000000000000..9b72303c07a8e --- /dev/null +++ b/drivers/watchdog/wdt_renesas_rx_iwdt.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Independent Watchdog (IWDT) Driver for Renesas RX + */ + +#define DT_DRV_COMPAT renesas_rx_iwdt + +#include +#include +#include +#include +#include + +#include "r_iwdt_rx_if.h" + +#include + +#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL +#include +LOG_MODULE_REGISTER(wdt_iwdt_rx); + +#define IWDT_NODELABEL DT_NODELABEL(iwdt) +#define IWDT_NMI_VECTOR 2 + +#ifdef CONFIG_WDT_RENESAS_RX_IWDT_REGISTER_START_MODE +#define IWDT_WINDOW_START DT_PROP(IWDT_NODELABEL, window_start) +#define IWDT_WINDOW_END DT_PROP(IWDT_NODELABEL, window_end) +#endif /* CONFIG_WDT_RENESAS_RX_IWDT_REGISTER_START_MODE */ + +#define WDT_RENESAS_RX_SUPPORTED_FLAGS (WDT_FLAG_RESET_NONE | WDT_FLAG_RESET_SOC) +struct wdt_iwdt_rx_config { + struct st_iwdt *const regs; + const struct device *clock_dev; +}; + +struct wdt_iwdt_rx_data { + wdt_callback_t callback; + iwdt_config_t iwdt_config; + bool timeout_installed; +}; + +#if CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI +static void wdt_iwdt_isr(const struct device *dev) +{ + struct wdt_iwdt_rx_data *data = dev->data; + + wdt_callback_t callback = data->callback; + + if (callback) { + callback(dev, 0); + } +} +#endif /* CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI */ + +static int wdt_iwdt_rx_disable(const struct device *dev) +{ + ARG_UNUSED(dev); + + LOG_ERR("Independent Watchdog cannot be stopped once started"); + + return -EPERM; +} + +static int wdt_iwdt_rx_feed(const struct device *dev, int channel_id) +{ + ARG_UNUSED(dev); + ARG_UNUSED(channel_id); + iwdt_err_t err; + + /* Reset counter */ + err = R_IWDT_Control(IWDT_CMD_REFRESH_COUNTING, NULL); + if (err != IWDT_SUCCESS) { + return -EIO; + } + + return 0; +} + +static int wdt_iwdt_rx_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg) +{ + struct wdt_iwdt_rx_data *data = dev->data; + + if (cfg->window.min > cfg->window.max || cfg->window.max == 0) { + return -EINVAL; + } + + if ((cfg->flags & ~WDT_RENESAS_RX_SUPPORTED_FLAGS) != 0) { + return -ENOTSUP; + } + + if (cfg->callback != NULL && (cfg->flags & WDT_FLAG_RESET_MASK) != 0) { + LOG_ERR("WDT_FLAG_RESET_NONE should be chosen in case of interrupt response"); + return -ENOTSUP; + } + +#ifdef CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE + /* In auto-start mode, IWDT is started by OFS setting when the chip is reset. + * So timeout and other parameters must be configured via Kconfig. + * Runtime configuration is ignored. + */ + if (CONFIG_WDT_RENESAS_RX_OFS0_IRQ_SEL_IWDTRSTIRQS == 0) { + if ((cfg->flags & WDT_FLAG_RESET_MASK) != WDT_FLAG_RESET_NONE) { + LOG_ERR("Reset flag is not consistent with OFS setting"); + return -EINVAL; + } + } else if (CONFIG_WDT_RENESAS_RX_OFS0_IRQ_SEL_IWDTRSTIRQS == 1) { + if ((cfg->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_NONE) { + LOG_ERR("Reset flag is not consistent with OFS setting"); + return -EINVAL; + } + } else { + LOG_ERR("Invalid OFS setting"); + return -EINVAL; + } + + LOG_WRN("IWDT is auto-started by OFS. Timeout and other parameters must be configured via " + "Kconfig, runtime configuration is ignored."); +#ifdef CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI + data->callback = cfg->callback; +#endif + data->timeout_installed = true; + return 0; +#else /* CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE */ + const struct wdt_iwdt_rx_config *iwdt_cfg = dev->config; + uint32_t clock_rate; + int ret; + + /* Get the iwdt clock rate in hz */ + ret = clock_control_get_rate(iwdt_cfg->clock_dev, NULL, &clock_rate); + if (ret != 0) { + return ret; + } + + uint32_t clock_rate_khz = clock_rate / 1000; + + const uint16_t timeout_period[4] = {128, 512, 1024, 2048}; + const uint16_t clock_divide[6][2] = {{IWDT_CLOCK_DIV_1, 1}, {IWDT_CLOCK_DIV_16, 16}, + {IWDT_CLOCK_DIV_32, 32}, {IWDT_CLOCK_DIV_64, 64}, + {IWDT_CLOCK_DIV_128, 128}, {IWDT_CLOCK_DIV_256, 256}}; + int16_t last_error = INT16_MAX; + int32_t error; + uint16_t iwdt_tops = 0; + uint16_t iwdt_clock_div = 0; + uint16_t iwdt_timeout = ((uint32_t)timeout_period[0] * clock_divide[0][1]) / clock_rate_khz; + + for (int idx_p = 0; idx_p < 4; idx_p++) { + for (int idx_d = 0; idx_d < 6; idx_d++) { + iwdt_timeout = ((uint32_t)timeout_period[idx_p] * clock_divide[idx_d][1]) / + clock_rate_khz; + error = cfg->window.max - iwdt_timeout; + + if (error < 0) { + break; + } + + if (error < last_error) { + last_error = error; + iwdt_tops = idx_p; + iwdt_clock_div = clock_divide[idx_d][0]; + } + } + } + + data->iwdt_config.timeout = iwdt_tops; + data->iwdt_config.iwdtclk_div = iwdt_clock_div; + data->iwdt_config.window_start = IWDT_WINDOW_START; + data->iwdt_config.window_end = IWDT_WINDOW_END; + data->iwdt_config.timeout_control = + (cfg->flags & WDT_FLAG_RESET_MASK) != 0 ? IWDT_TIMEOUT_RESET : IWDT_TIMEOUT_NMI; + data->iwdt_config.count_stop_enable = IWDT_COUNT_STOP_DISABLE; + + data->timeout_installed = true; + +#if CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI + data->callback = cfg->callback; +#endif + return 0; + +#endif /* CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE */ +} + +static int wdt_iwdt_rx_setup(const struct device *dev, uint8_t options) +{ + struct wdt_iwdt_rx_data *data = dev->data; + + if (!data->timeout_installed) { + return -EINVAL; + } + +#ifdef CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI + nmi_enable(IWDT_NMI_VECTOR, (nmi_callback_t)wdt_iwdt_isr, (void *)dev); +#endif /* CONFIG_WDT_RENESAS_RX_IWDT_USE_NMI */ + +#if CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE + LOG_WRN("WDT is configured in auto-start mode, setup via API is not supported"); + return 0; +#else /* CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE */ + + iwdt_err_t err; + int ret; + + if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) { + return -ENOTSUP; + } + + if (options & WDT_OPT_PAUSE_IN_SLEEP) { + data->iwdt_config.count_stop_enable = IWDT_COUNT_STOP_ENABLE; + } else { + data->iwdt_config.count_stop_enable = IWDT_COUNT_STOP_DISABLE; + } + + err = R_IWDT_Open(&data->iwdt_config); + if (err != IWDT_SUCCESS) { + return -EINVAL; + } + + ret = wdt_iwdt_rx_feed(dev, 0); + if (ret != 0) { + return ret; + } + + return 0; +#endif /* CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE */ +} + +static DEVICE_API(wdt, wdt_iwdt_rx_api) = { + .disable = wdt_iwdt_rx_disable, + .feed = wdt_iwdt_rx_feed, + .install_timeout = wdt_iwdt_rx_install_timeout, + .setup = wdt_iwdt_rx_setup, +}; + +#define IWDT_RENESAS_RX_DEFINE(idx) \ + static struct wdt_iwdt_rx_config iwdt_rx_cfg##idx = { \ + .regs = (struct st_iwdt *)DT_REG_ADDR(IWDT_NODELABEL), \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(idx)), \ + }; \ + static struct wdt_iwdt_rx_data iwdt_rx_data##idx = { \ + .timeout_installed = false, \ + .iwdt_config = {.count_stop_enable = IWDT_COUNT_STOP_DISABLE, \ + .timeout_control = IWDT_TIMEOUT_RESET}, \ + }; \ + \ + DEVICE_DT_DEFINE(idx, NULL, NULL, &iwdt_rx_data##idx, &iwdt_rx_cfg##idx, POST_KERNEL, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_iwdt_rx_api); + +DT_FOREACH_STATUS_OKAY(renesas_rx_iwdt, IWDT_RENESAS_RX_DEFINE); diff --git a/dts/bindings/watchdog/renesas,rx-iwdt.yaml b/dts/bindings/watchdog/renesas,rx-iwdt.yaml new file mode 100644 index 0000000000000..bcfd1b400c611 --- /dev/null +++ b/dts/bindings/watchdog/renesas,rx-iwdt.yaml @@ -0,0 +1,39 @@ +# Copyright (c) 2025 Renesas Electronics Corporation and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX Independent Watchdog + +compatible: "renesas,rx-iwdt" + +include: base.yaml + +properties: + reg: + required: true + + clocks: + required: true + + window-start: + required: true + type: int + enum: [0, 0x1000, 0x2000, 0x3000] + description: | + The start of the window in clock cycles. The watchdog will reset the system + if the watchdog is not refreshed within the window. + - 0: 25% + - 0x1000: 50% + - 0x2000: 75% + - 0x3000: 100% (window end position is not specified.) + + window-end: + required: true + type: int + enum: [0, 0x100, 0x200, 0x300] + description: | + The end of the window in clock cycles. The watchdog will reset the system + if the watchdog is not refreshed within the window. + - 0: 75% + - 0x200: 50% + - 0x200: 25% + - 0x300: 0% (window start position is not specified.) diff --git a/dts/rx/renesas/rx-qemu.dtsi b/dts/rx/renesas/rx-qemu.dtsi index 5652ceaa66b27..27ef92faf950a 100644 --- a/dts/rx/renesas/rx-qemu.dtsi +++ b/dts/rx/renesas/rx-qemu.dtsi @@ -41,8 +41,12 @@ <0x00872f0 0x02>, <0x0087500 0x0f>, <0x0087510 0x01>, - <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + <0x0087514 0x01>, + <0x0087580 0x01>, + <0x0087581 0x01>, + <0x0087582 0x01>; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0", "NMISR", + "NMIER", "NMICLR"; swint1: swint1@872e0 { compatible = "renesas,rx-swint"; diff --git a/dts/rx/renesas/rx130-common.dtsi b/dts/rx/renesas/rx130-common.dtsi index 86e8232c04d2a..50167ca423515 100644 --- a/dts/rx/renesas/rx130-common.dtsi +++ b/dts/rx/renesas/rx130-common.dtsi @@ -41,8 +41,12 @@ <0x00872f0 0x02>, <0x0087500 0x0f>, <0x0087510 0x01>, - <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + <0x0087514 0x01>, + <0x0087580 0x01>, + <0x0087581 0x01>, + <0x0087582 0x01>; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR","IRQFLTE","IRQFLTC0", "NMISR", + "NMIER", "NMICLR"; swint1: swint1@872e0 { compatible = "renesas,rx-swint"; @@ -839,5 +843,12 @@ zephyr,memory-region = "OFSM"; status = "okay"; }; + + iwdt: watchdog@88030 { + compatible = "renesas,rx-iwdt"; + reg = <0x00088030 0x10>; + clocks = <&iwdtlsclk 0 0>; + status = "disabled"; + }; }; }; diff --git a/dts/rx/renesas/rx261-common.dtsi b/dts/rx/renesas/rx261-common.dtsi index 1f978d52fe4e1..7c5a09e6305fa 100644 --- a/dts/rx/renesas/rx261-common.dtsi +++ b/dts/rx/renesas/rx261-common.dtsi @@ -40,8 +40,12 @@ <0x00872f0 0x02>, <0x0087500 0x0f>, <0x0087510 0x01>, - <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + <0x0087514 0x01>, + <0x0087580 0x01>, + <0x0087581 0x01>, + <0x0087582 0x01>; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0", "NMISR", + "NMIER", "NMICLR"; swint1: swint1@872e0 { compatible = "renesas,rx-swint"; diff --git a/include/zephyr/arch/rx/linker.ld b/include/zephyr/arch/rx/linker.ld index f0cdc4b18c9a9..fc66cdfd30f4f 100644 --- a/include/zephyr/arch/rx/linker.ld +++ b/include/zephyr/arch/rx/linker.ld @@ -298,9 +298,10 @@ SECTIONS _end = .; } GROUP_LINK_IN(RAMABLE_REGION) -#include _ebss = . ; +#include + _image_ram_end = .; _end = .; PROVIDE(__end = _end); diff --git a/include/zephyr/arch/rx/sw_nmi_table.h b/include/zephyr/arch/rx/sw_nmi_table.h new file mode 100644 index 0000000000000..e1eb675059149 --- /dev/null +++ b/include/zephyr/arch/rx/sw_nmi_table.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_RX_SW_NMI_TABLE_H +#define ZEPHYR_INCLUDE_ARCH_RX_SW_NMI_TABLE_H + +#include +#include + +#define NMI_TABLE_SIZE (5) + +typedef void (*nmi_callback_t)(void *arg); + +struct nmi_vector_entry { + nmi_callback_t callback; + void *arg; +}; + +extern struct nmi_vector_entry _nmi_vector_table[NMI_TABLE_SIZE]; + +void nmi_enable(uint8_t nmi_vector, nmi_callback_t callback, void *arg); +int get_nmi_request(void); +void handle_nmi(uint8_t nmi_vector); + +#endif /* ZEPHYR_INCLUDE_ARCH_RX_SW_NMI_TABLE_H */ diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 2ce3656a0e0c2..31c65d1e9402d 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -371,4 +371,9 @@ config USE_RX_RDP_ADC help Enable RX RDP ADC driver +config USE_RX_RDP_IWDT + bool + help + Enable RX RDP IWDT driver + endif # HAS_RENESAS_RX_RDP diff --git a/soc/renesas/rx/rx130/Kconfig b/soc/renesas/rx/rx130/Kconfig index 566ae64f1dfff..66f481b78cf8a 100644 --- a/soc/renesas/rx/rx130/Kconfig +++ b/soc/renesas/rx/rx130/Kconfig @@ -9,3 +9,168 @@ config SOC_SERIES_RX130 select HAS_RENESAS_RX_RDP select CLOCK_CONTROL select SOC_EARLY_INIT_HOOK + +if SOC_SERIES_RX130 +if WDT_RENESAS_RX_IWDT_AUTO_START_MODE + +choice + prompt "IWDT OFS0 Start Mode Select" + default WDT_RENESAS_RX_STARTMODE_HALT + +config WDT_RENESAS_RX_STARTMODE_AUTO_ACTIVATE + bool "IWDT is automatically activated in auto-start mode after a reset" + +config WDT_RENESAS_RX_STARTMODE_HALT + bool "IWDT is halted after a reset" + +endchoice + +config WDT_RENESAS_RX_OFS0_IWDTSTRT + int + default 0 if WDT_RENESAS_RX_STARTMODE_HALT + default 1 if WDT_RENESAS_RX_STARTMODE_AUTO_ACTIVATE + +choice + prompt "IWDT Timeout Period Select" + default WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_2048 + +config WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_128 + bool "128 cycles" + +config WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_512 + bool "512 cycles" + +config WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_1024 + bool "1024 cycles" + +config WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_2048 + bool "2048 cycles" + +endchoice + +config WDT_RENESAS_RX_OFS0_TIMEOUT_IWDTTOPS + int + default 0 if WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_128 + default 1 if WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_512 + default 2 if WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_1024 + default 3 if WDT_RENESAS_RX_OFS0_TIMEOUT_PERIOD_2048 + +choice + prompt "IWDT Clock Divide Ratio Select" + default WDT_RENESAS_RX_OFS0_CLKDIV_128 + +config WDT_RENESAS_RX_OFS0_CLKDIV_1 + bool "No division" + +config WDT_RENESAS_RX_OFS0_CLKDIV_16 + bool "Divide-by-16" + +config WDT_RENESAS_RX_OFS0_CLKDIV_32 + bool "Divide-by-32" + +config WDT_RENESAS_RX_OFS0_CLKDIV_64 + bool "Divide-by-64" + +config WDT_RENESAS_RX_OFS0_CLKDIV_128 + bool "Divide-by-128" + +config WDT_RENESAS_RX_OFS0_CLKDIV_256 + bool "Divide-by-256" + +endchoice + +config WDT_RENESAS_RX_OFS0_CLKDIV_IWDTCKS + int + default 0 if WDT_RENESAS_RX_OFS0_CLKDIV_1 + default 2 if WDT_RENESAS_RX_OFS0_CLKDIV_16 + default 3 if WDT_RENESAS_RX_OFS0_CLKDIV_32 + default 4 if WDT_RENESAS_RX_OFS0_CLKDIV_64 + default 15 if WDT_RENESAS_RX_OFS0_CLKDIV_128 + default 5 if WDT_RENESAS_RX_OFS0_CLKDIV_256 + +choice + prompt "IWDT Window Start Position Select" + default WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_100 + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_25 + bool "25%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_50 + bool "50%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_75 + bool "75%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_100 + bool "100% (window start position is not specified.)" + +endchoice + +config WDT_RENESAS_RX_OFS0_WINDOW_STRT_IWDTRPSS + int + default 0 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_25 + default 1 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_50 + default 2 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_75 + default 3 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_STRT_100 + +choice + prompt "IWDT Window End Position Select" + default WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_0 + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_75 + bool "75%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_50 + bool "50%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_25 + bool "25%" + +config WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_0 + bool "0% (window end position is not specified.)" + +endchoice + +config WDT_RENESAS_RX_OFS0_WINDOW_END_IWDTRPES + int + default 0 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_75 + default 1 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_50 + default 2 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_25 + default 3 if WDT_RENESAS_RX_OFS0_IWDT_WINDOW_END_0 + +choice + prompt "IWDT Reset Interrupt Request Select" + default WDT_RENESAS_RX_OFS0_IRQ_ENA + +config WDT_RENESAS_RX_OFS0_IRQ_ENA + bool "Non-maskable interrupt request output is enabled." + +config WDT_RENESAS_RX_OFS0_RESET_ENA + bool "Reset output is enabled." + +endchoice + +config WDT_RENESAS_RX_OFS0_IRQ_SEL_IWDTRSTIRQS + int + default 0 if WDT_RENESAS_RX_OFS0_IRQ_ENA + default 1 if WDT_RENESAS_RX_OFS0_RESET_ENA + +choice + prompt "IWDT Sleep Mode Count Stop Control" + default WDT_RENESAS_RX_OFS0_COUNT_STOP_DIS + +config WDT_RENESAS_RX_OFS0_COUNT_STOP_ENA + bool "Count stop is disabled" + +config WDT_RENESAS_RX_OFS0_COUNT_STOP_DIS + bool "Count is stopped at a transition to sleep mode, software standby mode, or deep sleep mode." + +endchoice + +config WDT_RENESAS_RX_OFS0_IWDTSLCSTP + int "IWDT Sleep Mode Count Stop Control" + default 0 if WDT_RENESAS_RX_OFS0_COUNT_STOP_DIS + default 1 if WDT_RENESAS_RX_OFS0_COUNT_STOP_ENA + +endif # WDT_RENESAS_RX_IWDT_AUTO_START_MODE +endif # SOC_SERIES_RX130 diff --git a/soc/renesas/rx/rx130/ofsm.c b/soc/renesas/rx/rx130/ofsm.c deleted file mode 100644 index 70fc502503e7e..0000000000000 --- a/soc/renesas/rx/rx130/ofsm.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH - * Copyright (c) 2024 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * - * Option-Setting Memory for the RX. This region of memory (located in flash) - * determines the state of the MCU after reset and can not be changed on runtime - * - * All registers are set to 0xffffffff by default, which are "safe" settings. - * Please refer to the Renesas RX Group User's Manual before changing any of - * the values as some changes can be permanent or lock access to the device. - * - * Address range: 0xFE7F5D00 to 0xFE7F5D7F (128 Bytes) - */ - -#define __OFS_MDE __attribute__((section(".ofs_mde"))) - -/* Endian Select Register (MDE) at 0xFE7F5D00 - * - * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little - * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) - * - * b6-b4 (Bank Mode Select) indicate whether the flash is operated in - * Dual mode (0 0 0) or Linear mode (1 1 1). - * - * all other bits are reserved and have to be set to 1 - */ -const unsigned long __OFS_MDE __MDEreg = 0xffffffff; /* little */ - -struct st_ofs0 { - unsigned long res0: 1; - unsigned long IWDTSTRT: 1; - unsigned long IWDTTOPS: 2; - unsigned long IWDTCKS: 4; - unsigned long IWDTRPES: 2; - unsigned long IWDTRPSS: 2; - unsigned long IWDTRSTIRQS: 1; - unsigned long res1: 1; - unsigned long IWDTSLCSTP: 1; - unsigned long res2: 16; -}; - -const unsigned long __OFS_MDE __OFS0reg = 0xffffffff; - -/* Option Function Select Register 1 (OFS1) at 0xFE7F5D08 (Voltage detection and - * HOCO) - */ -const unsigned long __OFS_MDE __OFS1reg = 0xffffffff; diff --git a/soc/renesas/rx/rx130/ofsm.h b/soc/renesas/rx/rx130/ofsm.h new file mode 100644 index 0000000000000..f0888fa8dee39 --- /dev/null +++ b/soc/renesas/rx/rx130/ofsm.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Option setting header file for Renesas RX130 + */ + +/* + * Option-Setting Memory for the RX. This region of memory (located in flash) + * determines the state of the MCU after reset and can not be changed on runtime + * + * All registers are set to 0xffffffff by default, which are "safe" settings. + * Please refer to the Renesas RX Group User's Manual before changing any of + * the values as some changes can be permanent or lock access to the device. + * + * Address range: 0xFFFFFF80 to 0xFFFFFF8F + */ + +/* Endian Select Register (MDE) at 0xFFFFFF80 + * + * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little + * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) + * + * all other bits are reserved and have to be set to 1 + */ +#define SOC_RX_MDE (0xFFFFFFFFUL) /* little endian */ + +/* Option Function Select Register 0 (OFS0) + * This section sets the IWDT (Independent Watchdog Timer) behavior immediately after reset + * by programming the OFS0 register. When enabled, IWDT starts counting automatically + * starts after a reset. + */ + +#ifdef CONFIG_WDT_RENESAS_RX_IWDT_AUTO_START_MODE +#define SOC_RX_OFS0 \ + ((CONFIG_WDT_RENESAS_RX_OFS0_IWDTSTRT << 1) | /* bit 1 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_TIMEOUT_IWDTTOPS & 0x3) << 2) | /* bits 2-3 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_CLKDIV_IWDTCKS & 0xF) << 4) | /* bits 4-7 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_WINDOW_END_IWDTRPES & 0x3) << 8) | /* bits 8-9 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_WINDOW_STRT_IWDTRPSS & 0x3) << 10) | /* bits 10-11 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_IRQ_SEL_IWDTRSTIRQS & 0x1) << 12) | /* bit 12 */ \ + ((CONFIG_WDT_RENESAS_RX_OFS0_IWDTSLCSTP & 0x1) << 14) | /* bit 14 */ \ + 0xFFFFA001UL /* reserved bits 0,13,15..31 */ \ + ) +#else +#define SOC_RX_OFS0 (0xFFFFFFFFUL) +#endif + +/* Option Function Select Register 1 (OFS1) (Voltage detection and HOCO) + */ +#define SOC_RX_OFS1 (0xFFFFFFFFUL) diff --git a/soc/renesas/rx/rx261/ofsm.h b/soc/renesas/rx/rx261/ofsm.h new file mode 100644 index 0000000000000..7f41641a63440 --- /dev/null +++ b/soc/renesas/rx/rx261/ofsm.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Option setting header file for Renesas RX261 + */ + +#include + +/* + * Option-Setting Memory for the RX. This region of memory (located in flash) + * determines the state of the MCU after reset and can not be changed on runtime + * + * All registers are set to 0xffffffff by default, which are "safe" settings. + * Please refer to the Renesas RX Group User's Manual before changing any of + * the values as some changes can be permanent or lock access to the device. + * + * Address range: 0xFFFFFF80 to 0xFFFFFF8F + */ + +/* Endian Select Register (MDE) at 0xFFFFFF80 + * + * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little + * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) + * + * all other bits are reserved and have to be set to 1 + */ +#define SOC_RX_MDE (0xFFFFFFFFUL) /* little endian */ + +/* Option Function Select Register 0 (OFS0) + * This section sets the IWDT (Independent Watchdog Timer) behavior immediately after reset + * by programming the OFS0 register. When enabled, IWDT starts counting automatically + * starts after a reset. + */ +#define SOC_RX_OFS0 (0xFFFFFFFFUL) + +/* Option Function Select Register 1 (OFS1) (Voltage detection and HOCO) + */ + +#define RX_HOCO_FREQ DT_PROP(DT_NODELABEL(hoco), clock_frequency) + +#if (RX_HOCO_FREQ == 24000000) +#define SOC_OFS1_HOCO 0b10 +#elif (RX_HOCO_FREQ == 32000000) +#define SOC_OFS1_HOCO 0b11 +#elif (RX_HOCO_FREQ == 48000000) +#define SOC_OFS1_HOCO 0b01 +#elif (RX_HOCO_FREQ == 64000000) +#define SOC_OFS1_HOCO 0b00 +#else +#error "Unsupported HOCO clock frequency (must be 24/32/48/64 MHz)" +#endif + +#define SOC_RX_OFS1 ((SOC_OFS1_HOCO << 12) | 0xFFFFCFFFUL) diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/Kconfig b/tests/drivers/watchdog/wdt_basic_reset_none/Kconfig index 8bce14f84e586..d69fc3ac880d0 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/Kconfig +++ b/tests/drivers/watchdog/wdt_basic_reset_none/Kconfig @@ -20,3 +20,15 @@ config TEST_WDT_SLEEP_TIME The units for this value will change based on the watchdog driver being tested. Most drivers represent this as milliseconds due to the max window reaching the millisecond feed window. + +config TEST_WDT_SETUP_FLAGS + int "WDT setup flags for test, selectable options are: No flags (0x0U), WDT_OPT_PAUSE_IN_SLEEP (0x1U), WDT_OPT_PAUSE_HALTED_BY_DBG (0x2U)" + default 2 + help + Set the watchdog setup flags for the test. + +config TEST_WDT_TIMEOUT_UNIT_TICKS + bool "Use watchdog timeout unit in ticks" + default n + help + Enable this option to configure the watchdog timeout unit in system ticks diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/boards/app_ewm.conf b/tests/drivers/watchdog/wdt_basic_reset_none/boards/app_ewm.conf new file mode 100644 index 0000000000000..b22326a40f71d --- /dev/null +++ b/tests/drivers/watchdog/wdt_basic_reset_none/boards/app_ewm.conf @@ -0,0 +1,2 @@ +CONFIG_TEST_WDT_SETUP_FLAGS=0 +CONFIG_TEST_WDT_TIMEOUT_UNIT_TICKS=y diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/boards/rsk_rx130_512kb.conf b/tests/drivers/watchdog/wdt_basic_reset_none/boards/rsk_rx130_512kb.conf new file mode 100644 index 0000000000000..71c236f5ee676 --- /dev/null +++ b/tests/drivers/watchdog/wdt_basic_reset_none/boards/rsk_rx130_512kb.conf @@ -0,0 +1 @@ +CONFIG_TEST_WDT_SETUP_FLAGS=0 diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/src/main.c b/tests/drivers/watchdog/wdt_basic_reset_none/src/main.c index 9fa744d0bba8f..75efc18411499 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/src/main.c +++ b/tests/drivers/watchdog/wdt_basic_reset_none/src/main.c @@ -22,15 +22,14 @@ #define WDT_FEED_TRIES 2 #define WDT_TEST_CB_TEST_VALUE 0xCB #define WDT_TIMEOUT_VALUE CONFIG_TEST_WDT_MAX_WINDOW_TIME + 10 +#define WDT_SETUP_FLAGS CONFIG_TEST_WDT_SETUP_FLAGS -#if defined(CONFIG_WDT_NXP_EWM) -#define WDT_SETUP_FLAGS 0 -#define WDT_TIMEOUT K_TICKS(WDT_TIMEOUT_VALUE) -#define SLEEP_TIME K_TICKS(CONFIG_TEST_WDT_SLEEP_TIME) +#if defined(CONFIG_TEST_WDT_TIMEOUT_UNIT_TICKS) +#define WDT_TIMEOUT K_TICKS(WDT_TIMEOUT_VALUE) +#define SLEEP_TIME K_TICKS(CONFIG_TEST_WDT_SLEEP_TIME) #else -#define WDT_SETUP_FLAGS WDT_OPT_PAUSE_HALTED_BY_DBG -#define WDT_TIMEOUT K_MSEC(WDT_TIMEOUT_VALUE) -#define SLEEP_TIME K_MSEC(CONFIG_TEST_WDT_SLEEP_TIME) +#define WDT_TIMEOUT K_MSEC(WDT_TIMEOUT_VALUE) +#define SLEEP_TIME K_MSEC(CONFIG_TEST_WDT_SLEEP_TIME) #endif static struct wdt_timeout_cfg m_cfg_wdt0; diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml index 1e6ae08b31a18..ce4ddeb6eb5d9 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml @@ -27,7 +27,9 @@ tests: - frdm_mcxw72/mcxw727c/cpu0 - mimxrt1180_evk/mimxrt1189/cm33 - mimxrt1180_evk/mimxrt1189/cm7 - extra_args: DTC_OVERLAY_FILE="boards/app_ewm.overlay" + extra_args: + - EXTRA_CONF_FILE="boards/app_ewm.conf" + - DTC_OVERLAY_FILE="boards/app_ewm.overlay" extra_configs: - CONFIG_TEST_WDT_MAX_WINDOW_TIME=254 - CONFIG_TEST_WDT_SLEEP_TIME=68 @@ -37,7 +39,9 @@ tests: - frdm_ke17z integration_platforms: - frdm_ke17z - extra_args: DTC_OVERLAY_FILE="boards/frdm_ke1xz.overlay" + extra_args: + - EXTRA_CONF_FILE="boards/app_ewm.conf" + - DTC_OVERLAY_FILE="boards/frdm_ke1xz.overlay" extra_configs: - CONFIG_TEST_WDT_MAX_WINDOW_TIME=254 - CONFIG_TEST_WDT_SLEEP_TIME=68