diff --git a/drivers/flash/flash_stm32_ex_op.c b/drivers/flash/flash_stm32_ex_op.c
index 2d5f754261624..e91eaf939e18e 100644
--- a/drivers/flash/flash_stm32_ex_op.c
+++ b/drivers/flash/flash_stm32_ex_op.c
@@ -24,6 +24,13 @@ int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 
+#if defined(FLASH_CR_OBL_LAUNCH)
+	/* Force the option byte loading before locking */
+	if (enable) {
+		regs->CR |= FLASH_CR_OBL_LAUNCH;
+	}
+#endif
+
 #if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 or H7 */
 	if (enable) {
 		regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
diff --git a/drivers/flash/flash_stm32g4x.c b/drivers/flash/flash_stm32g4x.c
index 3c26874b1a9ce..904e859e5f69c 100644
--- a/drivers/flash/flash_stm32g4x.c
+++ b/drivers/flash/flash_stm32g4x.c
@@ -17,6 +17,8 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 #include <zephyr/init.h>
 #include <soc.h>
 #include <stm32_ll_system.h>
+#include <stm32_ll_cortex.h>
+#include <stm32_ll_pwr.h>
 
 #include "flash_stm32.h"
 
@@ -280,14 +282,6 @@ int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
 	/* Make sure previous write is completed. */
 	barrier_dsync_fence_full();
 
-	rc = flash_stm32_wait_flash_idle(dev);
-	if (rc < 0) {
-		return rc;
-	}
-
-	/* Force the option byte loading */
-	regs->CR |= FLASH_CR_OBL_LAUNCH;
-
 	return flash_stm32_wait_flash_idle(dev);
 }
 
@@ -326,6 +320,15 @@ void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
 {
 	flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
 				       (uint32_t)level << FLASH_OPTR_RDP_Pos);
+
+	/*
+	 * POR needed to reload option bytes, done at runtime by entering standby mode
+	 * /!\ make sure a wakeup source is configured!
+	 */
+	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+	LL_LPM_EnableDeepSleep();
+	/* enter SLEEP mode : WFE or WFI */
+	k_cpu_idle();
 }
 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
 
diff --git a/drivers/flash/flash_stm32l4x.c b/drivers/flash/flash_stm32l4x.c
index 91f496d81d98c..56bbef89bb2b5 100644
--- a/drivers/flash/flash_stm32l4x.c
+++ b/drivers/flash/flash_stm32l4x.c
@@ -18,6 +18,9 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 #include <zephyr/sys/barrier.h>
 #include <zephyr/init.h>
 #include <soc.h>
+#include <stm32_ll_system.h>
+#include <stm32_ll_cortex.h>
+#include <stm32_ll_pwr.h>
 
 #include "flash_stm32.h"
 
@@ -271,14 +274,6 @@ int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
 	/* Make sure previous write is completed. */
 	barrier_dsync_fence_full();
 
-	rc = flash_stm32_wait_flash_idle(dev);
-	if (rc < 0) {
-		return rc;
-	}
-
-	/* Force the option byte loading */
-	regs->CR |= FLASH_CR_OBL_LAUNCH;
-
 	return flash_stm32_wait_flash_idle(dev);
 }
 
@@ -317,6 +312,15 @@ void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
 {
 	flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
 				       (uint32_t)level << FLASH_OPTR_RDP_Pos);
+
+	/*
+	 * POR needed to reload option bytes, done at runtime by entering standby mode
+	 * /!\ make sure a wakeup source is configured!
+	 */
+	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+	LL_LPM_EnableDeepSleep();
+	/* enter SLEEP mode : WFE or WFI */
+	k_cpu_idle();
 }
 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */