diff --git a/drivers/i2s/i2s_stm32_sai.c b/drivers/i2s/i2s_stm32_sai.c
index f692af120c9d3..dc41dd35fc1c7 100644
--- a/drivers/i2s/i2s_stm32_sai.c
+++ b/drivers/i2s/i2s_stm32_sai.c
@@ -286,7 +286,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
 	hdma->Init.Request = dma_cfg.dma_slot;
 	hdma->Init.Mode = DMA_NORMAL;
 
-#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X)
+#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X) ||                  \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 	hdma->Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 	hdma->Init.Priority = DMA_PRIORITY_HIGH;
@@ -310,7 +311,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
 	if (stream->dma_cfg.channel_direction == (enum dma_channel_direction)MEMORY_TO_PERIPHERAL) {
 		hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
 
-#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X)
+#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) &&                \
+	!defined(CONFIG_SOC_SERIES_STM32G4X)
 		hdma->Init.SrcInc = DMA_SINC_INCREMENTED;
 		hdma->Init.DestInc = DMA_DINC_FIXED;
 #endif
@@ -319,7 +321,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
 	} else {
 		hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
 
-#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X)
+#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) &&                \
+	!defined(CONFIG_SOC_SERIES_STM32G4X)
 		hdma->Init.SrcInc = DMA_SINC_FIXED;
 		hdma->Init.DestInc = DMA_DINC_INCREMENTED;
 #endif
@@ -338,7 +341,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
 		LOG_ERR("HAL_DMA_ConfigChannelAttributes: <Failed>");
 		return -EIO;
 	}
-#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X)
+#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) &&              \
+	!defined(CONFIG_SOC_SERIES_STM32G4X)
 	if (HAL_DMA_ConfigChannelAttributes(&dev_data->hdma, DMA_CHANNEL_NPRIV) != HAL_OK) {
 		LOG_ERR("HAL_DMA_ConfigChannelAttributes: <Failed>");
 		return -EIO;
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
index ec83a77392638..79c7838509ce3 100644
--- a/dts/arm/st/g4/stm32g4.dtsi
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -2,6 +2,7 @@
  * Copyright (c) 2021 The Chromium OS Authors
  * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
  * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Mario Paja
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -674,6 +675,28 @@
 			interrupts = <63 0>;
 			status = "disabled";
 		};
+
+		sai1_a: sai1@40015404 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015404 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21)>;
+			dmas = <&dma1 1 108 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+					     STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
+
+		sai1_b: sai1@40015424 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015424 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21)>;
+			dmas = <&dma1 2 109 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+					     STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
 	};
 
 	die_temp: dietemp {
diff --git a/samples/drivers/i2s/output/boards/nucleo_g431kb.conf b/samples/drivers/i2s/output/boards/nucleo_g431kb.conf
new file mode 100644
index 0000000000000..4f3f73a1e06a5
--- /dev/null
+++ b/samples/drivers/i2s/output/boards/nucleo_g431kb.conf
@@ -0,0 +1 @@
+CONFIG_HEAP_MEM_POOL_SIZE=4192
diff --git a/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay b/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay
new file mode 100644
index 0000000000000..acb9b8891a554
--- /dev/null
+++ b/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2s-tx = &sai1_a;
+	};
+};
+
+&pll {
+	/* 44.1KHz (-0.03% Error) */
+	div-q = <8>;
+};
+
+/* MCLK is not enabled */
+/* SAI1_A MCLK (PB8) is not available on the Arduino Nano header */
+&sai1_a {
+	pinctrl-0 = <&sai1_sd_a_pa10 &sai1_fs_a_pa9 &sai1_sck_a_pa8>;
+	pinctrl-names = "default";
+	status = "okay";
+	mclk-divider = "div-256";
+	dma-names = "tx";
+};
+
+&dma1{
+	status = "okay";
+};
+
+&dmamux1{
+	status = "okay";
+};
+
+/* I2C2 SCL conflicts with SAI1_A FS */
+/* I2C2 SDA conflicts with SAI1_A SCK */
+&i2c2 {
+	status = "disabled";
+};