From 558ddcf716c8120358eef7c83ee4e4953760975f Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Tue, 22 Jul 2025 09:21:51 +0200 Subject: [PATCH 1/3] dts: st: g4: add sai node for stm32g4xx Define SAI1 node A & B for STM32G4xx series Signed-off-by: Mario Paja --- dts/arm/st/g4/stm32g4.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index ec83a77392638..79c7838509ce3 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -2,6 +2,7 @@ * Copyright (c) 2021 The Chromium OS Authors * Copyright (c) 2019 Richard Osterloh * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Mario Paja * * SPDX-License-Identifier: Apache-2.0 */ @@ -674,6 +675,28 @@ interrupts = <63 0>; status = "disabled"; }; + + sai1_a: sai1@40015404 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015404 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>; + dmas = <&dma1 1 108 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; + + sai1_b: sai1@40015424 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015424 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>; + dmas = <&dma1 2 109 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; }; die_temp: dietemp { From 13b17ed0e0222ad809112c2bc667472c6f06f79c Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Mon, 8 Sep 2025 08:43:11 +0200 Subject: [PATCH 2/3] drivers: i2s: stm32_sai: add support for stm32g4xx series STM32G4xx series shares several DMA configurations with the other platforms. These changes aim to enable platform specific DMA configuration and align them to other platforms. Signed-off-by: Mario Paja --- drivers/i2s/i2s_stm32_sai.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/i2s/i2s_stm32_sai.c b/drivers/i2s/i2s_stm32_sai.c index f692af120c9d3..dc41dd35fc1c7 100644 --- a/drivers/i2s/i2s_stm32_sai.c +++ b/drivers/i2s/i2s_stm32_sai.c @@ -286,7 +286,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) hdma->Init.Request = dma_cfg.dma_slot; hdma->Init.Mode = DMA_NORMAL; -#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X) +#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X) || \ + defined(CONFIG_SOC_SERIES_STM32G4X) hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma->Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma->Init.Priority = DMA_PRIORITY_HIGH; @@ -310,7 +311,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) if (stream->dma_cfg.channel_direction == (enum dma_channel_direction)MEMORY_TO_PERIPHERAL) { hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; -#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) +#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \ + !defined(CONFIG_SOC_SERIES_STM32G4X) hdma->Init.SrcInc = DMA_SINC_INCREMENTED; hdma->Init.DestInc = DMA_DINC_FIXED; #endif @@ -319,7 +321,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) } else { hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; -#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) +#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \ + !defined(CONFIG_SOC_SERIES_STM32G4X) hdma->Init.SrcInc = DMA_SINC_FIXED; hdma->Init.DestInc = DMA_DINC_INCREMENTED; #endif @@ -338,7 +341,8 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) LOG_ERR("HAL_DMA_ConfigChannelAttributes: "); return -EIO; } -#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) +#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) && \ + !defined(CONFIG_SOC_SERIES_STM32G4X) if (HAL_DMA_ConfigChannelAttributes(&dev_data->hdma, DMA_CHANNEL_NPRIV) != HAL_OK) { LOG_ERR("HAL_DMA_ConfigChannelAttributes: "); return -EIO; From b0d7572db4ffad9ac9450dea8b97b037ec4aea22 Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Thu, 24 Jul 2025 11:06:33 +0200 Subject: [PATCH 3/3] samples: i2s: output: add nucleo_g431kb Add nucleo_g431kb board in samples/drivers/i2s/output Signed-off-by: Mario Paja --- .../i2s/output/boards/nucleo_g431kb.conf | 1 + .../i2s/output/boards/nucleo_g431kb.overlay | 40 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 samples/drivers/i2s/output/boards/nucleo_g431kb.conf create mode 100644 samples/drivers/i2s/output/boards/nucleo_g431kb.overlay diff --git a/samples/drivers/i2s/output/boards/nucleo_g431kb.conf b/samples/drivers/i2s/output/boards/nucleo_g431kb.conf new file mode 100644 index 0000000000000..4f3f73a1e06a5 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_g431kb.conf @@ -0,0 +1 @@ +CONFIG_HEAP_MEM_POOL_SIZE=4192 diff --git a/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay b/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay new file mode 100644 index 0000000000000..acb9b8891a554 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_g431kb.overlay @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2s-tx = &sai1_a; + }; +}; + +&pll { + /* 44.1KHz (-0.03% Error) */ + div-q = <8>; +}; + +/* MCLK is not enabled */ +/* SAI1_A MCLK (PB8) is not available on the Arduino Nano header */ +&sai1_a { + pinctrl-0 = <&sai1_sd_a_pa10 &sai1_fs_a_pa9 &sai1_sck_a_pa8>; + pinctrl-names = "default"; + status = "okay"; + mclk-divider = "div-256"; + dma-names = "tx"; +}; + +&dma1{ + status = "okay"; +}; + +&dmamux1{ + status = "okay"; +}; + +/* I2C2 SCL conflicts with SAI1_A FS */ +/* I2C2 SDA conflicts with SAI1_A SCK */ +&i2c2 { + status = "disabled"; +};