diff --git a/boards/renesas/mcb_rx26t/Kconfig.mcb_rx26t b/boards/renesas/mcb_rx26t/Kconfig.mcb_rx26t new file mode 100644 index 0000000000000..ecd0a6a52737c --- /dev/null +++ b/boards/renesas/mcb_rx26t/Kconfig.mcb_rx26t @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MCB_RX26T + select SOC_R5F526TFDDFP diff --git a/boards/renesas/mcb_rx26t/board.cmake b/boards/renesas/mcb_rx26t/board.cmake new file mode 100644 index 0000000000000..81690b2021ac8 --- /dev/null +++ b/boards/renesas/mcb_rx26t/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F526TF" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1") +board_runner_args(rfp "--device=RX200" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/mcb_rx26t/board.yml b/boards/renesas/mcb_rx26t/board.yml new file mode 100644 index 0000000000000..0348f1ff931d8 --- /dev/null +++ b/boards/renesas/mcb_rx26t/board.yml @@ -0,0 +1,5 @@ +board: + name: mcb_rx26t + vendor: renesas + socs: + - name: r5f526tfddfp diff --git a/boards/renesas/mcb_rx26t/doc/index.rst b/boards/renesas/mcb_rx26t/doc/index.rst new file mode 100644 index 0000000000000..b4b98c98ca864 --- /dev/null +++ b/boards/renesas/mcb_rx26t/doc/index.rst @@ -0,0 +1,156 @@ +.. zephyr:board:: mcb_rx26t + +Overview +******** + +MCB-RX26T Type B is a CPU board for motor control evaluation. By using this product in combination with +an inverter board, motor control using RX26T can be easily performed. + +**MCU Native Pin Access** + +The MCB-RX26T Type B includes: + +- CPU maximum operating frequency 120MHz, 32-bit RXv3 Core +- Package/Pin count: LFQFP/100 pin +- ROM/RAM: 512KB/48KB +- MCU input clock: 10MHz (Generate with external crystal oscillator) + +**System Control and Debugging** + +- Power supply: DC 5V,3.3V (selectable with jumper switch) Select one way automatically from the below + + - USB-powered (debug port) + - External power supply via standard input + +- Debugging support: + + - Via E2lite debugger with E2OB (Onboard debugger circuit) + +- Connector: + + - Inverter board connector + - USB connector for E2 OB + - SCI connector for Renesas Motor Workbench communication + - Through hole for CAN communication + - Through hole for SPI communication + - PMOD connectors + +- User LEDs and buttons: + + - Four User LEDs + - Power LED indicating availability of regulated power + - One Reset button + +Hardware +******** +Detailed hardware features can be found at: + +- RX26T MCU: `RX26T Group User's Manual Hardware`_ +- MCB-RX26T Type B: `MCB-RX26T Type B - User's Manual`_ + +Note: +The CPU used in the RX26T is based on the RXv3 core. However, the current version of the Zephyr kernel +only supports the RXv1 core. Since the RXv3 core is backward-compatible with RXv1, it works with this version. +But the following limitations apply: + +- FPU context saving is not supported. Do not use the FPU. +- Register bank save function is not supported. Do not use instructions for register bank save function. +- Accumulator register saving is not supported. Do not use DSP instructions or any libraries that include DSP instructions. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``mcb_rx26t`` board target configuration can be +built, flashed, and debugged as below. + +Currently, the Zephyr SDK hasn't added support for RX builds yet, so the GCC for RX toolchain is required and build system +need to be set to use "cross-compile". + + - Download and install GCC for RX v8.3.0.202405 toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for MCB-RX26T Type B: + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b mcb_rx26t samples/basic/blinky + +Flashing +======== + +Program can be flashed to MCB-RX26T via e2lite E2OB (Onboard debugger circuit). + +To flash the program to board + + 1. Connect from board's debug connector port to host PC using USB connector for E2 OB. + + 2. Execute west command + + .. code-block:: console + + west flash + +Debugging +========= + +You can use `Renesas Debug extension`_ on Visual Studio code for a visual debug interface. +The configuration for launch.json is as below. + +.. code-block:: json + + { + "version": "0.2.0", + "configurations": [ + { + "type": "renesas-hardware", + "request": "launch", + "name": "Renesas GDB Hardware Debugging", + "target": { + "deviceFamily": "RX", + "device": "R5F526TF", + "debuggerType": "E2LITE", + "serverParameters": [ + "-uUseFine=", "1", + "-w=", "1", + ], + } + } + ] + } + + +References +********** + +- `MCB-RX26T Type B Website`_ +- `RX26T MCU group Website`_ + +.. _MCB-RX26T Type B Website: + https://www.renesas.com/en/design-resources/boards-kits/mcb-rx26t-type-b + +.. _RX26T MCU group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx26t-32-bit-microcontroller-optimized-dual-motor-and-pfc-control +.. _MCB-RX26T Type B - User's Manual: + https://www.renesas.com/en/document/mat/mcb-rx26t-type-b-users-manual + +.. _RX26T Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx26t-group-users-manual-hardware + +.. _Renesas Debug extension: + https://marketplace.visualstudio.com/items?itemName=RenesasElectronicsCorporation.renesas-debug diff --git a/boards/renesas/mcb_rx26t/doc/mcb_rx26t.webp b/boards/renesas/mcb_rx26t/doc/mcb_rx26t.webp new file mode 100644 index 0000000000000..371a3e82adf50 Binary files /dev/null and b/boards/renesas/mcb_rx26t/doc/mcb_rx26t.webp differ diff --git a/boards/renesas/mcb_rx26t/mcb_rx26t-pinctrl.dtsi b/boards/renesas/mcb_rx26t/mcb_rx26t-pinctrl.dtsi new file mode 100644 index 0000000000000..a8d911f3663b8 --- /dev/null +++ b/boards/renesas/mcb_rx26t/mcb_rx26t-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci12_default: sci12_default { + group1 { + psels = , /* TX - PB5 */ + ; /* RX - PB6 */ + }; + }; +}; diff --git a/boards/renesas/mcb_rx26t/mcb_rx26t.dts b/boards/renesas/mcb_rx26t/mcb_rx26t.dts new file mode 100644 index 0000000000000..4f4b4423be7b6 --- /dev/null +++ b/boards/renesas/mcb_rx26t/mcb_rx26t.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "mcb_rx26t-pinctrl.dtsi" + +/ { + model = "Renesas MCB-RX26T KIT"; + compatible = "renesas,mcb_rx26t","renesas,rxv3"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart12; + zephyr,shell-uart = &uart12; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport2 1 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport2 0 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioport6 5 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + + led4: led4 { + gpios = <&ioport6 4 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + led3 = &led4; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&pll { + div = <1>; + mul = ; + status = "okay"; +}; + +&cmt { + clock-frequency = <60000000>; + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&sci12 { + pinctrl-0 = <&sci12_default>; + pinctrl-names = "default"; + status = "okay"; + + uart12: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/mcb_rx26t/mcb_rx26t.yaml b/boards/renesas/mcb_rx26t/mcb_rx26t.yaml new file mode 100644 index 0000000000000..94b2674f11c02 --- /dev/null +++ b/boards/renesas/mcb_rx26t/mcb_rx26t.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: mcb_rx26t +name: Renesas MCB-RX26T +type: mcu +arch: rx +toolchain: + - rxgcc +supported: + - gpio + - serial + - timer +ram: 64 +flash: 512 diff --git a/boards/renesas/mcb_rx26t/mcb_rx26t_defconfig b/boards/renesas/mcb_rx26t/mcb_rx26t_defconfig new file mode 100644 index 0000000000000..c23cdd58f2a0c --- /dev/null +++ b/boards/renesas/mcb_rx26t/mcb_rx26t_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/drivers/serial/uart_renesas_rx_sci.c b/drivers/serial/uart_renesas_rx_sci.c index d8ac3b926ee13..8e66051bafbeb 100644 --- a/drivers/serial/uart_renesas_rx_sci.c +++ b/drivers/serial/uart_renesas_rx_sci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,9 +14,12 @@ #include #include "r_sci_rx_if.h" +#include "iodefine_sci.h" #if CONFIG_SOC_SERIES_RX130 #include "r_sci_rx130_private.h" +#elif CONFIG_SOC_SERIES_RX26T +#include "r_sci_rx26t_private.h" #else #error Unknown SOC, not (yet) supported. #endif @@ -68,7 +71,7 @@ struct uart_rx_sci_data { static int uart_rx_sci_poll_in(const struct device *dev, unsigned char *c) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); if (IS_ENABLED(CONFIG_UART_ASYNC_API) && sci->SCR.BIT.RIE) { return -EBUSY; @@ -86,7 +89,7 @@ static int uart_rx_sci_poll_in(const struct device *dev, unsigned char *c) static void uart_rx_sci_poll_out(const struct device *dev, unsigned char c) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); while (sci->SSR.BIT.TEND == 0U) { } @@ -96,7 +99,7 @@ static void uart_rx_sci_poll_out(const struct device *dev, unsigned char c) static int uart_rx_err_check(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); const uint32_t status = sci->SSR.BYTE; int errors = 0; @@ -227,7 +230,7 @@ static int uart_rx_config_get(const struct device *dev, struct uart_config *cfg) static int uart_rx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); uint8_t num_tx = 0U; if (size > 0 && sci->SSR.BIT.TDRE) { @@ -240,7 +243,7 @@ static int uart_rx_fifo_fill(const struct device *dev, const uint8_t *tx_data, i static int uart_rx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); uint8_t num_rx = 0U; if (size > 0 && sci->SSR.BIT.RDRF) { @@ -254,7 +257,7 @@ static int uart_rx_fifo_read(const struct device *dev, uint8_t *rx_data, const i static void uart_rx_irq_tx_enable(const struct device *dev) { struct uart_rx_sci_data *data = dev->data; - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BYTE |= (BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos)); irq_enable(data->tei_irq); @@ -274,7 +277,7 @@ static void uart_rx_irq_tx_enable(const struct device *dev) static void uart_rx_irq_tx_disable(const struct device *dev) { struct uart_rx_sci_data *data = dev->data; - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BYTE &= ~(BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos)); irq_disable(data->tei_irq); @@ -282,7 +285,7 @@ static void uart_rx_irq_tx_disable(const struct device *dev) static int uart_rx_irq_tx_ready(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.TIE == 1U) && (sci->SSR.BYTE & (BIT(R_SCI_SSR_TDRE_Pos) | BIT(R_SCI_SSR_TEND_Pos))); @@ -290,28 +293,28 @@ static int uart_rx_irq_tx_ready(const struct device *dev) static int uart_rx_irq_tx_complete(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.TEIE == 1U) && (sci->SSR.BYTE & BIT(R_SCI_SSR_TEND_Pos)); } static void uart_rx_irq_rx_enable(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BIT.RIE = 1U; } static void uart_rx_irq_rx_disable(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BIT.RIE = 0U; } static int uart_rx_irq_rx_ready(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.RIE == 1U) && ((sci->SSR.BYTE & BIT(R_SCI_SSR_RDRF_Pos))); } @@ -332,7 +335,7 @@ static void uart_rx_irq_err_disable(const struct device *dev) static int uart_rx_irq_is_pending(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); bool tx_pending = false; bool rx_pending = false; @@ -439,7 +442,9 @@ static void uart_rx_sci_txi_isr(const struct device *dev) data->user_cb(dev, data->user_cb_data); } } +#endif +#ifndef CONFIG_SOC_SERIES_RX26T static void uart_rx_sci_tei_isr(const struct device *dev) { struct uart_rx_sci_data *data = dev->data; @@ -459,7 +464,16 @@ static void uart_rx_sci_eri_isr(const struct device *dev) } #endif +#if defined(CONFIG_SOC_SERIES_RX26T) +#define UART_RX_SCI_CONFIG_INIT(index) +#else +#define UART_RX_SCI_CONFIG_INIT(index) \ + .tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \ + .eri_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), +#endif + #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API +#ifndef CONFIG_SOC_SERIES_RX26T #define UART_RX_SCI_IRQ_INIT(index) \ do { \ IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \ @@ -480,9 +494,19 @@ static void uart_rx_sci_eri_isr(const struct device *dev) irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)); \ } while (0) #else -#define UART_RX_SCI_IRQ_INIT(index) +#define UART_RX_SCI_IRQ_INIT(index) \ + do { \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \ + uart_rx_sci_rxi_isr, DEVICE_DT_INST_GET(index), 0); \ + IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \ + DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \ + uart_rx_sci_txi_isr, DEVICE_DT_INST_GET(index), 0); \ + irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)); \ + irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)); \ + } while (0) +#endif #endif - #define UART_RX_INIT(index) \ PINCTRL_DT_DEFINE(DT_INST_PARENT(index)); \ @@ -506,9 +530,7 @@ static void uart_rx_sci_eri_isr(const struct device *dev) }, \ .rxi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \ .txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \ - .tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \ - .eri_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \ - }; \ + UART_RX_SCI_CONFIG_INIT(index)}; \ \ static int uart_rx_init_##index(const struct device *dev) \ { \ diff --git a/dts/rx/renesas/r5f526tfddfp.dtsi b/dts/rx/renesas/r5f526tfddfp.dtsi new file mode 100644 index 0000000000000..2c1b94abaec2c --- /dev/null +++ b/dts/rx/renesas/r5f526tfddfp.dtsi @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + mosel = <0>; + stabilization-time = <4>; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + loco: clock-loco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <240000>; + #clock-cells = <0>; + status = "okay"; + }; + + iwdtlsclk: clock-iwdt-low-speed { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <120000>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,rx-cgc-pll"; + #clock-cells = <0>; + div = <1>; + clocks = <&xtal>; + mul = ; + status = "disabled"; + }; + + canfdmclk: clock-canfdm { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + pclkblock: pclkblock@80010 { + compatible = "renesas,rx-cgc-pclk-block"; + reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>, + <0x0008001C 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; + #clock-cells = <0>; + clocks = <&pll>; + status = "okay"; + + iclk: iclk { + compatible = "renesas,rx-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,rx-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,rx-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,rx-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,rx-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,rx-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + canfdclk: clock-canfd { + compatible = "renesas,rx-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + }; + + caclclk: caclclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&loco>; + #clock-cells = <2>; + status = "disabled"; + }; + + cacmclk: cacmclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + #clock-cells = <2>; + status = "disabled"; + }; + + cachclk: cachclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&hoco>; + #clock-cells = <2>; + status = "disabled"; + }; + + caciclk: caciclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&iwdtlsclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + iwdtclk: iwdtclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&iwdtlsclk>; + #clock-cells = <2>; + status = "disabled"; + }; + }; + + soc { + sram0: memory@0 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + flash: flash-controller@7e0000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "renesas,rx-flash"; + reg = <0x007e0000 0x1000>; + + code_flash: flash@fff80000 { + compatible = "renesas,rx-nv-flash"; + reg = <0xfff80000 DT_SIZE_K(512)>; + }; + + data_flash: flash@100000 { + compatible = "renesas,rx-nv-flash"; + reg = <0x00100000 DT_SIZE_K(16)>; + }; + }; + }; +}; diff --git a/dts/rx/renesas/rx26t-common.dtsi b/dts/rx/renesas/rx26t-common.dtsi new file mode 100644 index 0000000000000..85668d6601c18 --- /dev/null +++ b/dts/rx/renesas/rx26t-common.dtsi @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * common device tree elements of all (currently supported) RX MCUs + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "renesas,rx"; + device_type = "cpu"; + reg = <0>; + status = "okay"; + }; + }; + + icu: interrupt-controller@87000 { + #interrupt-cells = <2>; + compatible = "renesas,rx-icu"; + interrupt-controller; + reg = <0x0087000 0xff>, + <0x0087200 0x1f>, + <0x0087300 0xff>, + <0x00872f0 0x02>, + <0x0087500 0x0f>, + <0x0087510 0x01>, + <0x0087514 0x01>; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + interrupt-parent = <&icu>; + + pinctrl: pin-controller@8c11f { + compatible = "renesas,rx-pinctrl"; + reg = <0x0008C11F 0x3c0>; + status = "okay"; + }; + + pinmux0: pinmux@8c140 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c140 0x8>; + status = "okay"; + }; + + pinmux1: pinmux@8c148 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c148 0x8>; + status = "okay"; + }; + + pinmux2: pinmux@8c150 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c150 0x8>; + status = "okay"; + }; + + pinmux3: pinmux@8c158 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c158 0x8>; + status = "okay"; + }; + + pinmux4: pinmux@8c160 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c160 0x8>; + status = "okay"; + }; + + pinmux5: pinmux@8c168 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c168 0x8>; + status = "okay"; + }; + + pinmux6: pinmux@8c170 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c170 0x8>; + status = "okay"; + }; + + pinmux7: pinmux@8c178 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c178 0x8>; + status = "okay"; + }; + + pinmux8: pinmux@8c180 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c180 0x8>; + status = "okay"; + }; + + pinmux9: pinmux@8c188 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c188 0x8>; + status = "okay"; + }; + + pinmuxa: pinmux@8c190 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c190 0x8>; + status = "okay"; + }; + + pinmuxb: pinmux@8c198 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c198 0x8>; + status = "okay"; + }; + + pinmuxd: pinmux@8c1a8 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1a8 0x8>; + status = "okay"; + }; + + pinmuxe: pinmux@8c1b0 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1b0 0x8>; + status = "okay"; + }; + + pinmuxn: pinmux@8c1f7 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1f7 0x8>; + status = "okay"; + }; + + ioport0: gpio@8c000 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x02>; + ngpios = <2>; + port = <0>; + reg = <0x0008C000 0x01>, + <0x0008C020 0x01>, + <0x0008C040 0x01>, + <0x0008C060 0x01>, + <0x0008C080 0x01>, + <0x0008C0C0 0x01>, + <0x0008C0E0 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR", "DSCR"; + pinmux = <&pinmux0>; + status = "disabled"; + }; + + ioport1: gpio@8c001 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <2>; + port = <1>; + reg = <0x0008C001 0x01>, + <0x0008C021 0x01>, + <0x0008C041 0x01>, + <0x0008C061 0x01>, + <0x0008C082 0x01>, + <0x0008C0C1 0x01>, + <0x0008C0E1 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR", "DSCR"; + pinmux = <&pinmux1>; + status = "disabled"; + }; + + ioport2: gpio@8c002 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <2>; + reg = <0x0008C002 0x01>, + <0x0008C022 0x01>, + <0x0008C042 0x01>, + <0x0008C062 0x01>, + <0x0008C084 0x01>, + <0x0008C085 0x01>, + <0x0008C0C2 0x01>, + <0x0008C0E2 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", "DSCR"; + pinmux = <&pinmux2>; + status = "disabled"; + }; + + ioport3: gpio@8c003 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <3>; + reg = <0x0008C003 0x01>, + <0x0008C023 0x01>, + <0x0008C043 0x01>, + <0x0008C063 0x01>, + <0x0008C086 0x01>, + <0x0008C087 0x01>, + <0x0008C0C3 0x01>, + <0x0008C0E3 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", "DSCR"; + pinmux = <&pinmux3>; + status = "disabled"; + }; + + ioport4: gpio@8c004 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <4>; + reg = <0x0008C004 0x01>, + <0x0008C024 0x01>, + <0x0008C044 0x01>, + <0x0008C064 0x01>, + <0x0008C088 0x01>, + <0x0008C089 0x01>, + <0x0008C0C4 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux4>; + status = "disabled"; + }; + + ioport5: gpio@8c005 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <5>; + reg = <0x0008C005 0x01>, + <0x0008C025 0x01>, + <0x0008C045 0x01>, + <0x0008C065 0x01>, + <0x0008C08A 0x01>, + <0x0008C08B 0x01>, + <0x0008C0C5 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux5>; + status = "disabled"; + }; + + ioport6: gpio@8c006 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <6>; + reg = <0x0008C006 0x01>, + <0x0008C026 0x01>, + <0x0008C046 0x01>, + <0x0008C066 0x01>, + <0x0008C08C 0x01>, + <0x0008C08D 0x01>, + <0x0008C0C6 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux5>; + status = "disabled"; + }; + + ioport7: gpio@8c007 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <7>; + port = <7>; + reg = <0x0008C007 0x01>, + <0x0008C027 0x01>, + <0x0008C047 0x01>, + <0x0008C067 0x01>, + <0x0008C08E 0x01>, + <0x0008C08F 0x01>, + <0x0008C0C7 0x01>, + <0x0008C0E7 0x01>, + <0x0008C12F 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", + "DSCR", "DSCR2"; + pinmux = <&pinmux7>; + status = "disabled"; + }; + + ioport8: gpio@8c008 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <3>; + port = <8>; + reg = <0x0008C008 0x01>, + <0x0008C028 0x01>, + <0x0008C048 0x01>, + <0x0008C068 0x01>, + <0x0008C090 0x01>, + <0x0008C0C8 0x01>, + <0x0008C0E8 0x01>, + <0x0008C130 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR", "DSCR", + "DSCR2"; + pinmux = <&pinmux8>; + status = "disabled"; + }; + + ioport9: gpio@8c009 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <7>; + port = <9>; + reg = <0x0008C009 0x01>, + <0x0008C029 0x01>, + <0x0008C049 0x01>, + <0x0008C069 0x01>, + <0x0008C092 0x01>, + <0x0008C093 0x01>, + <0x0008C0C9 0x01>, + <0x0008C0E9 0x01>, + <0x0008C131 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", + "DSCR", "DSCR2"; + pinmux = <&pinmux9>; + status = "disabled"; + }; + + ioporta: gpio@8c00a { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <10>; + reg = <0x0008C00A 0x01>, + <0x0008C02A 0x01>, + <0x0008C04A 0x01>, + <0x0008C06A 0x01>, + <0x0008C094 0x01>, + <0x0008C095 0x01>, + <0x0008C0CA 0x01>, + <0x0008C0EA 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", + "PCR", "DSCR"; + pinmux = <&pinmuxa>; + status = "disabled"; + }; + + ioportb: gpio@8c00b { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <11>; + reg = <0x0008C00B 0x01>, + <0x0008C02B 0x01>, + <0x0008C04B 0x01>, + <0x0008C06B 0x01>, + <0x0008C096 0x01>, + <0x0008C097 0x01>, + <0x0008C0CB 0x01>, + <0x0008C0EB 0x01>, + <0x0008C133 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", + "DSCR", "DSCR2"; + pinmux = <&pinmuxb>; + status = "disabled"; + }; + + ioportd: gpio@8c00d { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <13>; + reg = <0x0008C00D 0x01>, + <0x0008C02D 0x01>, + <0x0008C04D 0x01>, + <0x0008C06D 0x01>, + <0x0008C09A 0x01>, + <0x0008C09B 0x01>, + <0x0008C0CD 0x01>, + <0x0008C0ED 0x01>, + <0x0008C135 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", + "DSCR", "DSCR2"; + pinmux = <&pinmuxd>; + status = "disabled"; + }; + + ioporte: gpio@8c00e { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <6>; + port = <14>; + reg = <0x0008C00E 0x01>, + <0x0008C02E 0x01>, + <0x0008C04E 0x01>, + <0x0008C06E 0x01>, + <0x0008C09C 0x01>, + <0x0008C09D 0x01>, + <0x0008C0CE 0x01>, + <0x0008C0EE 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", "DSCR"; + pinmux = <&pinmuxe>; + status = "disabled"; + }; + + ioportn: gpio@8c016 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <2>; + port = <23>; + reg = <0x0008C016 0x01>, + <0x0008C036 0x01>, + <0x0008C056 0x01>, + <0x0008C076 0x01>, + <0x0008C0D6 0x01>, + <0x0008C0F6 0x01>, + <0x0008C0AD 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "PCR", "DSCR", "ODR1"; + pinmux = <&pinmuxn>; + status = "disabled"; + }; + + sci1: sci1@8a020 { + compatible = "renesas,rx-sci"; + interrupts = <60 1>, <61 1>; + interrupt-names = "rxi", "txi"; + reg = <0x8A020 0x20>; + clocks = <&pclkb MSTPB 30>; + status = "disabled"; + channel = <1>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci5: sci5@8a0a0 { + compatible = "renesas,rx-sci"; + interrupts = <84 1>, <85 1>; + interrupt-names = "rxi", "txi"; + reg = <0x8A0A0 0x20>; + clocks = <&pclkb MSTPB 26>; + status = "disabled"; + channel = <5>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci6: sci6@8a0c0 { + compatible = "renesas,rx-sci"; + interrupts = <86 1>, <87 1>; + interrupt-names = "rxi", "txi"; + reg = <0x8A0C0 0x20>; + clocks = <&pclkb MSTPB 25>; + status = "disabled"; + channel = <6>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci12: sci12@8b300 { + compatible = "renesas,rx-sci"; + interrupts = <116 1>, <117 1>; + interrupt-names = "rxi", "txi"; + reg = <0x8B300 0x20>; + clocks = <&pclkb MSTPB 4>; + status = "disabled"; + channel = <12>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + cmt: timer@88000 { + compatible = "renesas,rx-timer-cmt-start-control"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pclkb MSTPA 15>; + reg = <0x00088000 0x02>; + reg-names = "CMSTR0"; + status = "okay"; + + cmt0: timer@88002 { + compatible = "renesas,rx-timer-cmt"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00088002 0x02>, + <0x00088004 0x02>, + <0x00088006 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <28 1>; + interrupt-names = "cmi"; + status = "okay"; + }; + + cmt1: timer@88008 { + compatible = "renesas,rx-timer-cmt"; + reg = <0x00088008 0x02>, + <0x0008800A 0x02>, + <0x0008800C 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <29 1>; + interrupt-names = "cmi"; + status = "okay"; + }; + }; + + ofsm: ofsm@120040 { + compatible = "zephyr,memory-region"; + reg = <0x00120040 0xBF>; + zephyr,memory-region = "OFSM"; + status = "okay"; + }; + }; +}; diff --git a/include/zephyr/drivers/clock_control/renesas_rx_cgc.h b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h index 19f196b6d65d9..4b44151776f7d 100644 --- a/include/zephyr/drivers/clock_control/renesas_rx_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h @@ -17,6 +17,11 @@ (UTIL_CAT(RX_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ (RX_CLOCKS_CLOCK_DISABLED)) +#define RX_CGC_PLL_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(RX_PLL_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (RX_CLOCKS_CLOCK_DISABLED)) + struct clock_control_rx_pclk_cfg { const struct device *clock_src_dev; uint32_t clk_div; diff --git a/include/zephyr/dt-bindings/clock/rx_clock.h b/include/zephyr/dt-bindings/clock/rx_clock.h index cab40d575fd57..ee022ae803a0c 100644 --- a/include/zephyr/dt-bindings/clock/rx_clock.h +++ b/include/zephyr/dt-bindings/clock/rx_clock.h @@ -14,6 +14,11 @@ #define RX_CLOCKS_SOURCE_PLL 4 #define RX_CLOCKS_SOURCE_CLOCK_DISABLE 0xff +#ifdef CONFIG_SOC_SERIES_RX26T +#define RX_PLL_CLOCKS_SOURCE_CLOCK_MAIN_OSC 0 +#define RX_PLL_CLOCKS_SOURCE_CLOCK_HOCO 1 +#endif /* CONFIG_SOC_SERIES_RX26T */ + #define RX_PLL_MUL_4 7 #define RX_PLL_MUL_4_5 8 #define RX_PLL_MUL_5 9 @@ -24,6 +29,48 @@ #define RX_PLL_MUL_7_5 14 #define RX_PLL_MUL_8 15 +#define RX_PLL_MUL_10 19 +#define RX_PLL_MUL_10_5 20 +#define RX_PLL_MUL_11 21 +#define RX_PLL_MUL_11_5 22 +#define RX_PLL_MUL_12 23 +#define RX_PLL_MUL_12_5 24 +#define RX_PLL_MUL_13 25 +#define RX_PLL_MUL_13_5 26 +#define RX_PLL_MUL_14 27 +#define RX_PLL_MUL_14_5 28 +#define RX_PLL_MUL_15 29 +#define RX_PLL_MUL_15_5 30 +#define RX_PLL_MUL_16 31 +#define RX_PLL_MUL_16_5 32 +#define RX_PLL_MUL_17 33 +#define RX_PLL_MUL_17_5 34 +#define RX_PLL_MUL_18 35 +#define RX_PLL_MUL_18_5 36 +#define RX_PLL_MUL_19 37 +#define RX_PLL_MUL_19_5 38 +#define RX_PLL_MUL_20 39 +#define RX_PLL_MUL_20_5 40 +#define RX_PLL_MUL_21 41 +#define RX_PLL_MUL_21_5 42 +#define RX_PLL_MUL_22 43 +#define RX_PLL_MUL_22_5 44 +#define RX_PLL_MUL_23 45 +#define RX_PLL_MUL_23_5 46 +#define RX_PLL_MUL_24 47 +#define RX_PLL_MUL_24_5 48 +#define RX_PLL_MUL_25 49 +#define RX_PLL_MUL_25_5 50 +#define RX_PLL_MUL_26 51 +#define RX_PLL_MUL_26_5 52 +#define RX_PLL_MUL_27 53 +#define RX_PLL_MUL_27_5 54 +#define RX_PLL_MUL_28 55 +#define RX_PLL_MUL_28_5 56 +#define RX_PLL_MUL_29 57 +#define RX_PLL_MUL_29_5 58 +#define RX_PLL_MUL_30 59 + #define MSTPA 0 #define MSTPB 1 #define MSTPC 2 diff --git a/soc/renesas/rx/rx26t/CMakeLists.txt b/soc/renesas/rx/rx26t/CMakeLists.txt new file mode 100644 index 0000000000000..278090303888b --- /dev/null +++ b/soc/renesas/rx/rx26t/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS ofsm.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/rx/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rx/rx26t/Kconfig b/soc/renesas/rx/rx26t/Kconfig new file mode 100644 index 0000000000000..54c68b53159b9 --- /dev/null +++ b/soc/renesas/rx/rx26t/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX26T + select RX + select CPU_RXV3 + select XIP + select CLOCK_CONTROL_RENESAS_RX_CGC if CLOCK_CONTROL + select HAS_RENESAS_RX_RDP + select CLOCK_CONTROL diff --git a/soc/renesas/rx/rx26t/Kconfig.defconfig b/soc/renesas/rx/rx26t/Kconfig.defconfig new file mode 100644 index 0000000000000..f237db715f421 --- /dev/null +++ b/soc/renesas/rx/rx26t/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RX26T + +# Set the PCLKB/8 frequency to SYS_CLOCK_HW_CYCLES_PER_SEC. +# Because the CMT of Systick Timer divides the source clock of PCLKB by 8-divider. +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 7500000 + +# SYS_CLOCK_TICKS_PER_SEC is set to 100 if PCLKB is 48MHz or less. +# (PCLKB = SYS_CLOCK_HW_CYCLES_PER_SEC * 8) +config SYS_CLOCK_TICKS_PER_SEC + #default 100 if SYS_CLOCK_HW_CYCLES_PER_SEC <= 6000000 + default 1000 + +config INITIALIZATION_STACK_SIZE + default 512 + +# Enable hex file generation +config BUILD_OUTPUT_HEX + default y + +endif # SOC_SERIES_RX26T diff --git a/soc/renesas/rx/rx26t/Kconfig.soc b/soc/renesas/rx/rx26t/Kconfig.soc new file mode 100644 index 0000000000000..fcb1de7a1c5cd --- /dev/null +++ b/soc/renesas/rx/rx26t/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX26T + bool + select SOC_FAMILY_RENESAS_RX + help + Renesas RX26T series + +config SOC_R5F526TFDDFP + bool + select SOC_SERIES_RX26T + help + SOC_R5F526TFDDFP + +config SOC_SERIES + default "rx26t" if SOC_SERIES_RX26T + +config SOC + default "r5f526tfddfp" if SOC_R5F526TFDDFP diff --git a/soc/renesas/rx/rx26t/ofsm.c b/soc/renesas/rx/rx26t/ofsm.c new file mode 100644 index 0000000000000..eb81b0a327949 --- /dev/null +++ b/soc/renesas/rx/rx26t/ofsm.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * + * Option-Setting Memory for the RX. This region of memory (located in flash) + * determines the state of the MCU after reset and can not be changed on runtime + * + * All registers are set to 0xffffffff by default, which are "safe" settings. + * Please refer to the Renesas RX Group User's Manual before changing any of + * the values as some changes can be permanent or lock access to the device. + * + * Address range: 0x00120040 to 0x001200ff + */ + +#define __OFS_MDE __attribute__((section(".ofs_mde"))) +#define __OFS0 __attribute__((section(".ofs0"))) +#define __OFS1 __attribute__((section(".ofs1"))) + +/* Endian Select Register (MDE) at 0x00120064 + * + * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little + * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) + * + * b6-b4 (Bank Mode Select) indicate whether the flash is operated in + * Dual mode (0 0 0) or Linear mode (1 1 1). + * + * all other bits are reserved and have to be set to 1 + */ +const unsigned long __OFS_MDE __MDEreg = 0xffffffffU; /* little */ + +/* Option function select register 0 (OFS0) at 0x00120068 (Watchdog settings) + */ + +const unsigned long __OFS0 __OFS0reg = 0xffffffffU; + +/* Option Function Select Register 1 (OFS1) at 0x0012006C (Voltage detection and + * HOCO) + */ +const unsigned long __OFS1 __OFS1reg = 0xffffffffU; diff --git a/soc/renesas/rx/rx26t/ofsm.ld b/soc/renesas/rx/rx26t/ofsm.ld new file mode 100644 index 0000000000000..f54ed44eb7ae0 --- /dev/null +++ b/soc/renesas/rx/rx26t/ofsm.ld @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.ofsm,,) +{ + __OFSM_START = .; + KEEP(*(.spcc)) + . = __OFSM_START + 0x8; + KEEP(*(.tmef)) + . = __OFSM_START + 0x10; + KEEP(*(.osis)) + . = __OFSM_START + 0x20; + KEEP(*(.tminf)) + . = __OFSM_START + 0x24; + KEEP(*(.mde)) + . = __OFSM_START + 0x28; + KEEP(*(.ofs0)) + . = __OFSM_START + 0x2c; + KEEP(*(.ofs1)) + . = __OFSM_START + 0x50; + KEEP(*(.banksel)) + . = __OFSM_START + 0x60; + KEEP(*(.faw)) + __OFSM_END = .; +} GROUP_LINK_IN(OFSM) = 0xFF diff --git a/soc/renesas/rx/rx26t/soc.c b/soc/renesas/rx/rx26t/soc.c new file mode 100644 index 0000000000000..3691f72d562a6 --- /dev/null +++ b/soc/renesas/rx/rx26t/soc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief System/hardware module for RX SOC family + */ + +#include +#include +#include +#include +#include + +#include "platform.h" +#include "r_bsp_cpu.h" + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +void soc_early_init_hook(void) +{ +#ifdef CONFIG_HAS_RENESAS_RX_RDP + bsp_ram_initialize(); + bsp_interrupt_open(); + bsp_register_protect_open(); +#if CONFIG_RENESAS_NONE_USED_PORT_INIT == 1 + /* + * This is the function that initializes the unused port. + * Please see datails on this in the "Handling of Unused Pins" section of PORT chapter + * of RX MCU of User's manual. + * And please MUST set "BSP_PACKAGE_PINS" definition to your device of pin type in + * r_bsp_config.h Otherwise, the port may output without intention. + */ + bsp_non_existent_port_init(); + +#endif /* CONFIG_RENESAS_NONE_USED_PORT_INIT */ +#endif /* CONFIG_HAS_RENESAS_RX_RDP */ +} diff --git a/soc/renesas/rx/rx26t/soc.h b/soc/renesas/rx/rx26t/soc.h new file mode 100644 index 0000000000000..f1653a6c0b745 --- /dev/null +++ b/soc/renesas/rx/rx26t/soc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief SOC header file for Renesas RX SOC series + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include +#include "reg_protection.h" + +#endif /* _SOC_H_ */ diff --git a/soc/renesas/rx/soc.yml b/soc/renesas/rx/soc.yml index 5d28644afd65f..66aa865ef7fe0 100644 --- a/soc/renesas/rx/soc.yml +++ b/soc/renesas/rx/soc.yml @@ -7,3 +7,6 @@ family: - name: rx62n socs: - name: r5f562n8 + - name: rx26t + socs: + - name: r5f526tfddfp diff --git a/west.yml b/west.yml index 60cd188d65129..316eeda0b9495 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0769fe1520f6c14e6301188588da758a609f181d + revision: pull/121/head groups: - hal - name: hal_rpi_pico