diff --git a/arch/riscv/CMakeLists.txt b/arch/riscv/CMakeLists.txt index c471c4c6b51f3..a476285e5172c 100644 --- a/arch/riscv/CMakeLists.txt +++ b/arch/riscv/CMakeLists.txt @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(core) +add_subdirectory(custom) zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/arch/riscv/error.h) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5d3e85450f195..2a4e19023bfe6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -526,6 +526,7 @@ config RISCV_NO_MTVAL_ON_FP_TRAP to handle FP exceptions. rsource "Kconfig.isa" -rsource "core/Kconfig" + +rsource "custom/Kconfig" endmenu diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt index b2bf26dbf39a9..abd9d4504134c 100644 --- a/arch/riscv/core/CMakeLists.txt +++ b/arch/riscv/core/CMakeLists.txt @@ -42,5 +42,3 @@ if(CONFIG_GEN_SW_ISR_TABLE) zephyr_linker_sources(RODATA swi_tables.ld) endif() endif() - -add_subdirectory_ifdef(CONFIG_XUANTIE xuantie) diff --git a/arch/riscv/core/Kconfig b/arch/riscv/core/Kconfig deleted file mode 100644 index c3bfe4158a5ac..0000000000000 --- a/arch/riscv/core/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# RISC-V cores configuration options - -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -config XUANTIE - bool - help - This option signifies the use of a CPU of the XuanTie RISC-V family - -rsource "xuantie/Kconfig" diff --git a/arch/riscv/core/xuantie/CMakeLists.txt b/arch/riscv/core/xuantie/CMakeLists.txt deleted file mode 100644 index 38a4c403765a5..0000000000000 --- a/arch/riscv/core/xuantie/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/cache.h) - -zephyr_library() - -zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO cache_xtheadcmo.c) -zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO_E907 cache_xtheadcmo_e907.c) diff --git a/arch/riscv/core/xuantie/Kconfig b/arch/riscv/core/xuantie/Kconfig deleted file mode 100644 index bb0cf7b0b004c..0000000000000 --- a/arch/riscv/core/xuantie/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# SPDX-License-Identifier: Apache-2.0 - -config XUANTIE_E907 - bool - select XUANTIE - select GEN_IRQ_VECTOR_TABLE - select INCLUDE_RESET_VECTOR - select RISCV_HAS_CLIC - select RISCV_MACHINE_TIMER - select RISCV_PRIVILEGED - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_VECTORED_MODE - -if XUANTIE - -config CACHE_XTHEADCMO - bool - default y - select CACHE_MANAGEMENT - select CPU_HAS_ICACHE - help - This option enables cache support for XuanTie family of CPUs using the XTHeadCmo extension - -if CACHE_XTHEADCMO - -config DCACHE_LINE_SIZE - default 32 - -config ICACHE_LINE_SIZE - default 32 - -config CACHE_XTHEADCMO_E907 - bool - default y - depends on XUANTIE_E907 - select CPU_HAS_DCACHE - help - This option enables the additional XTHeadCmo cache functions for the E907 cores - -endif # CACHE_XTHEADCMO - -endif # XUANTIE diff --git a/arch/riscv/custom/CMakeLists.txt b/arch/riscv/custom/CMakeLists.txt new file mode 100644 index 0000000000000..fab46a8142a6c --- /dev/null +++ b/arch/riscv/custom/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory_ifdef(CONFIG_DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED andes) +add_subdirectory_ifdef(CONFIG_DT_HAS_OPENHWGROUP_CVA6_ENABLED openhwgroup/cva6) +add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei) +add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy) +add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy) +add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead) diff --git a/arch/riscv/custom/Kconfig b/arch/riscv/custom/Kconfig new file mode 100644 index 0000000000000..e14abc77280d4 --- /dev/null +++ b/arch/riscv/custom/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +if DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED + +rsource "andes/Kconfig" + +endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED + +if DT_HAS_XUANTIE_E907_ENABLED + +rsource "thead/Kconfig" +rsource "thead/Kconfig.core" + +endif # DT_HAS_XUANTIE_E907_ENABLED diff --git a/arch/riscv/custom/andes/CMakeLists.txt b/arch/riscv/custom/andes/CMakeLists.txt new file mode 100644 index 0000000000000..1b0c491142480 --- /dev/null +++ b/arch/riscv/custom/andes/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA pma.c) +zephyr_sources_ifndef(CONFIG_INCLUDE_RESET_VECTOR reset.S) +zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECIT RODATA SORT_KEY 0x0 execit.ld) +zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA RAM_SECTIONS SORT_KEY 0x0 pma_align_start.ld) +zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA RAM_SECTIONS SORT_KEY z_end pma_align_end.ld) diff --git a/arch/riscv/custom/andes/Kconfig b/arch/riscv/custom/andes/Kconfig new file mode 100644 index 0000000000000..142f8f8b79dc0 --- /dev/null +++ b/arch/riscv/custom/andes/Kconfig @@ -0,0 +1,73 @@ +# Copyright (c) 2025 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config CPU_HAS_ANDES_EXECIT + bool + help + The AndesCore supports EXEC.IT instruction. + +config RISCV_CUSTOM_CSR_ANDES_EXECIT + bool "Andes V5 EXEC.IT extension" + depends on CPU_HAS_ANDES_EXECIT + depends on RISCV_ISA_EXT_C + depends on !RISCV_GENERIC_TOOLCHAIN + depends on !LINKER_USE_NO_RELAX + help + The EXEC.IT extension (Execution on Instruction Table) generate + a look-up table and replaces suitable 32-bit instructions with + the 16-bit "exec.it ". + +config RISCV_CUSTOM_CSR_ANDES_NEXECIT + bool "Andes V5 New EXEC.IT opcode encoding" + depends on RISCV_CUSTOM_CSR_ANDES_EXECIT + help + The New EXEC.IT instruction is an alias of EXEC.IT with different + opcode encoding. + +config CPU_HAS_ANDES_HWDSP + bool + help + The AndesCore supports hardware DSP extension. + +config RISCV_CUSTOM_CSR_ANDES_HWDSP + bool "AndeStar V5 DSP ISA" + depends on CPU_HAS_ANDES_HWDSP + depends on !RISCV_GENERIC_TOOLCHAIN + help + This option enables the AndeStar v5 hardware DSP, in order to + support using the DSP instructions. + +config CPU_HAS_ANDES_PFT + bool + help + The AndesCore supports PowerBrake extension. + +config RISCV_CUSTOM_CSR_ANDES_PFT + bool "Andes V5 PowerBrake extension" + depends on CPU_HAS_ANDES_PFT + help + The PowerBrake extension throttles performance by reducing instruction + executing rate. + +config CPU_HAS_ANDES_PMA + bool + help + The AndesCore supports Programmable PMA. + +config RISCV_CUSTOM_CSR_ANDES_PMA + bool "Andes V5 Physical Memory Attribute (PMA)" + depends on CPU_HAS_ANDES_PMA + select ARCH_HAS_NOCACHE_MEMORY_SUPPORT + help + This option enables the Andes V5 PMA, in order to support SW to + configure physical memory attribute by PMA CSRs. The address + matching of Andes V5 PMA is like RISC-V PMP NAPOT mode + (power-of-two alignment). + +config RISCV_CUSTOM_CSR_ANDES_PMA_NAPOT_GRANULARITY + int + depends on RISCV_CUSTOM_CSR_ANDES_PMA + default 4096 + help + Minimum size (and alignment) of an PMA region. Use this symbol + to guarantee minimum size and alignment of PMA regions. diff --git a/soc/andestech/ae350/soc_v5.h b/arch/riscv/custom/andes/andes_csr.h similarity index 86% rename from soc/andestech/ae350/soc_v5.h rename to arch/riscv/custom/andes/andes_csr.h index 111a021a4f892..be3b27298c51a 100644 --- a/soc/andestech/ae350/soc_v5.h +++ b/arch/riscv/custom/andes/andes_csr.h @@ -1,11 +1,14 @@ /* - * Copyright (c) 2021 Andes Technology Corporation - * + * Copyright (c) 2025 Andes Technology Corporation * SPDX-License-Identifier: Apache-2.0 */ -#ifndef __RISCV_ANDES_V5_SOC_V5_H_ -#define __RISCV_ANDES_V5_SOC_V5_H_ +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* Control and Status Registers (CSRs) available for Andes V5 SoCs */ #define NDS_MMISC_CTL 0x7D0 @@ -46,4 +49,8 @@ #define NDS_PMAADDR14 0xBDE #define NDS_PMAADDR15 0xBDF -#endif /* __RISCV_ANDES_V5_SOC_V5_H_ */ +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_ */ diff --git a/arch/riscv/custom/andes/csr_context.h b/arch/riscv/custom/andes/csr_context.h new file mode 100644 index 0000000000000..d92ceff080ce9 --- /dev/null +++ b/arch/riscv/custom/andes/csr_context.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE. + */ + +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_ + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + +/* Andes V5 specific registers. */ +#if defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) && \ + defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP) + #define CUSTOM_CSR_ESF_MEMBERS \ + uint32_t mxstatus; \ + uint32_t ucode \ + + #define CUSTOM_CSR_ESF_INIT \ + 0, \ + 0 + +#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) + #define CUSTOM_CSR_ESF_MEMBERS \ + uint32_t mxstatus + + #define CUSTOM_CSR_ESF_INIT \ + 0 + +#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP) + #define CUSTOM_CSR_ESF_MEMBERS \ + uint32_t ucode + + #define CUSTOM_CSR_ESF_INIT \ + 0 + +#endif + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_ */ diff --git a/arch/riscv/custom/andes/csr_irq.inc b/arch/riscv/custom/andes/csr_irq.inc new file mode 100644 index 0000000000000..52a4200e1544e --- /dev/null +++ b/arch/riscv/custom/andes/csr_irq.inc @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifdef CONFIG_64BIT + /* register-wide load/store based on ld/sd (XLEN = 64) */ + + .macro lr, rd, mem + ld \rd, \mem + .endm + + .macro sr, rs, mem + sd \rs, \mem + .endm + +#else + /* register-wide load/store based on lw/sw (XLEN = 32) */ + + .macro lr, rd, mem + lw \rd, \mem + .endm + + .macro sr, rs, mem + sw \rs, \mem + .endm + +#endif + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + + .macro __custom_csr_save_context __soc_esf_reg reg + +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT + csrr \reg, NDS_MXSTATUS + sr \reg, __soc_esf_t_mxstatus_OFFSET(\__soc_esf_reg) +#endif + +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP + csrr \reg, NDS_UCODE + sr \reg, __soc_esf_t_ucode_OFFSET(\__soc_esf_reg) +#endif + + .endm + + .macro __custom_csr_restore_context __soc_esf_reg reg + +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT + lr \reg, __soc_esf_t_mxstatus_OFFSET(\__soc_esf_reg) + csrw NDS_MXSTATUS, \reg +#endif +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP + lr \reg, __soc_esf_t_ucode_OFFSET(\__soc_esf_reg) + csrw NDS_UCODE, \reg +#endif + + .endm + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/arch/riscv/custom/andes/csr_offsets.h b/arch/riscv/custom/andes/csr_offsets.h new file mode 100644 index 0000000000000..a5ef20d638435 --- /dev/null +++ b/arch/riscv/custom/andes/csr_offsets.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_OFFSETS. + */ + +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_ + +#ifdef CONFIG_RISCV_SOC_OFFSETS + +/* Andes V5 specific registers. */ +#if defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) && \ + defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP) + #define GEN_CUSTOM_CSR_OFFSET_SYMS() \ + GEN_OFFSET_SYM(soc_esf_t, mxstatus); \ + GEN_OFFSET_SYM(soc_esf_t, ucode) + +#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) + #define GEN_CUSTOM_CSR_OFFSET_SYMS() \ + GEN_OFFSET_SYM(soc_esf_t, mxstatus) + +#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP) + #define GEN_CUSTOM_CSR_OFFSET_SYMS() \ + GEN_OFFSET_SYM(soc_esf_t, ucode) + +#endif + +#endif /* CONFIG_RISCV_SOC_OFFSETS */ + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_ */ diff --git a/soc/andestech/ae350/common_linker/execit.ld b/arch/riscv/custom/andes/execit.ld similarity index 100% rename from soc/andestech/ae350/common_linker/execit.ld rename to arch/riscv/custom/andes/execit.ld diff --git a/soc/andestech/ae350/pma.c b/arch/riscv/custom/andes/pma.c similarity index 95% rename from soc/andestech/ae350/pma.c rename to arch/riscv/custom/andes/pma.c index 326bdf372b9bf..1e9d41c4f54f9 100644 --- a/soc/andestech/ae350/pma.c +++ b/arch/riscv/custom/andes/pma.c @@ -1,16 +1,14 @@ /* - * Copyright (c) 2021 Andes Technology Corporation - * + * Copyright (c) 2025 Andes Technology Corporation * SPDX-License-Identifier: Apache-2.0 */ -#include "soc_v5.h" - #include #include #include #include #include +#include #ifndef CONFIG_ASSERT #define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL @@ -149,7 +147,7 @@ static void region_init(const uint32_t index, static int pma_region_is_valid(const struct pma_region *region) { /* Region size must greater or equal to the minimum PMA region size */ - if (region->size < CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE) { + if (region->size < CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA_NAPOT_GRANULARITY) { return -EINVAL; } @@ -204,10 +202,10 @@ void pma_init(void) /* This CPU doesn't support PMA */ __ASSERT(0, "CPU doesn't support PMA. " - "Please disable CONFIG_SOC_ANDES_V5_PMA\n"); + "Please disable CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA\n"); #ifndef CONFIG_ASSERT LOG_ERR("CPU doesn't support PMA. " - "Please disable CONFIG_SOC_ANDES_V5_PMA"); + "Please disable CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA"); #endif return; } diff --git a/soc/andestech/ae350/pma.h b/arch/riscv/custom/andes/pma.h similarity index 66% rename from soc/andestech/ae350/pma.h rename to arch/riscv/custom/andes/pma.h index 459db7c98d946..11b5879403a03 100644 --- a/soc/andestech/ae350/pma.h +++ b/arch/riscv/custom/andes/pma.h @@ -1,10 +1,13 @@ /* - * Copyright (c) 2021 Andes Technology Corporation + * Copyright (c) 2025 Andes Technology Corporation * Copyright (c) 2024 Meta Platforms * * SPDX-License-Identifier: Apache-2.0 */ +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_PMA_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_PMA_H_ + /* * @brief Init PMA CSRs of each CPU core * @@ -16,3 +19,5 @@ void pma_init_per_core(void); /* Initialize PMA */ void pma_init(void); + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_PMA_H_ */ diff --git a/arch/riscv/custom/andes/pma_align_end.ld b/arch/riscv/custom/andes/pma_align_end.ld new file mode 100644 index 0000000000000..a403409d6a524 --- /dev/null +++ b/arch/riscv/custom/andes/pma_align_end.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma pop_macro("MPU_ALIGN") diff --git a/arch/riscv/custom/andes/pma_align_start.ld b/arch/riscv/custom/andes/pma_align_start.ld new file mode 100644 index 0000000000000..db3621c7314b9 --- /dev/null +++ b/arch/riscv/custom/andes/pma_align_start.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma push_macro("MPU_ALIGN") +#undef MPU_ALIGN +/* Make linker section alignment comply with PMA granularity. */ +#define MPU_ALIGN(region_size) \ + . = ALIGN(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA_NAPOT_GRANULARITY); \ + . = ALIGN( 1 << LOG2CEIL(region_size)) diff --git a/soc/andestech/ae350/start.S b/arch/riscv/custom/andes/reset.S similarity index 57% rename from soc/andestech/ae350/start.S rename to arch/riscv/custom/andes/reset.S index 9f0ac85caa35d..1214c80e7b677 100644 --- a/soc/andestech/ae350/start.S +++ b/arch/riscv/custom/andes/reset.S @@ -1,22 +1,21 @@ /* - * Copyright (c) 2021 Andes Technology Corporation - * + * Copyright (c) 2025 Andes Technology Corporation * SPDX-License-Identifier: Apache-2.0 */ -#include "soc_v5.h" - +#include #include +#include /* exports */ -GTEXT(entry) +GTEXT(__reset) + +/* imports */ +GTEXT(__initialize) -SECTION_FUNC(init, entry) - /* Disable linker relaxation before GP register initialization. */ - .option push - .option norelax +SECTION_FUNC(reset, __reset) -#ifdef CONFIG_SOC_ANDES_V5_EXECIT +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECIT /* Initialize EXECIT table */ la t0, _ITB_BASE_ csrw NDS_UITB, t0 @@ -30,12 +29,17 @@ SECTION_FUNC(init, entry) #ifdef CONFIG_DCACHE /* - * Enable D cache with HW prefetcher, D-cache write-around - * (threshold: 4 cache lines), and CM (Coherence Manager). + * Enable D cache with HW prefetcher and D-cache write-around + * (threshold: 4 cache lines). */ li t0, (0x3 << 13) csrc NDS_MCACHE_CTL, t0 - li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1) + li t0, (1 << 13) | (1 << 10) | (1 << 1) + csrs NDS_MCACHE_CTL, t0 + +#if DT_HAS_COMPAT_STATUS_OKAY(andestech_l2c) + /* Enable D-cache CM (Coherence Manager). */ + li t0, (1 << 19) csrs NDS_MCACHE_CTL, t0 /* Check if CPU support CM or not. */ @@ -52,12 +56,12 @@ check_cm_enabled: beqz t0, check_cm_enabled cache_enable_finish: +#endif /* DT_HAS_COMPAT_STATUS_OKAY(andestech_l2c) */ #endif /* Enable misaligned access and non-blocking load */ li t0, (1 << 8) | (1 << 6) csrs NDS_MMISC_CTL, t0 - j __start - - .option pop + /* Jump to __initialize */ + call __initialize diff --git a/arch/riscv/custom/nuclei/CMakeLists.txt b/arch/riscv/custom/nuclei/CMakeLists.txt new file mode 100644 index 0000000000000..f75aec6b31176 --- /dev/null +++ b/arch/riscv/custom/nuclei/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/gd/gd32/gd32vf103/nuclei_csr.h b/arch/riscv/custom/nuclei/nuclei_csr.h similarity index 97% rename from soc/gd/gd32/gd32vf103/nuclei_csr.h rename to arch/riscv/custom/nuclei/nuclei_csr.h index 4bc1f496fabe6..8186566f09e11 100644 --- a/soc/gd/gd32/gd32vf103/nuclei_csr.h +++ b/arch/riscv/custom/nuclei/nuclei_csr.h @@ -13,8 +13,8 @@ * Use arch/riscv/csr.h for RISC-V standard CSR and definitions. */ -#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_ -#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_ +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_NUCLEI_CSR_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_NUCLEI_CSR_H_ #include @@ -239,4 +239,4 @@ extern "C" { } #endif -#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_ */ +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_NUCLEI_CSR_H_ */ diff --git a/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt b/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt new file mode 100644 index 0000000000000..f75aec6b31176 --- /dev/null +++ b/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/openhwgroup/cva6/cva6.h b/arch/riscv/custom/openhwgroup/cva6/cva6_csr.h similarity index 59% rename from soc/openhwgroup/cva6/cva6.h rename to arch/riscv/custom/openhwgroup/cva6/cva6_csr.h index e728eb77e8cec..09edcee6f7104 100644 --- a/soc/openhwgroup/cva6/cva6.h +++ b/arch/riscv/custom/openhwgroup/cva6/cva6_csr.h @@ -8,8 +8,8 @@ * OpenHwGroup CVA6 declarations */ -#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H -#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_ #ifdef __cplusplus extern "C" { @@ -24,17 +24,17 @@ extern "C" { * */ -#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1 -#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0 +#define CVA6_DCACHE 0x7C1 +#define CVA6_ICACHE 0x7C0 -#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE 0x1 -#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0 +#define CVA6_DCACHE_ENABLE 0x1 +#define CVA6_DCACHE_DISABLE 0x0 -#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE 0x1 -#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0 +#define CVA6_ICACHE_ENABLE 0x1 +#define CVA6_ICACHE_DISABLE 0x0 #ifdef __cplusplus } #endif -#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */ +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_ */ diff --git a/arch/riscv/custom/openisa/ri5cy/CMakeLists.txt b/arch/riscv/custom/openisa/ri5cy/CMakeLists.txt new file mode 100644 index 0000000000000..68f3febfdea79 --- /dev/null +++ b/arch/riscv/custom/openisa/ri5cy/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +# Let's rely on `-march` being generated by the CMake script based on which `CONFIG_RISCV_ISA_EXT_*` +# options are y-selected; provide full arch string with the custom extension otherwise. +if(NOT CONFIG_RISCV_GENERIC_TOOLCHAIN) + zephyr_compile_options(-march=rv32imcxpulpv2) +endif() diff --git a/arch/riscv/custom/openisa/ri5cy/csr_context.h b/arch/riscv/custom/openisa/ri5cy/csr_context.h new file mode 100644 index 0000000000000..4c9b455e11dfb --- /dev/null +++ b/arch/riscv/custom/openisa/ri5cy/csr_context.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 Foundries.io Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE. + */ + +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_CONTEXT_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_CONTEXT_H_ + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + +/* Extra state for RI5CY hardware loop registers. */ +#define CUSTOM_CSR_ESF_MEMBERS \ + uint32_t lpstart0; \ + uint32_t lpend0; \ + uint32_t lpcount0; \ + uint32_t lpstart1; \ + uint32_t lpend1; \ + uint32_t lpcount1 + +/* Initial saved state. */ +#define CUSTOM_CSR_ESF_INIT \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0 + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_CONTEXT_H_ */ diff --git a/arch/riscv/custom/openisa/ri5cy/csr_irq.inc b/arch/riscv/custom/openisa/ri5cy/csr_irq.inc new file mode 100644 index 0000000000000..db32c4e5b0cd0 --- /dev/null +++ b/arch/riscv/custom/openisa/ri5cy/csr_irq.inc @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018 Foundries.io Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + + .macro __custom_csr_save_context __soc_esf_reg reg + + csrr \reg, RI5CY_LPSTART0 + sw \reg, __soc_esf_t_lpstart0_OFFSET(\__soc_esf_reg) + csrr \reg, RI5CY_LPEND0 + sw \reg, __soc_esf_t_lpend0_OFFSET(\__soc_esf_reg) + csrr \reg, RI5CY_LPCOUNT0 + sw \reg, __soc_esf_t_lpcount0_OFFSET(\__soc_esf_reg) + csrr \reg, RI5CY_LPSTART1 + sw \reg, __soc_esf_t_lpstart1_OFFSET(\__soc_esf_reg) + csrr \reg, RI5CY_LPEND1 + sw \reg, __soc_esf_t_lpend1_OFFSET(\__soc_esf_reg) + csrr \reg, RI5CY_LPCOUNT1 + sw \reg, __soc_esf_t_lpcount1_OFFSET(\__soc_esf_reg) + + .endm + + .macro __custom_csr_restore_context __soc_esf_reg reg + + lw \reg, __soc_esf_t_lpstart0_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPSTART0, \reg + lw \reg, __soc_esf_t_lpend0_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPEND0, \reg + lw \reg, __soc_esf_t_lpcount0_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPCOUNT0, \reg + lw \reg, __soc_esf_t_lpstart1_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPSTART1, \reg + lw \reg, __soc_esf_t_lpend1_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPEND1, \reg + lw \reg, __soc_esf_t_lpcount1_OFFSET(\__soc_esf_reg) + csrw RI5CY_LPCOUNT1, \reg + + .endm + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/arch/riscv/custom/openisa/ri5cy/csr_offsets.h b/arch/riscv/custom/openisa/ri5cy/csr_offsets.h new file mode 100644 index 0000000000000..5634746eab9dd --- /dev/null +++ b/arch/riscv/custom/openisa/ri5cy/csr_offsets.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018 Foundries.io Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_OFFSETS. + */ + +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_OFFSETS_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_OFFSETS_H_ + +#ifdef CONFIG_RISCV_SOC_OFFSETS + +#define GEN_CUSTOM_CSR_OFFSET_SYMS() \ + GEN_OFFSET_SYM(soc_esf_t, lpstart0); \ + GEN_OFFSET_SYM(soc_esf_t, lpend0); \ + GEN_OFFSET_SYM(soc_esf_t, lpcount0); \ + GEN_OFFSET_SYM(soc_esf_t, lpstart1); \ + GEN_OFFSET_SYM(soc_esf_t, lpend1); \ + GEN_OFFSET_SYM(soc_esf_t, lpcount1) + +#endif /* CONFIG_RISCV_SOC_OFFSETS */ + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_OFFSETS_H_ */ diff --git a/soc/openisa/rv32m1/soc_ri5cy.h b/arch/riscv/custom/openisa/ri5cy/ri5cy_csr.h similarity index 82% rename from soc/openisa/rv32m1/soc_ri5cy.h rename to arch/riscv/custom/openisa/ri5cy/ri5cy_csr.h index d9158935e088a..5e8b348bd2492 100644 --- a/soc/openisa/rv32m1/soc_ri5cy.h +++ b/arch/riscv/custom/openisa/ri5cy/ri5cy_csr.h @@ -4,8 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ -#define SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* Control and Status Registers (CSRs) available for RI5CY. */ #define RI5CY_USTATUS 0x000 @@ -40,4 +44,8 @@ #define RI5CY_PRIVLV 0xC10 #define RI5CY_MHARTID 0xF14 -#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ */ +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_RI5CY_CSR_H_ */ diff --git a/arch/riscv/custom/openisa/zero_riscy/CMakeLists.txt b/arch/riscv/custom/openisa/zero_riscy/CMakeLists.txt new file mode 100644 index 0000000000000..f75aec6b31176 --- /dev/null +++ b/arch/riscv/custom/openisa/zero_riscy/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/openisa/rv32m1/soc_zero_riscy.h b/arch/riscv/custom/openisa/zero_riscy/zero_riscy_csr.h similarity index 76% rename from soc/openisa/rv32m1/soc_zero_riscy.h rename to arch/riscv/custom/openisa/zero_riscy/zero_riscy_csr.h index 43cd144823a07..7e0ad555a32d1 100644 --- a/soc/openisa/rv32m1/soc_zero_riscy.h +++ b/arch/riscv/custom/openisa/zero_riscy/zero_riscy_csr.h @@ -4,8 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ -#define SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ +#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_ZERO_RISCY_CSR_H_ +#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_ZERO_RISCY_CSR_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* Control and Status Registers (CSRs) available for ZERO_RISCY. */ #define ZERO_RISCY_MSTATUS 0x300U @@ -28,4 +32,8 @@ #define ZERO_RISCY_PCMR 0x7A1U #define ZERO_RISCY_MHARTID 0xF14U -#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ */ +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENISA_ZERO_RISCY_CSR_H_ */ diff --git a/arch/riscv/custom/thead/CMakeLists.txt b/arch/riscv/custom/thead/CMakeLists.txt new file mode 100644 index 0000000000000..f2774d8a1f0b4 --- /dev/null +++ b/arch/riscv/custom/thead/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_THEAD_CMO cache_xtheadcmo.c) +zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_THEAD_CMO_E907 cache_xtheadcmo_e907.c) diff --git a/arch/riscv/custom/thead/Kconfig b/arch/riscv/custom/thead/Kconfig new file mode 100644 index 0000000000000..4c1d57a2ebaa5 --- /dev/null +++ b/arch/riscv/custom/thead/Kconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config CPU_HAS_THEAD_CMO + bool + help + The Xuantie core supports XTHeadCmo extension. + +config RISCV_CUSTOM_CSR_THEAD_CMO + bool + depends on CPU_HAS_THEAD_CMO + default y if CACHE_MANAGEMENT + help + This option enables the cache operation for XuanTie family of CPUs. + +config RISCV_CUSTOM_CSR_THEAD_CMO_E907 + bool + depends on CPU_HAS_THEAD_CMO + depends on DT_HAS_XUANTIE_E907_ENABLED + default y if CACHE_MANAGEMENT + help + This option enables the additional cache operation for XuanTie E907 cores. diff --git a/arch/riscv/custom/thead/Kconfig.core b/arch/riscv/custom/thead/Kconfig.core new file mode 100644 index 0000000000000..3550e91957fa4 --- /dev/null +++ b/arch/riscv/custom/thead/Kconfig.core @@ -0,0 +1,20 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config CPU_XUANTIE_E907 + bool + select GEN_IRQ_VECTOR_TABLE + select INCLUDE_RESET_VECTOR + select RISCV_HAS_CLIC + select RISCV_MACHINE_TIMER + select RISCV_PRIVILEGED + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_VECTORED_MODE + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select CPU_HAS_THEAD_CMO diff --git a/arch/riscv/core/xuantie/cache_xtheadcmo.c b/arch/riscv/custom/thead/cache_xtheadcmo.c similarity index 100% rename from arch/riscv/core/xuantie/cache_xtheadcmo.c rename to arch/riscv/custom/thead/cache_xtheadcmo.c diff --git a/arch/riscv/core/xuantie/cache_xtheadcmo_e907.c b/arch/riscv/custom/thead/cache_xtheadcmo_e907.c similarity index 100% rename from arch/riscv/core/xuantie/cache_xtheadcmo_e907.c rename to arch/riscv/custom/thead/cache_xtheadcmo_e907.c diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig index f34e627aed53f..b61e901b2a47c 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig @@ -1,15 +1,6 @@ CONFIG_XIP=n CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# Serial driver options CONFIG_SERIAL=y - -# GPIO driver options CONFIG_GPIO=y - -# PMP granularity options CONFIG_PMP_GRANULARITY=8 - -# EXEC.IT options -CONFIG_SOC_ANDES_V5_EXECIT=y diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig index f34e627aed53f..b61e901b2a47c 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig @@ -1,15 +1,6 @@ CONFIG_XIP=n CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# Serial driver options CONFIG_SERIAL=y - -# GPIO driver options CONFIG_GPIO=y - -# PMP granularity options CONFIG_PMP_GRANULARITY=8 - -# EXEC.IT options -CONFIG_SOC_ANDES_V5_EXECIT=y diff --git a/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig index 881ec1fdbefc0..b7d0f97e9ca64 100644 --- a/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig +++ b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig @@ -8,6 +8,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# HW DSP options -CONFIG_TELINK_B91_HWDSP=n diff --git a/drivers/cache/cache_andes.c b/drivers/cache/cache_andes.c index eb9dcc7684371..6b5c7a7c79fb5 100644 --- a/drivers/cache/cache_andes.c +++ b/drivers/cache/cache_andes.c @@ -4,13 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc_v5.h" - #include #include #include #include #include +#include LOG_MODULE_REGISTER(cache_andes, CONFIG_CACHE_LOG_LEVEL); diff --git a/dts/bindings/cpu/xuantie,e907.yaml b/dts/bindings/cpu/xuantie,e907.yaml new file mode 100644 index 0000000000000..c5dfc5250cf58 --- /dev/null +++ b/dts/bindings/cpu/xuantie,e907.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Xuantie E907 Core CPU + +compatible: "xuantie,e907" + +include: riscv,cpus.yaml + +properties: + hardware-exec-breakpoint-count: + type: int + description: Number of hardware break points diff --git a/dts/riscv/bflb/bl61x.dtsi b/dts/riscv/bflb/bl61x.dtsi index 1564933c5204a..b2936b8b901c0 100644 --- a/dts/riscv/bflb/bl61x.dtsi +++ b/dts/riscv/bflb/bl61x.dtsi @@ -79,6 +79,8 @@ compatible = "xuantie,e907", "riscv"; reg = <0>; riscv,isa = "rv32imafcp"; + i-cache-line-size = <32>; + d-cache-line-size = <32>; hardware-exec-breakpoint-count = <4>; status = "okay"; diff --git a/dts/riscv/telink/telink_b91.dtsi b/dts/riscv/telink/telink_b91.dtsi index aa6f166311f31..d572eace65b1e 100644 --- a/dts/riscv/telink/telink_b91.dtsi +++ b/dts/riscv/telink/telink_b91.dtsi @@ -23,7 +23,7 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <24000000>; - compatible = "telink,b91", "riscv"; + compatible = "telink,b91", "andestech,andescore-v5", "riscv"; riscv,isa = "rv32imac_zicsr_zifencei"; hlic: interrupt-controller { diff --git a/soc/andestech/ae350/CMakeLists.txt b/soc/andestech/ae350/CMakeLists.txt index 8c7f70a5b8c16..fdb98a7f8cba6 100644 --- a/soc/andestech/ae350/CMakeLists.txt +++ b/soc/andestech/ae350/CMakeLists.txt @@ -4,26 +4,19 @@ zephyr_include_directories(.) zephyr_sources( soc.c - start.S soc_irq.S ) -zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_PMA pma.c) -zephyr_linker_sources(ROM_START SORT_KEY 0x0 common_linker/init.ld) -zephyr_linker_sources_ifdef(CONFIG_SOC_ANDES_V5_EXECIT RODATA SORT_KEY 0x0 common_linker/execit.ld) -zephyr_linker_sources_ifdef(CONFIG_XIP RAM_SECTIONS SORT_KEY 0x0 common_linker/ram_start_nonzero.ld) +zephyr_linker_sources_ifdef(CONFIG_XIP RAM_SECTIONS SORT_KEY 0x0 ram_start_nonzero.ld) +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") # Note: AndeStar V5 DSP needs custom Andes V5 toolchain -if(CONFIG_SOC_ANDES_V5_HWDSP) +if(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP) zephyr_cc_option(-mext-dsp) endif() # Note: AndeStar V5 EXEC.IT needs custom Andes V5 toolchain -if(CONFIG_SOC_ANDES_V5_EXECIT) +if(CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECIT) zephyr_cc_option(-mexecit) zephyr_ld_options(-Wl,--mexecit) endif() - -if(CONFIG_SOC_SERIES_ANDES_AE350) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") -endif() diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig index 61db6d1772782..da4cc0193889c 100644 --- a/soc/andestech/ae350/Kconfig +++ b/soc/andestech/ae350/Kconfig @@ -11,11 +11,17 @@ config SOC_SERIES_ANDES_AE350 select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR select CPU_HAS_DCACHE select CPU_HAS_ICACHE - select CACHE_MANAGEMENT if DCACHE + select CPU_HAS_ANDES_EXECIT + select CPU_HAS_ANDES_HWDSP + select CPU_HAS_ANDES_PFT + select CPU_HAS_ANDES_PMA + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT + select ATOMIC_OPERATIONS_BUILTIN + select SOC_EARLY_INIT_HOOK if RISCV_CUSTOM_CSR_ANDES_PMA + select SOC_PER_CORE_INIT_HOOK if RISCV_CUSTOM_CSR_ANDES_PMA imply XIP config SOC_ANDES_AE350 @@ -66,49 +72,24 @@ config DOUBLE_PRECISION_FPU endchoice config SOC_ANDES_V5_HWDSP - bool "AndeStar V5 DSP ISA" - select RISCV_SOC_CONTEXT_SAVE - depends on !RISCV_GENERIC_TOOLCHAIN - help - This option enables the AndeStar v5 hardware DSP, in order to - support using the DSP instructions. + bool + select DEPRECATED config SOC_ANDES_V5_PFT - bool "Andes V5 PowerBrake extension" - default y - select RISCV_SOC_CONTEXT_SAVE - help - The PowerBrake extension throttles performance by reducing instruction - executing rate. + bool + select DEPRECATED config SOC_ANDES_V5_EXECIT - bool "Andes V5 EXEC.IT extension" - depends on RISCV_ISA_EXT_C - depends on !RISCV_GENERIC_TOOLCHAIN - depends on !LINKER_USE_NO_RELAX - help - The EXEC.IT extension (Execution on Instruction Table) generate - a look-up table and replaces suitable 32-bit instructions with - the 16-bit "exec.it ". + bool + select DEPRECATED config SOC_ANDES_V5_PMA - bool "Andes V5 Physical Memory Attribute (PMA)" - select ARCH_HAS_NOCACHE_MEMORY_SUPPORT - select SOC_EARLY_INIT_HOOK - select SOC_PER_CORE_INIT_HOOK - help - This option enables the Andes V5 PMA, in order to support SW to - configure physical memory attribute by PMA CSRs. The address - matching of Andes V5 PMA is like RISC-V PMP NAPOT mode - (power-of-two alignment). + bool + select DEPRECATED config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE - int - depends on SOC_ANDES_V5_PMA - default 4096 - help - Minimum size (and alignment) of an PMA region. Use this symbol - to guarantee minimum size and alignment of PMA regions. + bool + select DEPRECATED config SOC_ANDES_V5_L2C bool diff --git a/soc/andestech/ae350/Kconfig.defconfig b/soc/andestech/ae350/Kconfig.defconfig index 07212488424f8..81a1ce0d5c8f1 100644 --- a/soc/andestech/ae350/Kconfig.defconfig +++ b/soc/andestech/ae350/Kconfig.defconfig @@ -3,17 +3,11 @@ if SOC_SERIES_ANDES_AE350 -# Kconfig picks the first default with a satisfied condition. -# SoC defaults should be parsed before SoC Series defaults, because SoCs usually -# overrides SoC Series values. rsource "Kconfig.defconfig.ae*" config SYS_CLOCK_HW_CYCLES_PER_SEC default 60000000 -config KERNEL_ENTRY - default "entry" - config RISCV_GENERIC_TOOLCHAIN default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" default n diff --git a/soc/andestech/ae350/common_linker/init.ld b/soc/andestech/ae350/common_linker/init.ld deleted file mode 100644 index 0feb828931ba8..0000000000000 --- a/soc/andestech/ae350/common_linker/init.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Andes Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -KEEP(*(.init.*)) diff --git a/soc/andestech/ae350/linker.ld b/soc/andestech/ae350/linker.ld deleted file mode 100644 index 36e4e51f2e879..0000000000000 --- a/soc/andestech/ae350/linker.ld +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) 2016-2017 Jean-Paul Etienne - * Copyright (c) 2021 Andes Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the ae350 platform - */ - -#include - -#include -#include - -#include -#include - -#ifdef CONFIG_XIP -#define ROMABLE_REGION ROM -#else -#define ROMABLE_REGION RAM -#endif -#define RAMABLE_REGION RAM - -#define _EXCEPTION_SECTION_NAME exceptions -#define _RESET_SECTION_NAME reset - -#ifdef CONFIG_XIP -#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay) -#ifdef CONFIG_FLASH_LOAD_OFFSET -#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \ - CONFIG_FLASH_LOAD_OFFSET) -#else /* !CONFIG_FLASH_LOAD_OFFSET */ -#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) -#endif /* CONFIG_FLASH_LOAD_OFFSET */ -#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) -#elif DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), jedec_spi_nor) -/* For jedec,spi-nor we expect the spi controller to memory map the flash - * and for that mapping to be the second register property of the spi - * controller. - */ -#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash)) -#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1) -#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1) -#endif -#else /* CONFIG_XIP */ -#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS -#define ROM_SIZE KB(CONFIG_SRAM_SIZE) -#endif /* CONFIG_XIP */ - -#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS -#define RAM_SIZE KB(CONFIG_SRAM_SIZE) - -#ifdef CONFIG_RISCV_PMP - #define MPU_MIN_SIZE CONFIG_PMP_GRANULARITY - #define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE); - #if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT) - #define MPU_ALIGN(region_size) \ - . = ALIGN(MPU_MIN_SIZE); \ - . = ALIGN( 1 << LOG2CEIL(region_size)) - #else - #define MPU_ALIGN(region_size) \ - . = ALIGN(MPU_MIN_SIZE) - #endif -#else - #define MPU_MIN_SIZE_ALIGN - #define MPU_ALIGN(region_size) . = ALIGN(4) -#endif - -MEMORY -{ -#ifdef CONFIG_XIP - ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE -#endif - RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE - - LINKER_DT_REGIONS() - - /* Used by and documented in include/linker/intlist.ld */ - IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K -} - -ENTRY(CONFIG_KERNEL_ENTRY) - -SECTIONS - { - -#include - -#ifdef CONFIG_LLEXT -#include -#endif - - /* - * The .plt and .iplt are here according to - * 'riscv32-zephyr-elf-ld --verbose', before text section. - */ - SECTION_PROLOGUE(.plt,,) - { - *(.plt) - } - - SECTION_PROLOGUE(.iplt,,) - { - *(.iplt) - } - - GROUP_START(ROMABLE_REGION) - - SECTION_PROLOGUE(rom_start,,) - { - . = ALIGN(16); - MPU_ALIGN(__rom_region_size); - __rom_region_start = ABSOLUTE(.); -/* Located in generated directory. This file is populated by calling - * zephyr_linker_sources(ROM_START ...). - */ -#include - } GROUP_LINK_IN(ROMABLE_REGION) - -#ifdef CONFIG_CODE_DATA_RELOCATION -#include -#endif - - SECTION_PROLOGUE(_RESET_SECTION_NAME,,) - { - KEEP(*(.reset.*)) - } GROUP_LINK_IN(ROMABLE_REGION) - - SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,) - { - KEEP(*(".exception.entry.*")) - *(".exception.other.*") - } GROUP_LINK_IN(ROMABLE_REGION) - - SECTION_PROLOGUE(_TEXT_SECTION_NAME,,) - { - . = ALIGN(4); - KEEP(*(.openocd_debug)) - KEEP(*(".openocd_debug.*")) - - __text_region_start = .; - - *(.text) - *(".text.*") - *(.gnu.linkonce.t.*) -#include - } GROUP_LINK_IN(ROMABLE_REGION) - - __text_region_end = .; - - __rodata_region_start = .; -#include -/* Located in generated directory. This file is populated by calling - * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. - */ -#include -#include - - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) - { - . = ALIGN(4); - *(.srodata) - *(".srodata.*") - *(.rodata) - *(".rodata.*") - *(.gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. - */ -#include -#include - . = ALIGN(4); - } GROUP_LINK_IN(ROMABLE_REGION) - -#include - __rodata_region_end = .; - - /* For non-XIP system, __rom_region_end symbol should be set to - * the end of common ROMABLE_REGIONs (text and rodata) instead of - * the linker script end, so it wouldn't mistakenly contain - * RAMABLE_REGION in it. - */ -#ifndef CONFIG_XIP -#ifdef CONFIG_RISCV_PMP - SECTION_PROLOGUE(rom_mpu_padding,,) - { - MPU_ALIGN(__rodata_region_end - __rom_region_start); - } GROUP_LINK_IN(ROMABLE_REGION) -#endif /* CONFIG_RISCV_PMP */ - - __rom_region_end = .; - __rom_region_size = __rom_region_end - __rom_region_start; -#endif /* CONFIG_XIP */ - GROUP_END(ROMABLE_REGION) - - GROUP_START(RAMABLE_REGION) - - . = RAM_BASE; - _image_ram_start = .; - -#ifdef CONFIG_SOC_ANDES_V5_PMA -#pragma push_macro("MPU_ALIGN") -#undef MPU_ALIGN -/* Make linker section alignment comply with PMA granularity. */ -#define MPU_ALIGN(region_size) \ - . = ALIGN(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE); \ - . = ALIGN( 1 << LOG2CEIL(region_size)) -#endif - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. - */ -#include - -#ifdef CONFIG_SOC_ANDES_V5_PMA -#pragma pop_macro("MPU_ALIGN") -#endif - -#if defined(CONFIG_USERSPACE) -#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN -#define SMEM_PARTITION_ALIGN MPU_ALIGN - -#include - - _app_smem_size = _app_smem_end - _app_smem_start; - _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); -#endif /* CONFIG_USERSPACE */ - - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - MPU_MIN_SIZE_ALIGN - /* - * For performance, BSS section is assumed to be 4 byte aligned and - * a multiple of 4 bytes - */ - . = ALIGN(4); - __bss_start = .; - __kernel_ram_start = .; - *(.sbss) - *(".sbss.*") - *(.bss) - *(".bss.*") - COMMON_SYMBOLS - -#ifdef CONFIG_CODE_DATA_RELOCATION -#include -#endif - - /* - * As memory is cleared in words only, it is simpler to ensure the BSS - * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes. - */ - __bss_end = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#include - - SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) - { - . = ALIGN(4); - /* _image_ram_start = .; */ - __data_region_start = .; - __data_start = .; - - *(.data) - *(".data.*") - -#ifdef CONFIG_RISCV_GP - /* - * RISC-V architecture has 12-bit signed immediate offsets in the - * instructions. If we can put the most commonly accessed globals - * in a special 4K span of memory addressed by the GP register, then - * we can access those values in a single instruction, saving both - * codespace and runtime. - * - * Since these immediate offsets are signed, place gp 0x800 past the - * beginning of .sdata so that we can use both positive and negative - * offsets. - */ - . = ALIGN(8); - PROVIDE (__global_pointer$ = . + 0x800); -#endif - - *(.sdata .sdata.* .gnu.linkonce.s.*) - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. - */ -#include - -#ifdef CONFIG_CODE_DATA_RELOCATION -#include -#endif - - __data_end = .; - - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - __data_size = __data_end - __data_start; - __data_load_start = LOADADDR(_DATA_SECTION_NAME); - - __data_region_load_start = LOADADDR(_DATA_SECTION_NAME); - -#include -#include -#include - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. - */ -#include - - __data_region_end = .; - - __kernel_ram_end = .; - __kernel_ram_size = __kernel_ram_end - __kernel_ram_start; - -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) -GROUP_START(ITCM) - - SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8)) - { - __itcm_start = .; - *(.itcm) - *(".itcm.*") - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. */ -#include - - __itcm_end = .; - } GROUP_LINK_IN(ITCM AT> ROMABLE_REGION) - - __itcm_size = __itcm_end - __itcm_start; - __itcm_load_start = LOADADDR(_ITCM_SECTION_NAME); - -GROUP_END(ITCM) -#endif - -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) -GROUP_START(DTCM) - - SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8)) - { - __dtcm_start = .; - __dtcm_bss_start = .; - *(.dtcm_bss) - *(".dtcm_bss.*") - __dtcm_bss_end = .; - } GROUP_LINK_IN(DTCM) - - SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8)) - { - __dtcm_noinit_start = .; - *(.dtcm_noinit) - *(".dtcm_noinit.*") - __dtcm_noinit_end = .; - } GROUP_LINK_IN(DTCM) - - SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8)) - { - __dtcm_data_start = .; - *(.dtcm_data) - *(".dtcm_data.*") - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. */ -#include - - __dtcm_data_end = .; - } GROUP_LINK_IN(DTCM AT> ROMABLE_REGION) - - __dtcm_end = .; - - __dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME); - -GROUP_END(DTCM) -#endif - -/* Located in generated directory. This file is populated by the - * zephyr_linker_sources() Cmake function. - */ -#include - -#define LAST_RAM_ALIGN MPU_MIN_SIZE_ALIGN - -#include - - GROUP_END(RAMABLE_REGION) - -#include - - /DISCARD/ : { *(.note.GNU-stack) } - - SECTION_PROLOGUE(.riscv.attributes, 0,) - { - KEEP(*(.riscv.attributes)) - KEEP(*(.gnu.attributes)) - } - -/* Output section descriptions are needed for these sections to suppress - * warnings when "--orphan-handling=warn" is set for lld. - */ -#if defined(CONFIG_LLVM_USE_LLD) - SECTION_PROLOGUE(.symtab, 0,) { *(.symtab) } - SECTION_PROLOGUE(.strtab, 0,) { *(.strtab) } - SECTION_PROLOGUE(.shstrtab, 0,) { *(.shstrtab) } -#endif - - /* Sections generated from 'zephyr,memory-region' nodes */ - LINKER_DT_SECTIONS() - -#ifdef CONFIG_XIP -/* Must be last in romable region */ -SECTION_PROLOGUE(.last_section,,) -{ - /* .last_section contains a fixed word to ensure location counter and actual - * rom region data usage match when CONFIG_LINKER_LAST_SECTION_ID=y. */ - KEEP(*(.last_section)) -} GROUP_LINK_IN(ROMABLE_REGION) - -/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid - * to set __rom_region_end symbol at the end of linker script and - * doesn't mistakenly contain the RAMABLE_REGION in it. - */ -#ifndef CONFIG_RISCV_PMP -__rom_region_end = LOADADDR(.last_section) + SIZEOF(.last_section); -#else -/* Padding __rom_region_end to matches the requirement of the MPU region. - * __rom_region_size is used to configure the MPU region, but the actual rom - * region data usage is ends at .last_section. - */ -SECTION_PROLOGUE(rom_mpu_padding,(NOLOAD),) -{ - MPU_ALIGN(__rom_region_size); -} GROUP_LINK_IN(ROMABLE_REGION) -__rom_region_end = LOADADDR(rom_mpu_padding) + SIZEOF(rom_mpu_padding); -#endif /* !CONFIG_RISCV_PMP */ - -/* To provide the rom region size as a const expression, - * calculate this value here. - */ -__rom_region_size = __rom_region_end - __rom_region_start; -#endif - -} diff --git a/soc/andestech/ae350/common_linker/ram_start_nonzero.ld b/soc/andestech/ae350/ram_start_nonzero.ld similarity index 100% rename from soc/andestech/ae350/common_linker/ram_start_nonzero.ld rename to soc/andestech/ae350/ram_start_nonzero.ld diff --git a/soc/andestech/ae350/soc.c b/soc/andestech/ae350/soc.c index 852da6d811342..58e5afaddfbfb 100644 --- a/soc/andestech/ae350/soc.c +++ b/soc/andestech/ae350/soc.c @@ -4,22 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "pma.h" +#include #ifdef CONFIG_SOC_PER_CORE_INIT_HOOK void soc_per_core_init_hook(void) { -#ifdef CONFIG_SOC_ANDES_V5_PMA +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA pma_init_per_core(); -#endif /* SOC_ANDES_V5_PMA */ +#endif /* CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA */ } #endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ #ifdef CONFIG_SOC_EARLY_INIT_HOOK void soc_early_init_hook(void) { -#ifdef CONFIG_SOC_ANDES_V5_PMA +#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA pma_init(); -#endif /* CONFIG_SOC_ANDES_V5_PMA */ +#endif /* CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA */ } #endif /* CONFIG_SOC_EARLY_INIT_HOOK */ diff --git a/soc/andestech/ae350/soc_context.h b/soc/andestech/ae350/soc_context.h index 581a1ef534a19..57825f3177036 100644 --- a/soc/andestech/ae350/soc_context.h +++ b/soc/andestech/ae350/soc_context.h @@ -11,33 +11,17 @@ #ifndef SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_ #define SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_ +#include + #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* Andes V5 specific registers. */ -#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP) - #define SOC_ESF_MEMBERS \ - uint32_t mxstatus; \ - uint32_t ucode \ - - #define SOC_ESF_INIT \ - 0, \ - 0 - -#elif defined(CONFIG_SOC_ANDES_V5_PFT) - #define SOC_ESF_MEMBERS \ - uint32_t mxstatus - - #define SOC_ESF_INIT \ - 0 - -#elif defined(CONFIG_SOC_ANDES_V5_HWDSP) - #define SOC_ESF_MEMBERS \ - uint32_t ucode - #define SOC_ESF_INIT \ - 0 +#define SOC_ESF_MEMBERS \ + CUSTOM_CSR_ESF_MEMBERS -#endif +#define SOC_ESF_INIT \ + CUSTOM_CSR_ESF_INIT #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/soc/andestech/ae350/soc_irq.S b/soc/andestech/ae350/soc_irq.S index d5e28d307f5ac..7e7a45a4c829b 100644 --- a/soc/andestech/ae350/soc_irq.S +++ b/soc/andestech/ae350/soc_irq.S @@ -4,10 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc_v5.h" #include #include +#include #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE @@ -17,36 +17,14 @@ GTEXT(__soc_restore_context) SECTION_FUNC(exception.other, __soc_save_context) -#ifdef CONFIG_SOC_ANDES_V5_PFT - csrr t0, NDS_MXSTATUS -#endif -#ifdef CONFIG_SOC_ANDES_V5_HWDSP - csrr t1, NDS_UCODE -#endif - -#ifdef CONFIG_SOC_ANDES_V5_PFT - sw t0, __soc_esf_t_mxstatus_OFFSET(a0) -#endif -#ifdef CONFIG_SOC_ANDES_V5_HWDSP - sw t1, __soc_esf_t_ucode_OFFSET(a0) -#endif + __custom_csr_save_context a0, t0 + ret SECTION_FUNC(exception.other, __soc_restore_context) -#ifdef CONFIG_SOC_ANDES_V5_PFT - lw t0, __soc_esf_t_mxstatus_OFFSET(a0) -#endif -#ifdef CONFIG_SOC_ANDES_V5_HWDSP - lw t1, __soc_esf_t_ucode_OFFSET(a0) -#endif - -#ifdef CONFIG_SOC_ANDES_V5_PFT - csrw NDS_MXSTATUS, t0 -#endif -#ifdef CONFIG_SOC_ANDES_V5_HWDSP - csrw NDS_UCODE, t1 -#endif + __custom_csr_restore_context a0, t0 + ret #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/soc/andestech/ae350/soc_offsets.h b/soc/andestech/ae350/soc_offsets.h index 5a8514485e2dd..8c8cf718e3c19 100644 --- a/soc/andestech/ae350/soc_offsets.h +++ b/soc/andestech/ae350/soc_offsets.h @@ -11,23 +11,13 @@ #ifndef SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_ #define SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_ +#include + #ifdef CONFIG_RISCV_SOC_OFFSETS /* Andes V5 specific registers. */ -#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, mxstatus); \ - GEN_OFFSET_SYM(soc_esf_t, ucode) - -#elif defined(CONFIG_SOC_ANDES_V5_PFT) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, mxstatus) - -#elif defined(CONFIG_SOC_ANDES_V5_HWDSP) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, ucode) - -#endif +#define GEN_SOC_OFFSET_SYMS() \ + GEN_CUSTOM_CSR_OFFSET_SYMS() #endif /* CONFIG_RISCV_SOC_OFFSETS */ diff --git a/soc/bflb/bl61x/Kconfig b/soc/bflb/bl61x/Kconfig index bf311619847fa..d13afeffc0584 100644 --- a/soc/bflb/bl61x/Kconfig +++ b/soc/bflb/bl61x/Kconfig @@ -15,4 +15,5 @@ config SOC_SERIES_BL61X select SOC_EARLY_INIT_HOOK select SYSCON select XIP - select XUANTIE_E907 + select CPU_XUANTIE_E907 + select CACHE_MANAGEMENT diff --git a/soc/egis/et171/CMakeLists.txt b/soc/egis/et171/CMakeLists.txt index 7547dab8350e2..d1d0f0bff410c 100644 --- a/soc/egis/et171/CMakeLists.txt +++ b/soc/egis/et171/CMakeLists.txt @@ -5,6 +5,7 @@ zephyr_include_directories(.) zephyr_sources( soc.c start.S + soc_irq.S ) zephyr_linker_sources(ROM_START SORT_KEY 0x0 common_linker/init.ld) diff --git a/soc/egis/et171/Kconfig b/soc/egis/et171/Kconfig index 54dad5b7f897b..2d78bc2d8bfc6 100644 --- a/soc/egis/et171/Kconfig +++ b/soc/egis/et171/Kconfig @@ -14,10 +14,14 @@ config SOC_EGIS_ET171 select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR select CPU_HAS_FPU select CPU_HAS_DCACHE select CPU_HAS_ICACHE + select CPU_HAS_ANDES_EXECIT + select CPU_HAS_ANDES_HWDSP + select CPU_HAS_ANDES_PFT + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT select RISCV_PMP select HAS_FLASH_LOAD_OFFSET select SOC_EARLY_INIT_HOOK diff --git a/soc/egis/et171/Kconfig.defconfig b/soc/egis/et171/Kconfig.defconfig index e4a6a84674838..7dc97cd237c45 100644 --- a/soc/egis/et171/Kconfig.defconfig +++ b/soc/egis/et171/Kconfig.defconfig @@ -12,7 +12,7 @@ config KERNEL_ENTRY default "entry" config RISCV_GENERIC_TOOLCHAIN - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" config RISCV_SOC_INTERRUPT_INIT default y diff --git a/soc/egis/et171/soc_context.h b/soc/egis/et171/soc_context.h new file mode 100644 index 0000000000000..80747460b150e --- /dev/null +++ b/soc/egis/et171/soc_context.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE. + */ + +#ifndef SOC_RISCV_EGIS_ET171_SOC_CONTEXT_H_ +#define SOC_RISCV_EGIS_ET171_SOC_CONTEXT_H_ + +#include + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + +/* Egis ET171 specific registers. */ + +#define SOC_ESF_MEMBERS \ + CUSTOM_CSR_ESF_MEMBERS + +#define SOC_ESF_INIT \ + CUSTOM_CSR_ESF_INIT + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ + +#endif /* SOC_RISCV_EGIS_ET171_SOC_CONTEXT_H_ */ diff --git a/soc/egis/et171/soc_irq.S b/soc/egis/et171/soc_irq.S new file mode 100644 index 0000000000000..92a6f1d507bc9 --- /dev/null +++ b/soc/egis/et171/soc_irq.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include +#include +#include + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + +/* Exports */ +GTEXT(__soc_save_context) +GTEXT(__soc_restore_context) + +SECTION_FUNC(exception.other, __soc_save_context) + + __custom_csr_save_context a0, t0 + + ret + +SECTION_FUNC(exception.other, __soc_restore_context) + + __custom_csr_restore_context a0, t0 + + ret + +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/soc/egis/et171/soc_offsets.h b/soc/egis/et171/soc_offsets.h new file mode 100644 index 0000000000000..2a14fc92255ea --- /dev/null +++ b/soc/egis/et171/soc_offsets.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_OFFSETS. + */ + +#ifndef SOC_RISCV_EGIS_ET171_SOC_OFFSETS_H_ +#define SOC_RISCV_EGIS_ET171_SOC_OFFSETS_H_ + +#include + +#ifdef CONFIG_RISCV_SOC_OFFSETS + +/* Egis ET171 specific registers. */ +#define GEN_SOC_OFFSET_SYMS() \ + GEN_CUSTOM_CSR_OFFSET_SYMS() + +#endif /* CONFIG_RISCV_SOC_OFFSETS */ + +#endif /* SOC_RISCV_EGIS_ET171_SOC_OFFSETS_H_*/ diff --git a/soc/egis/et171/soc_v5.h b/soc/egis/et171/soc_v5.h deleted file mode 100644 index f15d6446284fa..0000000000000 --- a/soc/egis/et171/soc_v5.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 Andes Technology Corporation - * Copyright (c) 2025 Egis Technology Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __RISCV_ANDES_V5_SOC_V5_H_ -#define __RISCV_ANDES_V5_SOC_V5_H_ - -/* Control and Status Registers (CSRs) available for Andes V5 SoCs */ -#define NDS_MMISC_CTL 0x7D0 -#define NDS_MCACHE_CTL 0x7CA -#define NDS_MXSTATUS 0x7C4 -#define NDS_MCCTLBEGINADDR 0x7CB -#define NDS_MCCTLCOMMAND 0x7CC -#define NDS_MCCTLDATA 0x7CD -#define NDS_UITB 0x800 -#define NDS_UCODE 0x801 -#define NDS_UCCTLBEGINADDR 0x80B -#define NDS_UCCTLCOMMAND 0x80C -#define NDS_MICM_CFG 0xFC0 -#define NDS_MDCM_CFG 0xFC1 -#define NDS_MMSC_CFG 0xFC2 -#define NDS_MMSC_CFG2 0xFC3 -#define NDS_MRVARCH_CFG 0xFCA - -#endif /* __RISCV_ANDES_V5_SOC_V5_H_ */ diff --git a/soc/egis/et171/start.S b/soc/egis/et171/start.S index c26b61917a379..3475259cc6914 100644 --- a/soc/egis/et171/start.S +++ b/soc/egis/et171/start.S @@ -5,8 +5,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc_v5.h" - #include /* exports */ @@ -30,22 +28,6 @@ SECTION_FUNC(init, entry) header_end: -#ifdef CONFIG_ICACHE - /* Enable I cache with HW prefetcher. */ - li t0, (1 << 9) | (1 << 0) - csrs NDS_MCACHE_CTL, t0 -#endif - -#ifdef CONFIG_DCACHE - /* Enable D cache with HW prefetcher */ - li t0, (1 << 10) | (1 << 1) - csrs NDS_MCACHE_CTL, t0 -#endif - - /* Enable misaligned access and non-blocking load */ - li t0, (1 << 8) | (1 << 6) - csrs NDS_MMISC_CTL, t0 - j __start .option pop diff --git a/soc/gd/gd32/gd32vf103/entry.S b/soc/gd/gd32/gd32vf103/entry.S index 9c2fa3cadbc56..5ce47cb3aa677 100644 --- a/soc/gd/gd32/gd32vf103/entry.S +++ b/soc/gd/gd32/gd32vf103/entry.S @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "nuclei_csr.h" +#include #include #include diff --git a/soc/openhwgroup/cva6/soc_cache_management.c b/soc/openhwgroup/cva6/soc_cache_management.c index cb37c55a5ea08..e456f63670bb2 100644 --- a/soc/openhwgroup/cva6/soc_cache_management.c +++ b/soc/openhwgroup/cva6/soc_cache_management.c @@ -9,16 +9,16 @@ #include #include -#include "cva6.h" +#include void __weak arch_dcache_enable(void) { - csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE); + csr_write(CVA6_DCACHE, CVA6_DCACHE_ENABLE); } void __weak arch_dcache_disable(void) { - csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE); + csr_write(CVA6_DCACHE, CVA6_DCACHE_DISABLE); } int __weak arch_dcache_flush_all(void) @@ -66,12 +66,12 @@ int __weak arch_dcache_flush_and_invd_range(void *addr, size_t size) void __weak arch_icache_enable(void) { - csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE); + csr_write(CVA6_ICACHE, CVA6_ICACHE_ENABLE); } void __weak arch_icache_disable(void) { - csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE); + csr_write(CVA6_ICACHE, CVA6_ICACHE_DISABLE); } int __weak arch_icache_flush_all(void) diff --git a/soc/openisa/rv32m1/CMakeLists.txt b/soc/openisa/rv32m1/CMakeLists.txt index fcfda5f17eda8..86dd71ab47ef9 100644 --- a/soc/openisa/rv32m1/CMakeLists.txt +++ b/soc/openisa/rv32m1/CMakeLists.txt @@ -2,12 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -# Let's rely on `-march` being generated by the CMake script based on which `CONFIG_RISCV_ISA_EXT_*` -# options are y-selected; provide full arch string with the custom extension otherwise. -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY AND NOT CONFIG_RISCV_GENERIC_TOOLCHAIN) - zephyr_compile_options(-march=rv32imcxpulpv2) -endif() - zephyr_sources( vector.S soc_irq.S diff --git a/soc/openisa/rv32m1/soc.h b/soc/openisa/rv32m1/soc.h index a83f8fe080982..df58d26532854 100644 --- a/soc/openisa/rv32m1/soc.h +++ b/soc/openisa/rv32m1/soc.h @@ -96,10 +96,10 @@ static inline uint32_t rv32m1_intmux_line(unsigned int irq) #endif /* !_ASMLANGUAGE */ -#if defined(CONFIG_SOC_OPENISA_RV32M1_RI5CY) -#include "soc_ri5cy.h" -#elif defined(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) -#include "soc_zero_riscy.h" +#if defined(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED) +#include +#elif defined(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED) +#include #endif /* helper macro to convert from a DT_INST to HAL clock_ip_name */ diff --git a/soc/openisa/rv32m1/soc_context.h b/soc/openisa/rv32m1/soc_context.h index e1a675cd4026f..637f01ef46be7 100644 --- a/soc/openisa/rv32m1/soc_context.h +++ b/soc/openisa/rv32m1/soc_context.h @@ -11,26 +11,22 @@ #ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ #define SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ +#include + +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE + #ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY /* Extra state for RI5CY hardware loop registers. */ #define SOC_ESF_MEMBERS \ - uint32_t lpstart0; \ - uint32_t lpend0; \ - uint32_t lpcount0; \ - uint32_t lpstart1; \ - uint32_t lpend1; \ - uint32_t lpcount1 + CUSTOM_CSR_ESF_MEMBERS /* Initial saved state. */ -#define SOC_ESF_INIT \ - 0, \ - 0, \ - 0, \ - 0, \ - 0, \ - 0 +#define SOC_ESF_INIT \ + CUSTOM_CSR_ESF_INIT #endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ +#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ + #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ */ diff --git a/soc/openisa/rv32m1/soc_irq.S b/soc/openisa/rv32m1/soc_irq.S index 8333faa4236ca..94b5006a16821 100644 --- a/soc/openisa/rv32m1/soc_irq.S +++ b/soc/openisa/rv32m1/soc_irq.S @@ -9,6 +9,10 @@ #include +#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY +#include +#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ + /* Exports */ GTEXT(__soc_handle_irq) #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE @@ -49,36 +53,14 @@ SECTION_FUNC(exception.other, __soc_handle_irq) */ SECTION_FUNC(exception.other, __soc_save_context) #ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY - csrr t0, RI5CY_LPSTART0 - csrr t1, RI5CY_LPEND0 - csrr t2, RI5CY_LPCOUNT0 - sw t0, __soc_esf_t_lpstart0_OFFSET(a0) - sw t1, __soc_esf_t_lpend0_OFFSET(a0) - sw t2, __soc_esf_t_lpcount0_OFFSET(a0) - csrr t0, RI5CY_LPSTART1 - csrr t1, RI5CY_LPEND1 - csrr t2, RI5CY_LPCOUNT1 - sw t0, __soc_esf_t_lpstart1_OFFSET(a0) - sw t1, __soc_esf_t_lpend1_OFFSET(a0) - sw t2, __soc_esf_t_lpcount1_OFFSET(a0) + __custom_csr_save_context a0, t0 #endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ ret SECTION_FUNC(exception.other, __soc_restore_context) #ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY - lw t0, __soc_esf_t_lpstart0_OFFSET(a0) - lw t1, __soc_esf_t_lpend0_OFFSET(a0) - lw t2, __soc_esf_t_lpcount0_OFFSET(a0) - csrw RI5CY_LPSTART0, t0 - csrw RI5CY_LPEND0, t1 - csrw RI5CY_LPCOUNT0, t2 - lw t0, __soc_esf_t_lpstart1_OFFSET(a0) - lw t1, __soc_esf_t_lpend1_OFFSET(a0) - lw t2, __soc_esf_t_lpcount1_OFFSET(a0) - csrw RI5CY_LPSTART1, t0 - csrw RI5CY_LPEND1, t1 - csrw RI5CY_LPCOUNT1, t2 + __custom_csr_restore_context a0, t0 #endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ ret diff --git a/soc/openisa/rv32m1/soc_offsets.h b/soc/openisa/rv32m1/soc_offsets.h index 7e7ac08de78d6..803d1159ffc2a 100644 --- a/soc/openisa/rv32m1/soc_offsets.h +++ b/soc/openisa/rv32m1/soc_offsets.h @@ -15,6 +15,8 @@ #ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY +#include + #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* * Ensure offset macros are available in . @@ -23,12 +25,7 @@ * for use in assembly. */ #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, lpstart0); \ - GEN_OFFSET_SYM(soc_esf_t, lpend0); \ - GEN_OFFSET_SYM(soc_esf_t, lpcount0); \ - GEN_OFFSET_SYM(soc_esf_t, lpstart1); \ - GEN_OFFSET_SYM(soc_esf_t, lpend1); \ - GEN_OFFSET_SYM(soc_esf_t, lpcount1); \ + GEN_CUSTOM_CSR_OFFSET_SYMS(); \ GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \ (uint32_t)&EVENT0->INTPTPENDCLEAR) #else diff --git a/soc/telink/tlsr/tlsr951x/CMakeLists.txt b/soc/telink/tlsr/tlsr951x/CMakeLists.txt index 9e1dff40e4b1b..7bca7f33d7acd 100644 --- a/soc/telink/tlsr/tlsr951x/CMakeLists.txt +++ b/soc/telink/tlsr/tlsr951x/CMakeLists.txt @@ -13,7 +13,7 @@ zephyr_include_directories(.) zephyr_ld_options(-fuse-ld=bfd) # Set compile options -zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) +zephyr_compile_options_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP -mext-dsp) zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig index c538ed7516e47..d7e5bc152c2c2 100644 --- a/soc/telink/tlsr/tlsr951x/Kconfig +++ b/soc/telink/tlsr/tlsr951x/Kconfig @@ -15,19 +15,23 @@ config SOC_SERIES_TLSR951X select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select HAS_TELINK_DRIVERS select CPU_HAS_FPU - select INCLUDE_RESET_VECTOR + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_ANDES_HWDSP + select CPU_HAS_ANDES_PFT + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP + select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT imply XIP select SOC_EARLY_INIT_HOOK if SOC_SERIES_TLSR951X config TELINK_B91_HWDSP - bool "Support Hardware DSP" - select RISCV_SOC_CONTEXT_SAVE + bool + select DEPRECATED config TELINK_B91_PFT_ARCH - bool "Support performance throttling" - default y - select RISCV_SOC_CONTEXT_SAVE + bool + select DEPRECATED endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig index 777a0ac6f44e3..1cbe8821fab2a 100644 --- a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig +++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig @@ -30,4 +30,8 @@ config 2ND_LVL_INTR_00_OFFSET config HAS_FLASH_LOAD_OFFSET default y if BOOTLOADER_MCUBOOT +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/soc_context.h b/soc/telink/tlsr/tlsr951x/soc_context.h index 0f06686453988..8f2b9dd7d16ac 100644 --- a/soc/telink/tlsr/tlsr951x/soc_context.h +++ b/soc/telink/tlsr/tlsr951x/soc_context.h @@ -7,43 +7,16 @@ #ifndef SOC_RISCV_TELINK_B91_SOC_CONTEXT_H #define SOC_RISCV_TELINK_B91_SOC_CONTEXT_H +#include + #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* Telink B91 specific registers. */ -#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp) - #define SOC_ESF_MEMBERS \ - uint32_t mxstatus; \ - uint32_t ucode \ - - #define SOC_ESF_INIT \ - 0xdeadbaad, \ - 0xdeadbaad - - #define SOC_ESF_THREAD_INIT(soc_context) \ - (soc_context)->mxstatus = 0; \ - (soc_context)->ucode = 0 - -#elif defined(CONFIG_TELINK_B91_PFT_ARCH) - #define SOC_ESF_MEMBERS \ - uint32_t mxstatus - - #define SOC_ESF_INIT \ - 0xdeadbaad - - #define SOC_ESF_THREAD_INIT(soc_context) \ - (soc_context)->mxstatus = 0 - -#elif defined(__riscv_dsp) - - #define SOC_ESF_MEMBERS \ - uint32_t ucode - - #define SOC_ESF_INIT \ - 0xdeadbaad +#define SOC_ESF_MEMBERS \ + CUSTOM_CSR_ESF_MEMBERS - #define SOC_ESF_THREAD_INIT(soc_context) \ - (soc_context)->ucode = 0 -#endif +#define SOC_ESF_INIT \ + CUSTOM_CSR_ESF_INIT #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/soc/telink/tlsr/tlsr951x/soc_irq.S b/soc/telink/tlsr/tlsr951x/soc_irq.S index 76b3ac5a45dc6..4ddc1eadb3340 100644 --- a/soc/telink/tlsr/tlsr951x/soc_irq.S +++ b/soc/telink/tlsr/tlsr951x/soc_irq.S @@ -6,51 +6,24 @@ #include #include +#include -#include - -#define NDS_MXSTATUS 0x7C4 +#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* Exports */ -#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE GTEXT(__soc_save_context) GTEXT(__soc_restore_context) -#endif - -#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE SECTION_FUNC(exception.other, __soc_save_context) -#ifdef CONFIG_TELINK_B91_PFT_ARCH - csrr t0, NDS_MXSTATUS -#endif -#ifdef __riscv_dsp - csrr t1, ucode -#endif - -#ifdef CONFIG_TELINK_B91_PFT_ARCH - sw t0, __soc_esf_t_mxstatus_OFFSET(a0) -#endif -#ifdef __riscv_dsp - sw t1, __soc_esf_t_ucode_OFFSET(a0) -#endif + __custom_csr_save_context a0, t0 + ret SECTION_FUNC(exception.other, __soc_restore_context) -#ifdef CONFIG_TELINK_B91_PFT_ARCH - lw t0, __soc_esf_t_mxstatus_OFFSET(a0) -#endif -#ifdef __riscv_dsp - lw t1, __soc_esf_t_ucode_OFFSET(a0) -#endif - -#ifdef CONFIG_TELINK_B91_PFT_ARCH - csrw NDS_MXSTATUS, t0 -#endif -#ifdef __riscv_dsp - csrw ucode, t1 -#endif + __custom_csr_restore_context a0, t0 + ret #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ diff --git a/soc/telink/tlsr/tlsr951x/soc_offsets.h b/soc/telink/tlsr/tlsr951x/soc_offsets.h index 8b48bceedfffa..ff6b2e370aae1 100644 --- a/soc/telink/tlsr/tlsr951x/soc_offsets.h +++ b/soc/telink/tlsr/tlsr951x/soc_offsets.h @@ -7,23 +7,13 @@ #ifndef SOC_RISCV_TELINK_B91_SOC_OFFSETS_H #define SOC_RISCV_TELINK_B91_SOC_OFFSETS_H +#include + #ifdef CONFIG_RISCV_SOC_OFFSETS /* Telink B91 specific registers. */ -#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, mxstatus); \ - GEN_OFFSET_SYM(soc_esf_t, ucode) - -#elif defined(CONFIG_TELINK_B91_PFT_ARCH) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, mxstatus) - -#elif defined(__riscv_dsp) - #define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, ucode) - -#endif +#define GEN_SOC_OFFSET_SYMS() \ + GEN_CUSTOM_CSR_OFFSET_SYMS() #endif /* CONFIG_RISCV_SOC_OFFSETS */ diff --git a/soc/telink/tlsr/tlsr951x/start.S b/soc/telink/tlsr/tlsr951x/start.S index 6e09dabd4a957..7074860f6e97a 100644 --- a/soc/telink/tlsr/tlsr951x/start.S +++ b/soc/telink/tlsr/tlsr951x/start.S @@ -4,9 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define NDS_MCACHE_CTL 0x7CA -#define NDS_MMISC_CTL 0x7D0 - #include .option push @@ -31,17 +28,6 @@ entry: start: - /* Enable I/D-Cache */ - csrr t0, NDS_MCACHE_CTL - ori t0, t0, 1 #/I-Cache - ori t0, t0, 2 #/D-Cache - csrw NDS_MCACHE_CTL, t0 - fence.i - - /* Enable misaligned access and non-blocking load */ - li t0, (1 << 8) | (1 << 6) - csrs NDS_MMISC_CTL, t0 - _ZERO_AES: lui t0, 0 la t2, _AES_DATA_VMA_START