diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
index d565712f0a32d..db9e8e3cfed6a 100644
--- a/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
@@ -68,6 +68,7 @@ endif()
 if(NOT CONFIG_CPU_CORTEX_A)
   set(CONFIG_MCUX_COMPONENT_driver.reset ON)
   set(CONFIG_MCUX_COMPONENT_driver.memory ON)
+  set(CONFIG_MCUX_COMPONENT_driver.sentinel ON)
 endif()
 
 # Include fsl_dsp.c for ARM domains (applicable to i.MX RTxxx devices)
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
index a947124cc3fb9..42f6f129714ad 100644
--- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
@@ -132,6 +132,7 @@ set_variable_ifdef(CONFIG_DAI_NXP_ESAI          CONFIG_MCUX_COMPONENT_driver.esa
 set_variable_ifdef(CONFIG_MCUX_LPCMP            CONFIG_MCUX_COMPONENT_driver.lpcmp)
 set_variable_ifdef(CONFIG_NXP_RF_IMU            CONFIG_MCUX_COMPONENT_driver.imu)
 set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC        CONFIG_MCUX_COMPONENT_driver.trdc)
+set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC_1      CONFIG_MCUX_COMPONENT_driver.trdc_1)
 set_variable_ifdef(CONFIG_S3MU_MCUX_S3MU        CONFIG_MCUX_COMPONENT_driver.s3mu)
 set_variable_ifdef(CONFIG_DAI_NXP_MICFIL        CONFIG_MCUX_COMPONENT_driver.pdm)
 set_variable_ifdef(CONFIG_PINCTRL_NXP_PORT      CONFIG_MCUX_COMPONENT_driver.port)
diff --git a/soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.m33 b/soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.m33
index c4d70534a28e1..f2070a64f7644 100644
--- a/soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.m33
+++ b/soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.m33
@@ -17,4 +17,7 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 200000000
 
+config TRDC_MCUX_TRDC_1
+	default y
+	bool "Use TRDC_1 MCUX Driver"
 endif
diff --git a/soc/nxp/imx/imx9/imx93/m33/soc.c b/soc/nxp/imx/imx9/imx93/m33/soc.c
index ef61a7cb7fbb9..c4cb1b8dfabd7 100644
--- a/soc/nxp/imx/imx9/imx93/m33/soc.c
+++ b/soc/nxp/imx/imx9/imx93/m33/soc.c
@@ -8,8 +8,53 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
+#ifdef CONFIG_USERSPACE
+#include <fsl_trdc.h>
+#include <fsl_sentinel.h>
+#endif
 
 #ifdef CONFIG_SOC_EARLY_INIT_HOOK
+#ifdef CONFIG_USERSPACE
+void soc_init_trdc(void)
+{
+	uint32_t i, j;
+
+	/* Release TRDC(transfer owner of TRDC from s400 to m33) */
+	SENTINEL_ReleaseRDC(TRDC_TYPE);
+
+	/* Enable all access modes for MBC and MRC in all running mode */
+	trdc_hardware_config_t hwConfig;
+	trdc_memory_access_control_config_t memAccessConfig;
+
+	(void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
+	memAccessConfig.nonsecureUsrX  = 1U;
+	memAccessConfig.nonsecureUsrW  = 1U;
+	memAccessConfig.nonsecureUsrR  = 1U;
+	memAccessConfig.nonsecurePrivX = 1U;
+	memAccessConfig.nonsecurePrivW = 1U;
+	memAccessConfig.nonsecurePrivR = 1U;
+	memAccessConfig.secureUsrX     = 1U;
+	memAccessConfig.secureUsrW     = 1U;
+	memAccessConfig.secureUsrR     = 1U;
+	memAccessConfig.securePrivX    = 1U;
+	memAccessConfig.securePrivW    = 1U;
+	memAccessConfig.securePrivR    = 1U;
+
+	TRDC_GetHardwareConfig(TRDC1, &hwConfig);
+	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+		}
+	}
+
+	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+		}
+	}
+}
+#endif
+
 void soc_early_init_hook(void)
 {
 	/* Configure secure access to pin registers */
@@ -17,5 +62,12 @@ void soc_early_init_hook(void)
 	GPIO2->PCNS = 0x0;
 	GPIO3->PCNS = 0x0;
 	GPIO4->PCNS = 0x0;
+
+#ifdef CONFIG_USERSPACE
+	/* atf configure basic trdc setting about m33 core
+	 * init trdc for all running mode when enabled user space context
+	 */
+	soc_init_trdc();
+#endif
 }
 #endif