diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 6b839a8195a7c..d92265965831b 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -5732,6 +5732,15 @@ West: files: - modules/Kconfig.wurthelektronik +"West project: hal_xhsc": + status: maintained + maintainers: + - XH-YongbingLiu + files: + - modules/Kconfig.xhsc + labels: + - "platform: XHSC" + "West project: hal_xtensa": status: maintained maintainers: diff --git a/boards/xhsc/hc32f4a0_evb/Kconfig.hc32f4a0_evb b/boards/xhsc/hc32f4a0_evb/Kconfig.hc32f4a0_evb new file mode 100644 index 0000000000000..131284c468a08 --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/Kconfig.hc32f4a0_evb @@ -0,0 +1,5 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HC32F4A0_EVB + select SOC_HC32F4A0 diff --git a/boards/xhsc/hc32f4a0_evb/board.cmake b/boards/xhsc/hc32f4a0_evb/board.cmake new file mode 100644 index 0000000000000..dd1cd8ec9248b --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/board.cmake @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=HC32F4A0" "--frequency=10000000") +board_runner_args(jlink "--device=HC32F4A0" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/xhsc/hc32f4a0_evb/board.yml b/boards/xhsc/hc32f4a0_evb/board.yml new file mode 100644 index 0000000000000..05a0890ddc5e5 --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: hc32f4a0_evb + vendor: xhsc + socs: + - name: hc32f4a0 diff --git a/boards/xhsc/hc32f4a0_evb/doc/board.webp b/boards/xhsc/hc32f4a0_evb/doc/board.webp new file mode 100644 index 0000000000000..1d7dda73e7184 Binary files /dev/null and b/boards/xhsc/hc32f4a0_evb/doc/board.webp differ diff --git a/boards/xhsc/hc32f4a0_evb/doc/index.rst b/boards/xhsc/hc32f4a0_evb/doc/index.rst new file mode 100644 index 0000000000000..542f7fa6eae68 --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/doc/index.rst @@ -0,0 +1,127 @@ +.. zephyr:board:: hc32f4a0_evb + +Overview +******** + +HC32F4A0_EVB, also named as EV_F4A0_LQ176, is the official development board of +XHSC, equipped with HC32F4A0SITB chip, based on ARM Cortex-M4 core, with a +maximum frequency of 240 MHz, and rich on-board resources, which can give full +play to the performance of HC32F4A0SITB chip. + +Hardware +******** + +- MCU: HC32F4A0SITB, 240MHz, 2048KB FLASH, 512KB RAM +- External RAM: + * SRAM: 1MB , IS62WV51216 + * SDRAM: 8MB, IS42S16400J +- External FLASH: + * Nand: 256MB, MT29F2G08AB, + * SPI NOR: 64MB , W25Q64 +- Common Peripherals + - LEDs: 3, user LEDs (LED0, LED1, LED2). + - Buttons: 11, Matrix Keyboard (K1~K9), WAKEUP (K10), RESET (K11) +- Common Interfaces + * USB to serial port + * SD card interface + * Ethernet interface + * LCD interface + * USB HS, USB FS, USB 3300 + * DVP interface + * 3.5mm headphone jack, + * Line in connector + * speaker connector +- Debugging Interface + * On-board DAP debugger + * standard JTAG/SWD + +More information about the board and MCU can be found +at [XHSC](https://www.xhsc.com.cn/). + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Pin Mapping +=========== + +The peripherals of the HC32F4A0 SoC can be routed to various pins on the board. +The configuration of these routes can be modified through DTS. Please refer to +the datasheet to see the possible routings for each peripheral. + +Default Zephyr Peripheral Mapping +---------------------------------- + +- USART_1 TX/RX : PH15/PH13 (Virtual Port Com) +- LED11 : PC9 +- K10/WKUP : PA0 + +System Clock +------------ + +HC32F4A0_EVB System Clock could be driven by an internal or external oscillator, + as well as the PLL clock. By default, the System clock is driven by the PLL + clock at 240MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +HC32F4A0_EVB board has 10 USARTs. The Zephyr console output is +assigned to UART1. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +HC32F4A0_EVB board includes an XH-Link embedded debug tool interface. + +Using XH-Link +============= + +The HC32F4A0_EVB includes an onboard programmer/debugger (XH-Link) which +allow flash programming and debug over USB. + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample + application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hc32f4a0_evb + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hc32f4a0_evb + :goals: flash + :compact: + + You should see "Hello World! hc32f4a0_evb/hc32f4a0" in your terminal. + +#. To debug an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hc32f4a0_evb + :goals: debug + :compact: + +.. _HC32F4A0 Datasheet, Reference Manual, HC32F4A0_EVB Schematics: + https://www.xhsc.com.cn/product/112.html diff --git a/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb-pinctrl.dtsi b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb-pinctrl.dtsi new file mode 100644 index 0000000000000..d9193b5cd72fd --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb-pinctrl.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart1_default: usart1_default { + group0 { + pinmux = , + ; + }; + }; + + usart2_default: usart2_default { + group1 { + pinmux = , + ; + }; + }; + + usart3_default: usart3_default { + group1 { + pinmux = , + ; + }; + }; + + usart4_default: usart4_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.dts b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.dts new file mode 100644 index 0000000000000..21d907658a707 --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.dts @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "hc32f4a0_evb-pinctrl.dtsi" +#include + +/ { + model = "xhsc, EV_F4A0_LQ176_Rev1.0 board"; + compatible = "xhsc,hc32f4a0_evb"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "Wkup_key"; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led; + sw0 = &user_button; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +&clk_xtal { + status = "okay"; +}; + +&clk_xtal32 { + status = "okay"; +}; + +&clk_hrc { + status = "okay"; +}; + +&clk_mrc { + status = "okay"; +}; + +&clk_lrc { + status = "okay"; +}; + +&clk_pll { + status = "okay"; +}; + +&usart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + interrupt-parent = <&intc>; + interrupts = , + , + ; + interrupt-names = "ore", "rxne", "tc"; +}; diff --git a/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.yaml b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.yaml new file mode 100644 index 0000000000000..cbdfdfd485c78 --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb.yaml @@ -0,0 +1,16 @@ +identifier: hc32f4a0_evb +name: XHSC hc32f4a0_evb +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - clock control + - interrupt control + - serial +vendor: xhsc diff --git a/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb_defconfig b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb_defconfig new file mode 100644 index 0000000000000..90f7f212a65ae --- /dev/null +++ b/boards/xhsc/hc32f4a0_evb/hc32f4a0_evb_defconfig @@ -0,0 +1,17 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable FPU +CONFIG_FPU=y + +# GPIO Controller +CONFIG_GPIO=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/xhsc/index.rst b/boards/xhsc/index.rst new file mode 100644 index 0000000000000..d25f3ed75c2b7 --- /dev/null +++ b/boards/xhsc/index.rst @@ -0,0 +1,10 @@ +.. _boards-xhsc: + +XHSC +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 659c058ef61a0..5619aaf6f57a1 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ARM_SCMI clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK clock_control_fixed_rate.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_HC32 clock_control_hc32.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_SAM_D5X_E5X clock_control_mchp_sam_d5x_e5x.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index e2c4a071ab09a..ba7806ff53aa4 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -122,4 +122,6 @@ source "drivers/clock_control/Kconfig.sf32lb_hxt48" source "drivers/clock_control/Kconfig.sf32lb_rcc" +source "drivers/clock_control/Kconfig.hc32" + endif # CLOCK_CONTROL diff --git a/drivers/clock_control/Kconfig.hc32 b/drivers/clock_control/Kconfig.hc32 new file mode 100644 index 0000000000000..a6620b13c5afd --- /dev/null +++ b/drivers/clock_control/Kconfig.hc32 @@ -0,0 +1,7 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_HC32 + bool "HC32 Clock Control" + default y + depends on DT_HAS_XHSC_HC32_CLOCK_CONTROL_ENABLED diff --git a/drivers/clock_control/clock_control_hc32.c b/drivers/clock_control/clock_control_hc32.c new file mode 100644 index 0000000000000..4e203ae6a0f33 --- /dev/null +++ b/drivers/clock_control/clock_control_hc32.c @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "clock_control_hc32.h" + +/** + * @defgroup EV_HC32F460_LQFP100_V2_XTAL_CONFIG EV_HC32F460_LQFP100_V2 XTAL Configure definition + * @{ + */ +#define BSP_XTAL_PORT (GPIO_PORT_H) +#define BSP_XTAL_IN_PIN (GPIO_PIN_01) +#define BSP_XTAL_OUT_PIN (GPIO_PIN_00) + +/** + * @defgroup EV_HC32F460_LQFP100_V2_XTAL32_CONFIG EV_HC32F460_LQFP100_V2 XTAL32 Configure definition + * @{ + */ +#define BSP_XTAL32_PORT (GPIO_PORT_C) +#define BSP_XTAL32_IN_PIN (GPIO_PIN_15) +#define BSP_XTAL32_OUT_PIN (GPIO_PIN_14) + +static void hc32_clock_stale(uint32_t flag) +{ + uint32_t stable_time = 0; + + while (RESET == CLK_GetStableStatus(flag)) { + if (stable_time++ >= 20000) { + break; + } + } +} + +#if HC32_XTAL_ENABLED +static void hc32_clock_xtal_init(void) +{ + stc_clock_xtal_init_t stc_xtal_init; + + GPIO_AnalogCmd(BSP_XTAL_PORT, BSP_XTAL_IN_PIN | BSP_XTAL_OUT_PIN, ENABLE); + + (void)CLK_XtalStructInit(&stc_xtal_init); + stc_xtal_init.u8Mode = CLK_XTAL_MD_OSC; + stc_xtal_init.u8Drv = XTAL_DRV; + stc_xtal_init.u8State = CLK_XTAL_ON; + stc_xtal_init.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stc_xtal_init); + hc32_clock_stale(CLK_STB_FLAG_XTAL); +} +#endif /* HC32_XTAL_ENABLED */ + +#if HC32_XTAL32_ENABLED +static void hc32_clock_xtal32_init(void) +{ + stc_clock_xtal32_init_t stc_xtal32_init; + + (void)CLK_Xtal32StructInit(&stc_xtal32_init); + stc_xtal32_init.u8State = CLK_XTAL32_ON; + + if (1U == HC32_XTAL32_DRV) { + stc_xtal32_init.u8Drv = CLK_XTAL32_DRV_HIGH; + } else { + stc_xtal32_init.u8Drv = CLK_XTAL32_DRV_MID; + } + + stc_xtal32_init.u8Filter = CLK_XTAL32_FILTER_ALL_MD; + GPIO_AnalogCmd(BSP_XTAL32_PORT, BSP_XTAL32_IN_PIN | BSP_XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32Init(&stc_xtal32_init); +} +#endif /* HC32_XTAL32_ENABLED */ + +static void hc32_clock_hrc_init(void) +{ + CLK_HrcCmd(ENABLE); + hc32_clock_stale(CLK_STB_FLAG_HRC); +} + +static void hc32_clock_mrc_init(void) +{ + CLK_MrcCmd(ENABLE); +} + +static void hc32_clock_lrc_init(void) +{ + CLK_LrcCmd(ENABLE); +} + +#if HC32_PLL_ENABLED +static void hc32_clock_pll_init(void) +{ + stc_clock_pll_init_t stc_pll_init; + + (void)CLK_PLLStructInit(&stc_pll_init); + stc_pll_init.PLLCFGR = 0UL; + stc_pll_init.PLLCFGR_f.PLLM = (HC32_PLL_M_DIVISOR - 1UL); + stc_pll_init.PLLCFGR_f.PLLN = (HC32_PLL_N_MULTIPLIER - 1UL); + stc_pll_init.PLLCFGR_f.PLLP = (HC32_PLL_P_DIVISOR - 1UL); + stc_pll_init.PLLCFGR_f.PLLQ = (HC32_PLL_Q_DIVISOR - 1UL); + stc_pll_init.PLLCFGR_f.PLLR = (HC32_PLL_R_DIVISOR - 1UL); +#if HC32_PLL_SRC_XTAL + hc32_clock_xtal_init(); + stc_pll_init.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; +#elif HC32_PLL_SRC_HRC + hc32_clock_hrc_init(); + stc_pll_init.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_HRC; +#endif + stc_pll_init.u8PLLState = CLK_PLL_ON; + (void)CLK_PLLInit(&stc_pll_init); + hc32_clock_stale(CLK_STB_FLAG_PLL); +} +#endif + +static void hc32_clk_conf(void) +{ +#if HC32_PLL_ENABLED + hc32_clock_pll_init(); +#endif +#if HC32_XTAL_ENABLED + hc32_clock_xtal_init(); +#endif +#if HC32_HRC_ENABLED + hc32_clock_hrc_init(); +#endif +#if HC32_MRC_ENABLED + hc32_clock_mrc_init(); +#endif +#if HC32_LRC_ENABLED + hc32_clock_lrc_init(); +#endif +#if HC32_XTAL32_ENABLED + hc32_clock_xtal32_init(); +#endif +} + +#if defined(HC32F460) +static uint8_t hc32_system_running_mode(uint32_t frequency) +{ + uint8_t running_mode; + + if (frequency >= 168000000) { + running_mode = 2; + } else { + if (frequency >= 8000000) { + running_mode = 1; + } else { + running_mode = 0; + } + } + + return running_mode; +} + +static void hc32_run_mode_switch(uint32_t old_freq, uint32_t new_freq) +{ + uint8_t old_run_mode; + uint8_t new_run_mode; + + new_run_mode = hc32_system_running_mode(new_freq); + old_run_mode = hc32_system_running_mode(old_freq); + + if (old_run_mode == 0) { + if (new_run_mode == 1) { + PWC_LowSpeedToHighSpeed(); + } else if (new_run_mode == 2) { + PWC_LowSpeedToHighPerformance(); + } else { + /* Nothing to do */ + } + } else if (old_run_mode == 1) { + if (new_run_mode == 0) { + PWC_HighSpeedToLowSpeed(); + } else if (new_run_mode == 2) { + PWC_HighSpeedToHighPerformance(); + } else { + /* Nothing to do */ + } + } else if (old_run_mode == 2) { + if (new_run_mode == 0) { + PWC_HighPerformanceToLowSpeed(); + } else if (new_run_mode == 1) { + PWC_HighPerformanceToHighSpeed(); + } else { + /* Nothing to do */ + } + } else { + /* Nothing to do */ + } +} +#elif defined(HC32F4A0) +static void hc32_run_mode_switch(uint32_t old_freq, uint32_t new_freq) +{ + uint8_t old_run_mode; + uint8_t new_run_mode; + + new_run_mode = (new_freq >= 8000000) ? 1 : 0; + old_run_mode = (old_freq >= 8000000) ? 1 : 0; + + if (new_run_mode > old_run_mode) { + PWC_LowSpeedToHighSpeed(); + } else if (new_run_mode < old_run_mode) { + PWC_HighSpeedToLowSpeed(); + } else { + ; + } +} +#endif + +static int hc32_clock_control_init(const struct device *dev) +{ + uint32_t old_core_freq; + uint32_t new_core_freq; + stc_clock_freq_t stc_clock_freq; + + ARG_UNUSED(dev); + CLK_GetClockFreq(&stc_clock_freq); + old_core_freq = stc_clock_freq.u32SysclkFreq; + /* Set bus clk div. */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (HC32_HCLK_DIV(HC32_HCLK_PRESCALER) | HC32_EXCLK_DIV(HC32_EXCLK_PRESCALER) | + HC32_PCLK(0, HC32_PCLK0_PRESCALER) | HC32_PCLK(1, HC32_PCLK1_PRESCALER) | + HC32_PCLK(2, HC32_PCLK2_PRESCALER) | HC32_PCLK(3, HC32_PCLK3_PRESCALER) | + HC32_PCLK(4, HC32_PCLK4_PRESCALER))); + + /* sram init include read/write wait cycle setting */ + SRAM_SetWaitCycle(SRAM_SRAM_ALL, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + + /* flash read wait cycle setting */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE); + /* 3 cycles for 126MHz ~ 200MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT); + + hc32_clk_conf(); + +#if HC32_SYSCLK_SRC_PLL + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); +#elif HC32_SYSCLK_SRC_XTAL + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); +#elif HC32_SYSCLK_SRC_HRC + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_HRC); +#elif HC32_SYSCLK_SRC_MRC + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_MRC); +#endif + + CLK_GetClockFreq(&stc_clock_freq); + new_core_freq = stc_clock_freq.u32SysclkFreq; + hc32_run_mode_switch(old_core_freq, new_core_freq); + + return 0; +} + +static int hc32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) +{ + struct hc32_modules_clock_sys *clk_sys = (struct hc32_modules_clock_sys *)sub_system; + const struct hc32_modules_clock_config *mod_conf = + (const struct hc32_modules_clock_config *)dev->config; + + if (IN_RANGE(clk_sys->fcg, HC32_CLK_FCG0, HC32_CLK_FCG3) == 0) { + return -ENOTSUP; + } + + sys_clear_bits(mod_conf->addr + HC32_CLK_MODULES_OFFSET(clk_sys->fcg), + HC32_CLK_MODULES_BIT(clk_sys->bits)); + + return 0; +} + +static int hc32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system) +{ + struct hc32_modules_clock_sys *clk_sys = (struct hc32_modules_clock_sys *)sub_system; + const struct hc32_modules_clock_config *mod_conf = + (const struct hc32_modules_clock_config *)dev->config; + + if (IN_RANGE(clk_sys->fcg, HC32_CLK_FCG0, HC32_CLK_FCG3) == 0) { + return -ENOTSUP; + } + + sys_set_bits(mod_conf->addr + HC32_CLK_MODULES_OFFSET(clk_sys->fcg), + HC32_CLK_MODULES_BIT(clk_sys->bits)); + + return 0; +} + +static int hc32_clock_control_get_subsys_rate(const struct device *dev, + clock_control_subsys_t sub_system, uint32_t *rate) +{ + struct hc32_modules_clock_sys *clk_sys = (struct hc32_modules_clock_sys *)sub_system; + + ARG_UNUSED(dev); + switch (clk_sys->bus) { +#if HC32_HRC_ENABLED + case HC32_CLK_SRC_HRC: + *rate = HC32_HRC_FREQ; + break; +#endif +#if HC32_MRC_ENABLED + case HC32_CLK_SRC_MRC: + *rate = HC32_MRC_FREQ; + break; +#endif +#if HC32_XTAL_ENABLED + case HC32_CLK_SRC_XTAL: + *rate = HC32_XTAL_FREQ; + break; +#endif +#if HC32_PLL_ENABLED + case HC32_CLK_SRC_PLL: + *rate = HC32_PLL_FREQ; + break; +#endif + case HC32_CLK_BUS_HCLK: + *rate = CORE_CLK_FREQ; + break; + case HC32_CLK_BUS_PCLK0: + *rate = PCLK0_FREQ; + break; + case HC32_CLK_BUS_PCLK1: + *rate = PCLK1_FREQ; + break; + case HC32_CLK_BUS_PCLK2: + *rate = PCLK2_FREQ; + break; + case HC32_CLK_BUS_PCLK3: + *rate = PCLK3_FREQ; + break; + case HC32_CLK_BUS_PCLK4: + *rate = PCLK4_FREQ; + break; + case HC32_SYS_CLK: + *rate = SYS_CLK_FREQ; + break; + default: + return -ENOTSUP; + } + + return 0; +} + +static enum clock_control_status hc32_clock_control_get_status(const struct device *dev, + clock_control_subsys_t sys) +{ + struct hc32_modules_clock_sys *clk_sys = (struct hc32_modules_clock_sys *)sys; + const struct hc32_modules_clock_config *mod_conf = + (const struct hc32_modules_clock_config *)dev->config; + + if (IN_RANGE(clk_sys->fcg, HC32_CLK_FCG0, HC32_CLK_FCG3) == 0) { + return -CLOCK_CONTROL_STATUS_UNKNOWN; + } + + if (sys_test_bit(mod_conf->addr + HC32_CLK_MODULES_OFFSET(clk_sys->fcg), clk_sys->bits)) { + return CLOCK_CONTROL_STATUS_OFF; + } + + return CLOCK_CONTROL_STATUS_ON; +} + +static int hc32_clock_control_configure(const struct device *dev, clock_control_subsys_t sys, + void *data) +{ + uint32_t clk_sys = *(uint32_t *)sys; + uint32_t dat = *(uint32_t *)data; + + ARG_UNUSED(dev); + if (IN_RANGE(clk_sys, HC32_CLK_CONF_MIN, HC32_CLK_CONF_MAX) == 0) { + return -ENOTSUP; + } + switch (clk_sys) { + case HC32_CLK_CONF_PERI: + CLK_SetPeriClockSrc((uint16_t)dat); + break; + case HC32_CLK_CONF_USB: + CLK_SetUSBClockSrc((uint16_t)dat); + break; + case HC32_CLK_CONF_I2S: + CLK_SetI2SClockSrc((uint8_t)(dat >> 8), (uint8_t)dat); + break; + case HC32_CLK_CONF_TPIU: + CLK_SetTpiuClockDiv((uint8_t)dat & 0x03); + if ((uint8_t)dat & 0x80) { + CLK_TpiuClockCmd(ENABLE); + } else { + CLK_TpiuClockCmd(DISABLE); + } + break; + case HC32_CLK_CONF_SRC: + CLK_SetSysClockSrc((uint8_t)dat); + break; + case HC32_CLK_CONF_MCO: + CLK_MCOConfig(CLK_MCO1, (uint8_t)dat, CLK_MCO_DIV8); + CLK_MCOCmd(CLK_MCO1, ENABLE); + break; + default: + return -ENOTSUP; + } + return 0; +} + +static struct clock_control_driver_api hc32_clock_control_api = { + .on = hc32_clock_control_on, + .off = hc32_clock_control_off, + .get_rate = hc32_clock_control_get_subsys_rate, + .get_status = hc32_clock_control_get_status, + .configure = hc32_clock_control_configure, +}; + +static const struct hc32_modules_clock_config hc32_modules_clk = { + .addr = DT_REG_ADDR(DT_NODELABEL(bus_fcg)), +}; + +DEVICE_DT_DEFINE(DT_NODELABEL(clk_sys), &hc32_clock_control_init, NULL, NULL, &hc32_modules_clk, + PRE_KERNEL_1, 1, &hc32_clock_control_api); diff --git a/drivers/clock_control/clock_control_hc32.h b/drivers/clock_control/clock_control_hc32.h new file mode 100644 index 0000000000000..fafe2bbb52e5f --- /dev/null +++ b/drivers/clock_control/clock_control_hc32.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _HC32F4_CLOCK_ +#define _HC32F4_CLOCK_ + +#include +#include + +#if defined(HC32F460) +#define EFM_WAIT_CYCLE5_FREQ 168000000 +#define EFM_WAIT_CYCLE4_FREQ 132000000 +#define EFM_WAIT_CYCLE3_FREQ 99000000 +#define EFM_WAIT_CYCLE2_FREQ 66000000 +#define EFM_WAIT_CYCLE1_FREQ 33000000 +#elif defined(HC32F4A0) +#define EFM_WAIT_CYCLE5_FREQ 200000000 +#define EFM_WAIT_CYCLE4_FREQ 160000000 +#define EFM_WAIT_CYCLE3_FREQ 120000000 +#define EFM_WAIT_CYCLE2_FREQ 80000000 +#define EFM_WAIT_CYCLE1_FREQ 40000000 +#endif + +#if (CORE_CLK_FREQ > EFM_WAIT_CYCLE5_FREQ) +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE5 +#elif (CORE_CLK_FREQ > EFM_WAIT_CYCLE4_FREQ) +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE4 +#elif (CORE_CLK_FREQ > EFM_WAIT_CYCLE3_FREQ) +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE3 +#elif (CORE_CLK_FREQ > EFM_WAIT_CYCLE2_FREQ) +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE2 +#elif (CORE_CLK_FREQ > EFM_WAIT_CYCLE1_FREQ) +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE1 +#else +#define EFM_WAIT_CYCLE EFM_WAIT_CYCLE0 +#endif + +#if defined(HC32F460) +#if (CORE_CLK_FREQ > 126000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT3 +#elif (CORE_CLK_FREQ > 84000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT2 +#elif (CORE_CLK_FREQ > 42000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT1 +#else /* CORE_CLK_FREQ */ +#define GPIO_RD_WAIT GPIO_RD_WAIT0 +#endif /* CORE_CLK_FREQ */ +#elif defined(HC32F4A0) +#if (CORE_CLK_FREQ > 250000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT5 +#elif (CORE_CLK_FREQ > 200000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT4 +#elif (CORE_CLK_FREQ > 150000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT3 +#elif (CORE_CLK_FREQ > 100000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT2 +#elif (CORE_CLK_FREQ > 50000000) +#define GPIO_RD_WAIT GPIO_RD_WAIT1 +#else /* CORE_CLK_FREQ */ +#define GPIO_RD_WAIT GPIO_RD_WAIT0 +#endif /* CORE_CLK_FREQ */ +#endif /* HC32F460 & HC32F4A0*/ + +#if HC32_XTAL_ENABLED +#if ((HC32_XTAL_FREQ > 20000000) && (HC32_XTAL_FREQ <= 25000000)) +#define XTAL_DRV CLK_XTAL_DRV_HIGH +#elif (HC32_XTAL_FREQ > 16000000) +#define XTAL_DRV CLK_XTAL_DRV_MID +#elif (HC32_XTAL_FREQ > 8000000) +#define XTAL_DRV CLK_XTAL_DRV_LOW +#elif (HC32_XTAL_FREQ > 4000000) +#define XTAL_DRV CLK_XTAL_DRV_ULOW +#else +#error "xtal clock frequency not compatible" +#endif +#endif + +#define HC32_CLOCK_CONTROL_NAME "hc32-cc" + +struct hc32_modules_clock_config { + uint32_t addr; +}; +#endif /* !_HC32F4_CLOCK_ */ diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 6fb97fc1d0bb8..b6e484b6a31ba 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -36,6 +36,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_FXL6408 gpio_fxl6408.c) zephyr_library_sources_ifdef(CONFIG_GPIO_GD32 gpio_gd32.c) zephyr_library_sources_ifdef(CONFIG_GPIO_GECKO gpio_gecko.c) zephyr_library_sources_ifdef(CONFIG_GPIO_GRGPIO2 gpio_grgpio2.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_HC32 gpio_hc32.c) zephyr_library_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_INFINEON_CAT1 gpio_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_INTEL gpio_intel.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 6c4376c7feeae..e46cb6de694c3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -126,6 +126,7 @@ source "drivers/gpio/Kconfig.fxl6408" source "drivers/gpio/Kconfig.gd32" source "drivers/gpio/Kconfig.gecko" source "drivers/gpio/Kconfig.grgpio" +source "drivers/gpio/Kconfig.hc32" source "drivers/gpio/Kconfig.ifx_cat1" source "drivers/gpio/Kconfig.imx" source "drivers/gpio/Kconfig.intel" diff --git a/drivers/gpio/Kconfig.hc32 b/drivers/gpio/Kconfig.hc32 new file mode 100644 index 0000000000000..b45ef2a3fcf53 --- /dev/null +++ b/drivers/gpio/Kconfig.hc32 @@ -0,0 +1,10 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_HC32 + bool "GPIO Driver for HC32 MCUs" + default y + depends on DT_HAS_XHSC_HC32_GPIO_ENABLED + select HC32_LL_GPIO + help + Enable GPIO driver for HC32 line of MCUs diff --git a/drivers/gpio/gpio_hc32.c b/drivers/gpio/gpio_hc32.c new file mode 100644 index 0000000000000..4eb352f4a5b63 --- /dev/null +++ b/drivers/gpio/gpio_hc32.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT xhsc_hc32_gpio + +#include + +#include +#include +#include +#include "gpio_hc32.h" +#include +#include + +/** + * @brief Common GPIO driver for HC32 MCUs. + */ + +/** + * @brief EXTI interrupt callback + */ +static void gpio_hc32_isr(int line, void *arg) +{ + struct gpio_hc32_data *data = arg; + + EXTINT_ClearExtIntStatus(BIT(line)); + gpio_fire_callbacks(&data->cb, data->dev, BIT(line)); +} + +/** + * @brief Calculate the on/off status of the exit interrupt by the given flags + * + */ +static int gpio_hc32_cfg2ll_intr_on(gpio_flags_t flags) +{ + int ext_int = PIN_EXTINT_OFF; + + if ((flags & GPIO_INT_MASK) != 0) { + if ((flags & GPIO_INT_ENABLE) != 0) { + ext_int = PIN_EXTINT_ON; + } + } + + return ext_int; +} + +/** + * @brief Calculate interrupt trigger type by the given flags + * + */ +static int gpio_hc32_cfg2ll_intr_trig(gpio_flags_t flags) +{ + int trigger = HC32_EXTINT_TRIG_NOT_SUPPT; + + if ((flags & GPIO_INT_EDGE_BOTH) == GPIO_INT_EDGE_BOTH) { + trigger = HC32_EXTINT_TRIG_BOTH; + } else if ((flags & GPIO_INT_EDGE_RISING) == GPIO_INT_EDGE_RISING) { + trigger = HC32_EXTINT_TRIG_RISING; + } else if ((flags & GPIO_INT_EDGE_FALLING) == GPIO_INT_EDGE_FALLING) { + trigger = HC32_EXTINT_TRIG_FALLING; + } else if ((flags & GPIO_INT_LEVEL_LOW) == GPIO_INT_LEVEL_LOW) { + trigger = HC32_EXTINT_TRIG_LOW_LVL; + } else { + /* Nothing to do */ + } + + return trigger; +} + +/** + * @brief Calculate gpio output type + * + */ +static int gpio_hc32_cfg2ll_output_type(gpio_flags_t flags, uint16_t *out_type) +{ + if ((flags & GPIO_SINGLE_ENDED) != 0) { + if (flags & GPIO_LINE_OPEN_DRAIN) { + *out_type = PIN_OUT_TYPE_NMOS; + } else { + /* Output can't be open source */ + return -ENOTSUP; + } + } else { + *out_type = PIN_OUT_TYPE_CMOS; + } + + return 0; +} + +/** + * @brief Calculate gpio output status + * + */ +static int gpio_hc32_cfg2ll_output_status(gpio_flags_t flags, uint16_t *out_status) +{ + int ret = 0; + + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { + *out_status = PIN_STAT_SET; + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { + *out_status = PIN_STAT_RST; + } else { + if ((flags & GPIO_OUTPUT_INIT_LOGICAL) != 0U) { + /* Don't support logical set */ + ret = -ENOTSUP; + } + } + + return ret; +} + +/** + * @brief Configure pin or port + */ +static int gpio_hc32_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + int intr_trigger; + const struct gpio_hc32_config *cfg = dev->config; + const struct gpio_hc32_data *data = (struct gpio_hc32_data *)dev->data; + const struct device *intc_dev = data->intc_dev; + const struct hc32_extint_driver_api *extint_api = intc_dev->api; + uint8_t hc32_port = cfg->port; + stc_gpio_init_t stc_gpio_init; + + GPIO_StructInit(&stc_gpio_init); + + /* GPIO input/output configuration flags */ + if ((flags & GPIO_OUTPUT) != 0U) { + /* output */ + stc_gpio_init.u16PinDir = PIN_DIR_OUT; + + if (0 != gpio_hc32_cfg2ll_output_type(flags, &stc_gpio_init.u16PinOutputType)) { + return -ENOTSUP; + } + + if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) { + /* No pull up or down in out mode*/ + return -ENOTSUP; + } + + if (0 != gpio_hc32_cfg2ll_output_status(flags, &stc_gpio_init.u16PinState)) { + /* Don't support logical set */ + return -ENOTSUP; + } + } else if ((flags & GPIO_INPUT) != 0) { + /* Input */ + stc_gpio_init.u16PinDir = PIN_DIR_IN; + + if ((flags & GPIO_PULL_UP) != 0) { + stc_gpio_init.u16PullUp = PIN_PU_ON; + } else { + if ((flags & GPIO_PULL_DOWN) != 0) { + /* No pull down */ + return -ENOTSUP; + } + } + } else { + /* Deactivated: Analog */ + stc_gpio_init.u16PinAttr = PIN_ATTR_ANALOG; + } + + /* GPIO interrupt configuration flags */ + stc_gpio_init.u16ExtInt = gpio_hc32_cfg2ll_intr_on(flags); + if (PIN_EXTINT_ON == stc_gpio_init.u16ExtInt) { + intr_trigger = gpio_hc32_cfg2ll_intr_trig(flags); + if (HC32_EXTINT_TRIG_NOT_SUPPT == intr_trigger) { + stc_gpio_init.u16ExtInt = PIN_EXTINT_OFF; + return -ENOTSUP; + } + extint_api->extint_set_trigger(intc_dev, pin, intr_trigger); + } + + return GPIO_Init(hc32_port, BIT(pin), &stc_gpio_init); +} + +#if defined(CONFIG_GPIO_GET_CONFIG) +static int gpio_hc32_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint16_t PCR_value = *(cfg->base + pin * 4); + gpio_flags_t hc32_flag = 0; + + /* only support input/output cfg */ + if ((PCR_value & GPIO_PCR_DDIS) == 0U) { + if (((PCR_value)&GPIO_PCR_POUTE) != 0U) { + hc32_flag |= GPIO_OUTPUT; + if ((PCR_value & GPIO_PCR_POUT) != 0U) { + hc32_flag |= GPIO_OUTPUT_INIT_HIGH; + } else { + hc32_flag |= GPIO_OUTPUT_INIT_LOW; + } + } else { + hc32_flag |= GPIO_INPUT; + if (((PCR_value)&GPIO_PCR_PUU) != 0U) { + hc32_flag |= GPIO_PULL_UP; + } + } + } else { + hc32_flag &= ~(GPIO_OUTPUT | GPIO_INPUT); + } + + if ((PCR_value & GPIO_PCR_NOD) != 0U) { + hc32_flag |= GPIO_OPEN_DRAIN; + } + + *flags = hc32_flag; + return 0; +} +#endif + +static int gpio_hc32_port_get_raw(const struct device *dev, uint32_t *value) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint8_t port = cfg->port; + + *value = (uint32_t)GPIO_ReadInputPort(port); + + return 0; +} + +static int gpio_hc32_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint8_t port = cfg->port; + + GPIO_WritePort(port, mask); + + return 0; +} + +static int gpio_hc32_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint8_t port = cfg->port; + + GPIO_SetPins(port, pins); + + return 0; +} + +static int gpio_hc32_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint8_t port = cfg->port; + + GPIO_ResetPins(port, pins); + + return 0; +} + +static int gpio_hc32_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_hc32_config *cfg = dev->config; + uint8_t port = cfg->port; + + GPIO_TogglePins(port, pins); + + return 0; +} + +static int gpio_hc32_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + const struct gpio_hc32_config *cfg = dev->config; + struct gpio_hc32_data *data = (struct gpio_hc32_data *)dev->data; + const struct device *intc_dev = data->intc_dev; + const struct hc32_extint_driver_api *extint_api = intc_dev->api; + uint8_t port = cfg->port; + int trigger = 0; + int err = 0; + +#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT + if (mode == GPIO_INT_MODE_DISABLE_ONLY) { + extint_api->extint_disable(port, pin); + return 0; + } else if (mode == GPIO_INT_MODE_ENABLE_ONLY) { + extint_api->extint_enable(port, pin); + return 0; + } +#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */ + + switch (mode) { + case GPIO_INT_DISABLE: + extint_api->extint_disable(intc_dev, port, pin); + extint_api->extint_unset_cb(intc_dev, pin); + extint_api->extint_set_trigger(intc_dev, pin, HC32_EXTINT_TRIG_FALLING); + return 0; + + case GPIO_INT_MODE_LEVEL: + if (trig == GPIO_INT_TRIG_LOW) { + trigger = HC32_EXTINT_TRIG_LOW_LVL; + } else { + return -ENOTSUP; + } + break; + + case GPIO_INT_MODE_EDGE: + switch (trig) { + case GPIO_INT_TRIG_BOTH: + trigger = HC32_EXTINT_TRIG_BOTH; + break; + case GPIO_INT_TRIG_HIGH: + trigger = HC32_EXTINT_TRIG_RISING; + break; + case GPIO_INT_TRIG_LOW: + /* Default trigger is falling edge */ + default: + trigger = HC32_EXTINT_TRIG_FALLING; + break; + } + break; + + default: + break; + } + + extint_api->extint_set_trigger(intc_dev, pin, trigger); + err = extint_api->extint_set_cb(intc_dev, pin, gpio_hc32_isr, (void *)data); + extint_api->extint_enable(intc_dev, port, pin); + + return err; +} + +static int gpio_hc32_manage_callback(const struct device *dev, struct gpio_callback *callback, + bool set) +{ + struct gpio_hc32_data *data = dev->data; + + return gpio_manage_callback(&data->cb, callback, set); +} + +static uint32_t gpio_hc32_get_pending_int(const struct device *dev) +{ + return 0; +} + +static const struct gpio_driver_api gpio_hc32_driver = { + .pin_configure = gpio_hc32_configure, +#if defined(CONFIG_GPIO_GET_CONFIG) + .pin_get_config = gpio_hc32_get_config, +#endif /* CONFIG_GPIO_GET_CONFIG */ + .port_get_raw = gpio_hc32_port_get_raw, + .port_set_masked_raw = gpio_hc32_port_set_masked_raw, + .port_set_bits_raw = gpio_hc32_port_set_bits_raw, + .port_clear_bits_raw = gpio_hc32_port_clear_bits_raw, + .port_toggle_bits = gpio_hc32_port_toggle_bits, + .pin_interrupt_configure = gpio_hc32_pin_interrupt_configure, + .manage_callback = gpio_hc32_manage_callback, + .get_pending_int = gpio_hc32_get_pending_int, +}; + +static int gpio_hc32_init(const struct device *dev) +{ + struct gpio_hc32_data *data = dev->data; + + data->dev = dev; + return 0; +} + +#define GPIO_HC32_DEFINE(n) \ + static const struct gpio_hc32_config gpio_hc32_cfg_##n = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ + }, \ + .base = (uint16_t *)DT_INST_REG_ADDR(n), \ + .port = n, \ + }; \ + static struct gpio_hc32_data gpio_hc32_data_##n = { \ + .intc_dev = DEVICE_DT_GET(DT_INST(0, xhsc_hc32_extint)), \ + }; \ + DEVICE_DT_INST_DEFINE(n, gpio_hc32_init, NULL, &gpio_hc32_data_##n, &gpio_hc32_cfg_##n, \ + POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_hc32_driver); + +DT_INST_FOREACH_STATUS_OKAY(GPIO_HC32_DEFINE) diff --git a/drivers/gpio/gpio_hc32.h b/drivers/gpio/gpio_hc32.h new file mode 100644 index 0000000000000..f452f41a64e9a --- /dev/null +++ b/drivers/gpio/gpio_hc32.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_HC32_H_ +#define ZEPHYR_DRIVERS_GPIO_GPIO_HC32_H_ + +/** + * @file header for HC32 GPIO + */ + +#include +#include +/** + * @brief configuration of GPIO device + */ +struct gpio_hc32_config { + struct gpio_driver_config common; + /* port PCRxy register base address */ + uint16_t *base; + /* IO port */ + uint8_t port; +}; + +/** + * @brief driver data + */ +struct gpio_hc32_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + /* Device's owner of this data */ + const struct device *dev; + /* External interrupt device */ + const struct device *intc_dev; + /* User ISR cb */ + sys_slist_t cb; +}; + +#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_HC32_H_ */ diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt index 44a0b7573a81e..d102752a8963b 100644 --- a/drivers/interrupt_controller/CMakeLists.txt +++ b/drivers/interrupt_controller/CMakeLists.txt @@ -16,6 +16,8 @@ zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c) zephyr_library_sources_ifdef(CONFIG_GPIO_INTC_STM32WB0 intc_gpio_stm32wb0.c) zephyr_library_sources_ifdef(CONFIG_HAZARD3_INTC intc_hazard3.c) zephyr_library_sources_ifdef(CONFIG_HAZARD3_INTC intc_hazard3.S) +zephyr_library_sources_ifdef(CONFIG_INTC_HC32 intc_hc32.c) +zephyr_library_sources_ifdef(CONFIG_INTC_EXTINT_HC32 intc_extint_hc32.c) zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c) zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c) zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_INTC intc_ite_it51xxx.c) diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig index d3954cc1f3c84..72a030a8da954 100644 --- a/drivers/interrupt_controller/Kconfig +++ b/drivers/interrupt_controller/Kconfig @@ -125,4 +125,6 @@ source "drivers/interrupt_controller/Kconfig.wch_pfic" source "drivers/interrupt_controller/Kconfig.wch_exti" +source "drivers/interrupt_controller/Kconfig.hc32" + endmenu diff --git a/drivers/interrupt_controller/Kconfig.hc32 b/drivers/interrupt_controller/Kconfig.hc32 new file mode 100644 index 0000000000000..d999b98d1cc9b --- /dev/null +++ b/drivers/interrupt_controller/Kconfig.hc32 @@ -0,0 +1,29 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config INTC_HC32 + bool "Interrupt/Event Controller (INTC) Driver for HC32 family of MCUs" + default y + depends on DT_HAS_XHSC_HC32_INTC_ENABLED + select HC32_LL_INTERRUPTS + select HC32_LL_INTERRUPTS_SHARE + help + Enable INTC driver for HC32 line of MCUs + +config INTC_EXTINT_HC32 + bool "External Interrupt Controller (EXTINT) Driver for HC32 family of MCUs" + default y + depends on DT_HAS_XHSC_HC32_EXTINT_ENABLED + select HC32_LL_INTERRUPTS + help + Enable EXTINT driver for HC32 line of MCUs + +if INTC_EXTINT_HC32 + +config INTC_EXTINT_USE_SHARE_INTERRUPT + bool "INTC EXTINT used share interrupt" + default y + help + INTC EXTINT respond to irq handlers with share interrupt. + +endif # INTC_EXTINT_HC32 diff --git a/drivers/interrupt_controller/intc_extint_hc32.c b/drivers/interrupt_controller/intc_extint_hc32.c new file mode 100644 index 0000000000000..a05c9394c345d --- /dev/null +++ b/drivers/interrupt_controller/intc_extint_hc32.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Driver for External Interrupt controller in HC32 MCUs + */ + +#define DT_DRV_COMPAT xhsc_hc32_extint +#define EXTINT_NODE DT_INST(0, DT_DRV_COMPAT) + +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_INTC_LOG_LEVEL +#include +LOG_MODULE_REGISTER(intc_extint_hc32); + +#define INTC_EXTINT_NUM DT_PROP(EXTINT_NODE, extint_nums) +#define INTC_EXTINT_IRQN_DEF 0xFF + +static IRQn_Type extint_irq_table[INTC_EXTINT_NUM] = {[0 ... INTC_EXTINT_NUM - 1] = + INTC_EXTINT_IRQN_DEF}; + +/* wrapper for user callback */ +struct hc32_extint_cb { + hc32_extint_callback_t cb; + void *user; +}; + +struct hc32_extint_data { + /* callbacks */ + struct hc32_extint_cb cb[INTC_EXTINT_NUM]; +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + uint32_t extint_table; +#endif +}; + +/** + * @brief EXTINT ISR handler + */ +static void hc32_extint_isr(const void *arg) +{ + const struct device *dev = DEVICE_DT_GET(EXTINT_NODE); + struct hc32_extint_data *data = dev->data; + +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + uint32_t ch_idx; + + ARG_UNUSED(arg); + for (ch_idx = 0; ch_idx < INTC_EXTINT_NUM; ch_idx++) { + if (SET == EXTINT_GetExtIntStatus(BIT(ch_idx))) { + EXTINT_ClearExtIntStatus(BIT(ch_idx)); + /* run callback only if one is registered */ + if (data->cb[ch_idx].cb != NULL) { + data->cb[ch_idx].cb(ch_idx, data->cb[ch_idx].user); + } + } + } +#else + uint32_t ch = *(uint8_t *)arg; + + if (SET == EXTINT_GetExtIntStatus(BIT(ch))) { + EXTINT_ClearExtIntStatus(BIT(ch)); + /* run callback only if one is registered */ + if (data->cb[ch].cb != NULL) { + data->cb[ch].cb(ch, data->cb[ch].user); + } + } +#endif +} + +/* Configure irq information */ +static void hc32_irq_config(uint8_t ch, int irqn, int intsrc) +{ + /* fill irq table */ + extint_irq_table[ch] = (IRQn_Type)irqn; +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + INTC_ShareIrqCmd(intsrc, ENABLE); +#else + hc32_intc_irq_signin(irqn, intsrc); +#endif +} + +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) +#define HC32_EXTINT_INIT_SHARE(node_id, interrupts, idx) \ + hc32_irq_config(DT_PROP_BY_IDX(node_id, extint_chs, idx), \ + DT_IRQ_BY_IDX(node_id, idx, irq), DT_IRQ_BY_IDX(node_id, idx, int_src)); + +#else + +#define HC32_EXTINT_INIT(node_id, interrupts, idx) \ + static const uint8_t hc32_extint_ch_##idx = DT_PROP_BY_IDX(node_id, extint_chs, idx); \ + hc32_irq_config(hc32_extint_ch_##idx, DT_IRQ_BY_IDX(node_id, idx, irq), \ + DT_IRQ_BY_IDX(node_id, idx, int_src)); \ + IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), DT_IRQ_BY_IDX(node_id, idx, priority), \ + hc32_extint_isr, &hc32_extint_ch_##idx, 0); +#endif + +/** + * @brief initialize intc device driver + */ +static int hc32_intc_init(const struct device *dev) +{ +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + struct hc32_extint_data *data = dev->data; + + data->extint_table = 0; + DT_FOREACH_PROP_ELEM(EXTINT_NODE, interrupt_names, HC32_EXTINT_INIT_SHARE); + IRQ_CONNECT(DT_IRQ_BY_IDX(EXTINT_NODE, 0, irq), DT_IRQ_BY_IDX(EXTINT_NODE, 0, priority), + hc32_extint_isr, NULL, 0); +#else + ARG_UNUSED(dev); + DT_FOREACH_PROP_ELEM(EXTINT_NODE, interrupt_names, HC32_EXTINT_INIT); +#endif + + return 0; +} + +static void hc32_extint_enable(const struct device *dev, int port, int pin) +{ + int irqnum = 0; +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + struct hc32_extint_data *data = dev->data; +#else + ARG_UNUSED(dev); +#endif + + if (pin >= INTC_EXTINT_NUM) { + __ASSERT_NO_MSG(pin); + } + /* Get matching extint irq number from irq_table */ + irqnum = extint_irq_table[pin]; + if (irqnum == INTC_EXTINT_IRQN_DEF) { + __ASSERT_NO_MSG(pin); + } + + /* Enable requested pin interrupt */ + GPIO_ExtIntCmd((uint8_t)port, BIT((uint32_t)pin), ENABLE); +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + if (0 == data->extint_table) { + /* Enable extint irq interrupt */ + irq_enable(irqnum); + } + SET_REG32_BIT(data->extint_table, BIT((uint32_t)pin)); +#else + /* Enable extint irq interrupt */ + irq_enable(irqnum); +#endif +} + +static void hc32_extint_disable(const struct device *dev, int port, int pin) +{ + int irqnum = 0; +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + struct hc32_extint_data *data = dev->data; +#else + ARG_UNUSED(dev); +#endif + + if (pin >= INTC_EXTINT_NUM) { + __ASSERT_NO_MSG(pin); + } + /* Get matching extint irq number from irq_table */ + irqnum = extint_irq_table[pin]; + if (irqnum == INTC_EXTINT_IRQN_DEF) { + __ASSERT_NO_MSG(pin); + } + + /* Disable requested pin interrupt */ + GPIO_ExtIntCmd((uint8_t)port, BIT((uint32_t)pin), DISABLE); +#if defined(CONFIG_INTC_EXTINT_USE_SHARE_INTERRUPT) + CLR_REG32_BIT(data->extint_table, BIT((uint32_t)pin)); + if (0 == data->extint_table) { + /* Disable extint irq interrupt */ + irq_disable(irqnum); + } +#else + /* Disable extint irq interrupt */ + irq_disable(irqnum); +#endif +} + +static void hc32_extint_trigger(const struct device *dev, int pin, int trigger) +{ + stc_extint_init_t stc_extint_init; + + ARG_UNUSED(dev); + + if (pin >= INTC_EXTINT_NUM) { + __ASSERT_NO_MSG(pin); + } + + /* ExtInt config */ + (void)EXTINT_StructInit(&stc_extint_init); + switch (trigger) { + case HC32_EXTINT_TRIG_FALLING: + stc_extint_init.u32Edge = EXTINT_TRIG_FALLING; + break; + case HC32_EXTINT_TRIG_RISING: + stc_extint_init.u32Edge = EXTINT_TRIG_RISING; + break; + case HC32_EXTINT_TRIG_BOTH: + stc_extint_init.u32Edge = EXTINT_TRIG_BOTH; + break; + case HC32_EXTINT_TRIG_LOW_LVL: + stc_extint_init.u32Edge = EXTINT_TRIG_LOW; + break; + default: + __ASSERT_NO_MSG(trigger); + break; + } + EXTINT_Init(BIT((uint32_t)pin), &stc_extint_init); +} + +static int hc32_extint_set_callback(const struct device *dev, int pin, hc32_extint_callback_t cb, + void *user) +{ + struct hc32_extint_data *data = dev->data; + + if (pin >= INTC_EXTINT_NUM) { + __ASSERT_NO_MSG(pin); + } + + if ((data->cb[pin].cb == cb) && (data->cb[pin].user == user)) { + return 0; + } + /* if callback already exists/maybe-running return busy */ + if (data->cb[pin].cb != NULL) { + return -EBUSY; + } + data->cb[pin].cb = cb; + data->cb[pin].user = user; + + return 0; +} + +static void hc32_extint_unset_callback(const struct device *dev, int pin) +{ + struct hc32_extint_data *data = dev->data; + + if (pin >= INTC_EXTINT_NUM) { + __ASSERT_NO_MSG(pin); + } + + data->cb[pin].cb = NULL; + data->cb[pin].user = NULL; +} + +static struct hc32_extint_data extint_data; +static const struct hc32_extint_driver_api extint_api = { + .extint_enable = hc32_extint_enable, + .extint_disable = hc32_extint_disable, + .extint_set_trigger = hc32_extint_trigger, + .extint_set_cb = hc32_extint_set_callback, + .extint_unset_cb = hc32_extint_unset_callback, +}; + +DEVICE_DT_DEFINE(EXTINT_NODE, &hc32_intc_init, NULL, &extint_data, NULL, PRE_KERNEL_1, + CONFIG_INTC_INIT_PRIORITY, &extint_api); diff --git a/drivers/interrupt_controller/intc_hc32.c b/drivers/interrupt_controller/intc_hc32.c new file mode 100644 index 0000000000000..91abda57fab91 --- /dev/null +++ b/drivers/interrupt_controller/intc_hc32.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Driver for interrupt/event controller in HC32 MCUs + */ + +#define DT_DRV_COMPAT xhsc_hc32_intc + +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_INTC_LOG_LEVEL +#include +LOG_MODULE_REGISTER(intc_hc32); + +int hc32_intc_irq_signin(int irqn, int intsrc) +{ + stc_irq_signin_config_t stc_irq_sign_config; + + stc_irq_sign_config.enIRQn = (IRQn_Type)irqn; + stc_irq_sign_config.enIntSrc = (en_int_src_t)intsrc; + stc_irq_sign_config.pfnCallback = NULL; + if (LL_OK != INTC_IrqSignIn(&stc_irq_sign_config)) { + LOG_ERR("intc signin failed!"); + return -EACCES; + } + + return 0; +} + +int hc32_intc_irq_signout(int irqn) +{ + if (LL_OK != INTC_IrqSignOut((IRQn_Type)irqn)) { + LOG_ERR("intc signout failed!"); + return -EACCES; + } + + return 0; +} diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index ea46edf46dc5f..10970aa4f845d 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SF32LB52X pinctrl_sf32lb52x.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_HC32 pinctrl_hc32.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9050f3ef5c998..e624f9f69af65 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -88,6 +88,7 @@ source "drivers/pinctrl/Kconfig.realtek_rts5912" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" source "drivers/pinctrl/Kconfig.wch_00x_afio" source "drivers/pinctrl/Kconfig.sf32lb52x" +source "drivers/pinctrl/Kconfig.hc32" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.hc32 b/drivers/pinctrl/Kconfig.hc32 new file mode 100644 index 0000000000000..9e5a5763e1062 --- /dev/null +++ b/drivers/pinctrl/Kconfig.hc32 @@ -0,0 +1,9 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_HC32 + bool "Pin controller driver for xhsc hc32 processors" + default y + depends on DT_HAS_XHSC_HC32_PINCTRL_ENABLED + help + Enable pin controller driver for xhsc hc32 processors. diff --git a/drivers/pinctrl/pinctrl_hc32.c b/drivers/pinctrl/pinctrl_hc32.c new file mode 100644 index 0000000000000..fe388adf63c32 --- /dev/null +++ b/drivers/pinctrl/pinctrl_hc32.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define HC32_GPIO_PORT_VALID(nodelabel) \ + (DT_NODE_EXISTS(DT_NODELABEL(nodelabel))) \ + ? (DT_NODE_HAS_STATUS(DT_NODELABEL(nodelabel), okay)) \ + : (0) + +/** + * @brief Array containing bool value to each GPIO port. + * + * Entries will be 0 if the GPIO port is not enabled. + */ +static volatile uint8_t gpio_ports_valid[] = { + HC32_GPIO_PORT_VALID(gpioa), HC32_GPIO_PORT_VALID(gpiob), HC32_GPIO_PORT_VALID(gpioc), + HC32_GPIO_PORT_VALID(gpiod), HC32_GPIO_PORT_VALID(gpioe), HC32_GPIO_PORT_VALID(gpiof), + HC32_GPIO_PORT_VALID(gpiog), HC32_GPIO_PORT_VALID(gpioh), HC32_GPIO_PORT_VALID(gpioi), +}; + +static inline uint8_t HC32_get_port(uint8_t port_num) +{ +#if defined(HC32F460) + if ('H' == (port_num + 'A')) { + return GPIO_PORT_H; + } else { + return port_num; + } +#elif defined(HC32F4A0) + return port_num; +#endif +} + +static inline bool HC32_pin_is_valid(uint16_t pin) +{ + return ((pin & GPIO_PIN_ALL) == 0); +} + +static int hc32_pin_configure(const uint32_t pin_mux) +{ + uint8_t port_num = HC32_PORT(pin_mux); + uint16_t pin_num = BIT(HC32_PIN(pin_mux)); + uint8_t mode = HC32_MODE(pin_mux); + uint16_t func_num = HC32_FUNC_NUM(pin_mux); + stc_gpio_init_t stc_gpio_init; + + GPIO_StructInit(&stc_gpio_init); + + if ((gpio_ports_valid[port_num] != 1) || (HC32_pin_is_valid(pin_num))) { + return -EINVAL; + } + port_num = HC32_get_port(port_num); + + switch (mode) { + case HC32_ANALOG: + stc_gpio_init.u16PinAttr = PIN_ATTR_ANALOG; + goto end; + + case HC32_GPIO: + func_num = 0; + stc_gpio_init.u16PinAttr = PIN_ATTR_DIGITAL; + if (HC32_INPUT_ENABLE == HC32_PIN_EN_DIR(pin_mux)) { + /* input */ + stc_gpio_init.u16PinDir = PIN_DIR_IN; + } else { + /* output */ + stc_gpio_init.u16PinDir = PIN_DIR_OUT; + if (HC32_OUTPUT_HIGH == HC32_OUT_LEVEL(pin_mux)) { + stc_gpio_init.u16PinState = PIN_STAT_SET; + } + } + break; + + case HC32_FUNC: + GPIO_SetFunc(port_num, pin_num, func_num); + break; + + case HC32_SUBFUNC: + GPIO_SetSubFunc(func_num); + GPIO_SubFuncCmd(port_num, pin_num, ENABLE); + break; + + default: + break; + } + + if (HC32_PULL_UP == HC32_PIN_BIAS(pin_mux)) { + stc_gpio_init.u16PullUp = PIN_PU_ON; + } + if (HC32_PUSH_PULL == HC32_PIN_DRV(pin_mux)) { + stc_gpio_init.u16PinOutputType = PIN_OUT_TYPE_CMOS; + } else { + stc_gpio_init.u16PinOutputType = PIN_OUT_TYPE_NMOS; + } + + switch (HC32_PIN_DRIVER_STRENGTH(pin_mux)) { + case HC32_DRIVER_STRENGTH_LOW: + stc_gpio_init.u16PinDrv = PIN_LOW_DRV; + break; + + case HC32_DRIVER_STRENGTH_MEDIUM: + stc_gpio_init.u16PinDrv = PIN_MID_DRV; + break; + + case HC32_DRIVER_STRENGTH_HIGH: + stc_gpio_init.u16PinDrv = PIN_HIGH_DRV; + break; + + default: + break; + } +#if defined(HC32F4A0) + stc_gpio_init.u16PinInputType = + (HC32_CINSEL(pin_mux) == HC32_CINSEL_SCHMITT) ? PIN_IN_TYPE_SMT : PIN_IN_TYPE_CMOS; +#endif + + stc_gpio_init.u16Invert = + (HC32_INVERT_ENABLE == HC32_INVERT(pin_mux)) ? PIN_INVT_ON : PIN_INVT_OFF; + +end: + return GPIO_Init(port_num, pin_num, &stc_gpio_init); +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + int ret = 0; + + ARG_UNUSED(reg); + + for (uint8_t i = 0U; i < pin_cnt; i++) { + ret = hc32_pin_configure(pins[i]); + if (ret < 0) { + return ret; + } + } + + return 0; +} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 63520ac12639d..b6988ddeede53 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -38,6 +38,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB106X uart_ene_kb106x.c) zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB1200 uart_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_UART_ESP32 uart_esp32.c) zephyr_library_sources_ifdef(CONFIG_UART_GECKO uart_gecko.c) +zephyr_library_sources_ifdef(CONFIG_UART_HC32 uart_hc32.c) zephyr_library_sources_ifdef(CONFIG_UART_HOSTLINK uart_hostlink.c) zephyr_library_sources_ifdef(CONFIG_UART_IMX uart_imx.c) zephyr_library_sources_ifdef(CONFIG_UART_INFINEON_CAT1 uart_ifx_cat1.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 0d58009f31eb2..b545575d44668 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -179,6 +179,7 @@ rsource "Kconfig.ene" rsource "Kconfig.esp32" rsource "Kconfig.gd32" rsource "Kconfig.gecko" +rsource "Kconfig.hc32" rsource "Kconfig.hostlink" rsource "Kconfig.ifx_cat1" rsource "Kconfig.imx" diff --git a/drivers/serial/Kconfig.hc32 b/drivers/serial/Kconfig.hc32 new file mode 100644 index 0000000000000..6fffd5233b9ce --- /dev/null +++ b/drivers/serial/Kconfig.hc32 @@ -0,0 +1,16 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config UART_HC32 + bool "HC32 MCU serial driver" + default y + depends on DT_HAS_XHSC_HC32_UART_ENABLED + select SERIAL_HAS_DRIVER + select HC32_LL_USART + select SERIAL_SUPPORT_INTERRUPT if DT_HAS_XHSC_HC32_INTC_ENABLED + select UART_INTERRUPT_DRIVEN if DT_HAS_XHSC_HC32_INTC_ENABLED + select PINCTRL + help + This option enables the UART driver for HC32 family of + processors. + Set y if you wish to use serial port on HC32 MCU. diff --git a/drivers/serial/uart_hc32.c b/drivers/serial/uart_hc32.c new file mode 100644 index 0000000000000..5ed96501c9d11 --- /dev/null +++ b/drivers/serial/uart_hc32.c @@ -0,0 +1,783 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT xhsc_hc32_uart + +/** + * @brief Driver for UART port on HC32 family processor. + * @note + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "uart_hc32.h" + +#include +#include + +#include +#include +LOG_MODULE_REGISTER(uart_hc32, CONFIG_UART_LOG_LEVEL); + +/* This symbol takes the value 1 if one of the device instances */ +/* is configured in dts with a domain clock */ +#if HC32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define HC32_UART_DOMAIN_CLOCK_SUPPORT 1 +#else +#define HC32_UART_DOMAIN_CLOCK_SUPPORT 0 +#endif + +static inline void uart_hc32_set_parity(const struct device *dev, uint32_t parity) +{ + const struct uart_hc32_config *config = dev->config; + + USART_SetParity(config->usart, parity); +} + +static inline uint32_t uart_hc32_get_parity(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetParity(config->usart); +} + +static inline void uart_hc32_set_stopbits(const struct device *dev, uint32_t stopbits) +{ + const struct uart_hc32_config *config = dev->config; + + USART_SetStopBit(config->usart, stopbits); +} + +static inline uint32_t uart_hc32_get_stopbits(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetStopBit(config->usart); +} + +static inline void uart_hc32_set_databits(const struct device *dev, uint32_t databits) +{ + const struct uart_hc32_config *config = dev->config; + + USART_SetDataWidth(config->usart, databits); +} + +static inline uint32_t uart_hc32_get_databits(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetDataWidth(config->usart); +} + +static inline void uart_hc32_set_hwctrl(const struct device *dev, uint32_t hwctrl) +{ + const struct uart_hc32_config *config = dev->config; + + USART_SetHWFlowControl(config->usart, hwctrl); +} + +static inline uint32_t uart_hc32_get_hwctrl(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetHWFlowControl(config->usart); +} + +static inline void uart_hc32_set_baudrate(const struct device *dev, uint32_t baud_rate) +{ + const struct uart_hc32_config *config = dev->config; + + (void)USART_SetBaudrate(config->usart, baud_rate, NULL); +} + +static inline uint32_t uart_hc32_cfg2ll_parity(enum uart_config_parity parity) +{ + uint32_t ret_ll_parity = USART_PARITY_NONE; + + switch (parity) { + case UART_CFG_PARITY_ODD: + ret_ll_parity = USART_PARITY_ODD; + break; + case UART_CFG_PARITY_EVEN: + ret_ll_parity = USART_PARITY_EVEN; + break; + case UART_CFG_PARITY_NONE: + default: + break; + } + + return ret_ll_parity; +} + +static inline enum uart_config_parity uart_hc32_ll2cfg_parity(uint32_t parity) +{ + enum uart_config_parity ret_cfg_parity = UART_CFG_PARITY_NONE; + + switch (parity) { + case USART_PARITY_ODD: + ret_cfg_parity = UART_CFG_PARITY_ODD; + break; + case USART_PARITY_EVEN: + ret_cfg_parity = UART_CFG_PARITY_EVEN; + break; + case USART_PARITY_NONE: + default: + break; + } + + return ret_cfg_parity; +} + +static inline uint32_t uart_hc32_cfg2ll_stopbits(enum uart_config_stop_bits sb) +{ + uint32_t ret_ll_stopbits = USART_STOPBIT_1BIT; + +#ifdef USART_STOPBIT_2BIT + if (sb == UART_CFG_STOP_BITS_2) { + ret_ll_stopbits = USART_STOPBIT_2BIT; + } +#endif /* USART_STOPBIT_2BIT */ + + return ret_ll_stopbits; +} + +static inline enum uart_config_stop_bits uart_hc32_ll2cfg_stopbits(uint32_t sb) +{ + enum uart_config_stop_bits ret_cfg_stopbits = UART_CFG_STOP_BITS_1; + +#ifdef USART_STOPBIT_2BIT + if (sb == USART_STOPBIT_2BIT) { + ret_cfg_stopbits = UART_CFG_STOP_BITS_2; + } +#endif /* USART_STOPBIT_2BIT */ + + return ret_cfg_stopbits; +} + +static inline uint32_t uart_hc32_cfg2ll_databits(enum uart_config_data_bits db) +{ + uint32_t ret_ll_databits = USART_DATA_WIDTH_8BIT; + +/* Some MCU's don't support 9B datawidth */ +#ifdef USART_DATA_WIDTH_9BIT + if (db == UART_CFG_DATA_BITS_9) { + ret_ll_databits = USART_DATA_WIDTH_9BIT; + } +#endif /* USART_DATA_WIDTH_9BIT */ + + return ret_ll_databits; +} + +static inline enum uart_config_data_bits uart_hc32_ll2cfg_databits(uint32_t db) +{ + enum uart_config_data_bits ret_cfg_databits = UART_CFG_DATA_BITS_8; + +/* Some MCU's don't support 9B datawidth */ +#ifdef USART_DATA_WIDTH_9BIT + if (db == USART_DATA_WIDTH_9BIT) { + ret_cfg_databits = UART_CFG_DATA_BITS_9; + } +#endif /* USART_DATA_WIDTH_9BIT */ + + return ret_cfg_databits; +} + +/** + * @brief Get DDL hardware flow control define from + * Zephyr hardware flow control option. + * @note Supports only UART_CFG_FLOW_CTRL_RTS_CTS and UART_CFG_FLOW_CTRL_RS485. + * @param fc: Zephyr hardware flow control option. + * @retval USART_HW_FLOWCTRL_RTS, for device under supporting RTS_CTS. + */ +static inline uint32_t uart_hc32_cfg2ll_hwctrl(enum uart_config_flow_control fc) +{ + /* default config */ + return USART_HW_FLOWCTRL_RTS; +} + +/** + * @brief Get Zephyr hardware flow control option from + * DDL hardware flow control define. + * @note + * @param fc: DDL hardware flow control definition. + * @retval UART_CFG_FLOW_CTRL_RTS_CTS, or UART_CFG_FLOW_CTRL_NONE. + */ +static inline enum uart_config_flow_control uart_hc32_ll2cfg_hwctrl(uint32_t fc) +{ + /* DDL driver compatible with cfg, just return none */ + return UART_CFG_FLOW_CTRL_NONE; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE +static int uart_hc32_configure(const struct device *dev, const struct uart_config *cfg) +{ + const struct uart_hc32_config *config = dev->config; + struct uart_hc32_data *data = dev->data; + struct uart_config *uart_cfg = data->uart_cfg; + const uint32_t parity = uart_hc32_cfg2ll_parity(cfg->parity); + const uint32_t stopbits = uart_hc32_cfg2ll_stopbits(cfg->stop_bits); + const uint32_t databits = uart_hc32_cfg2ll_databits(cfg->data_bits); + + /* Hardware doesn't support mark or space parity */ + if ((cfg->parity == UART_CFG_PARITY_MARK) || (cfg->parity == UART_CFG_PARITY_SPACE)) { + return -ENOTSUP; + } + + /* Driver does not supports parity + 9 databits */ + if ((cfg->parity != UART_CFG_PARITY_NONE) && (cfg->data_bits == USART_DATA_WIDTH_9BIT)) { + return -ENOTSUP; + } + + /* When the transformed ddl parity don't match with what was requested, + * then it's not supported + */ + if (uart_hc32_ll2cfg_parity(parity) != cfg->parity) { + return -ENOTSUP; + } + + /* When the transformed ddl stop bits don't match with what was requested, + * then it's not supported + */ + if (uart_hc32_ll2cfg_stopbits(stopbits) != cfg->stop_bits) { + return -ENOTSUP; + } + + /* When the transformed ddl databits don't match with what was requested, + * then it's not supported + */ + if (uart_hc32_ll2cfg_databits(databits) != cfg->data_bits) { + return -ENOTSUP; + } + + USART_FuncCmd(config->usart, USART_TX | USART_RX, DISABLE); + uart_hc32_set_parity(dev, parity); + uart_hc32_set_stopbits(dev, stopbits); + uart_hc32_set_databits(dev, databits); + uart_hc32_set_baudrate(dev, uart_cfg->baudrate); + USART_FuncCmd(config->usart, USART_TX | USART_RX, ENABLE); + + return 0; +} + +static int uart_hc32_config_get(const struct device *dev, struct uart_config *cfg) +{ + struct uart_hc32_data *data = dev->data; + struct uart_config *uart_cfg = data->uart_cfg; + + cfg->baudrate = uart_cfg->baudrate; + cfg->parity = uart_hc32_ll2cfg_parity(uart_hc32_get_parity(dev)); + cfg->stop_bits = uart_hc32_ll2cfg_stopbits(uart_hc32_get_stopbits(dev)); + cfg->data_bits = uart_hc32_ll2cfg_databits(uart_hc32_get_databits(dev)); + cfg->flow_ctrl = uart_hc32_ll2cfg_hwctrl(uart_hc32_get_hwctrl(dev)); + + return 0; +} +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + +static int uart_hc32_poll_in(const struct device *dev, unsigned char *c) +{ + const struct uart_hc32_config *config = dev->config; + + if (USART_GetStatus(config->usart, USART_FLAG_OVERRUN | USART_FLAG_RX_TIMEOUT)) { + + USART_ClearStatus(config->usart, USART_FLAG_OVERRUN | USART_FLAG_FRAME_ERR); + } + + if (SET != USART_GetStatus(config->usart, USART_FLAG_RX_FULL)) { + return EIO; + } + + *c = (unsigned char)USART_ReadData(config->usart); + return 0; +} + +static void uart_hc32_poll_out(const struct device *dev, unsigned char c) +{ + unsigned int key; + const struct uart_hc32_config *config = dev->config; + + key = irq_lock(); + while (1) { + if (USART_GetStatus(config->usart, USART_FLAG_TX_EMPTY)) { + break; + } + } + + USART_WriteData(config->usart, (uint16_t)c); + irq_unlock(key); +} + +static int uart_hc32_err_check(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + uint32_t err = 0U; + + if (USART_GetStatus(config->usart, USART_FLAG_OVERRUN)) { + err |= UART_ERROR_OVERRUN; + } + + if (USART_GetStatus(config->usart, USART_FLAG_FRAME_ERR)) { + err |= UART_ERROR_FRAMING; + } + + if (USART_GetStatus(config->usart, USART_FLAG_PARITY_ERR)) { + err |= UART_ERROR_PARITY; + } + + return err; +} + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + +typedef void (*fifo_fill_fn)(const struct device *dev, const void *tx_data, const uint8_t offset); + +static int uart_hc32_fifo_fill_visitor(const struct device *dev, const void *tx_data, int size, + fifo_fill_fn fill_fn) +{ + const struct uart_hc32_config *config = dev->config; + uint8_t num_tx = 0U; + unsigned int key; + + if (!USART_GetStatus(config->usart, USART_FLAG_TX_EMPTY)) { + return num_tx; + } + + /* Lock interrupts to prevent nested interrupts or thread switch */ + key = irq_lock(); + + /* TXE flag will be set by hardware when moving data */ + while ((size - num_tx > 0) && USART_GetStatus(config->usart, USART_FLAG_TX_EMPTY)) { + /* Send a character */ + fill_fn(dev, tx_data, num_tx); + num_tx++; + } + + irq_unlock(key); + + return num_tx; +} + +static void fifo_fill_with_u8(const struct device *dev, const void *tx_data, const uint8_t offset) +{ + const uint8_t *data = (const uint8_t *)tx_data; + /* Send a character (8bit) */ + uart_hc32_poll_out(dev, data[offset]); +} + +static int uart_hc32_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ + if (UART_CFG_DATA_BITS_9 == uart_hc32_ll2cfg_databits(uart_hc32_get_databits(dev))) { + return -ENOTSUP; + } + return uart_hc32_fifo_fill_visitor(dev, (const void *)tx_data, size, fifo_fill_with_u8); +} + +typedef void (*fifo_read_fn)(const struct uart_hc32_config *config, void *rx_data, + const uint8_t offset); + +static int uart_hc32_fifo_read_visitor(const struct device *dev, void *rx_data, const int size, + fifo_read_fn read_fn) +{ + const struct uart_hc32_config *config = dev->config; + uint8_t num_rx = 0U; + + while ((size - num_rx > 0) && USART_GetStatus(config->usart, USART_FLAG_RX_FULL)) { + /* RXNE flag will be cleared upon read from RDR register */ + + read_fn(config, rx_data, num_rx); + num_rx++; + + /* Clear overrun error flag */ + if (USART_GetStatus(config->usart, USART_FLAG_OVERRUN)) { + USART_ClearStatus(config->usart, USART_FLAG_OVERRUN); + } + } + + return num_rx; +} + +static void fifo_read_with_u8(const struct uart_hc32_config *config, void *rx_data, + const uint8_t offset) +{ + uint8_t *data = (uint8_t *)rx_data; + + USART_UART_Receive(config->usart, &data[offset], 1U, 0xFFU); +} + +static int uart_hc32_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) +{ + if (UART_CFG_DATA_BITS_9 == uart_hc32_ll2cfg_databits(uart_hc32_get_databits(dev))) { + + return -ENOTSUP; + } + return uart_hc32_fifo_read_visitor(dev, (void *)rx_data, size, fifo_read_with_u8); +} + +static void uart_hc32_irq_tx_enable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + USART_FuncCmd(config->usart, USART_INT_TX_EMPTY | USART_INT_TX_CPLT, ENABLE); +} + +static void uart_hc32_irq_tx_disable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + USART_FuncCmd(config->usart, USART_INT_TX_EMPTY | USART_INT_TX_CPLT, DISABLE); +} + +static int uart_hc32_irq_tx_ready(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetStatus(config->usart, USART_FLAG_TX_EMPTY); +} + +static int uart_hc32_irq_tx_complete(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetStatus(config->usart, USART_FLAG_TX_CPLT); +} + +static void uart_hc32_irq_rx_enable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + USART_FuncCmd(config->usart, USART_INT_RX, ENABLE); +} + +static void uart_hc32_irq_rx_disable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + USART_FuncCmd(config->usart, USART_INT_RX, DISABLE); +} + +static int uart_hc32_irq_rx_ready(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetStatus(config->usart, USART_FLAG_RX_FULL); +} + +static void uart_hc32_irq_err_enable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + /* Enable FE, ORE parity error interruption */ + USART_FuncCmd(config->usart, USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT, ENABLE); +} + +static void uart_hc32_irq_err_disable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + USART_FuncCmd(config->usart, USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT, DISABLE); +} + +static int uart_hc32_irq_is_pending(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + + return USART_GetStatus(config->usart, USART_FLAG_ALL); +} + +static int uart_hc32_irq_update(const struct device *dev) +{ + ARG_UNUSED(dev); + return 1; +} + +/* + * user may use void *user_data = x to specify irq type, the x may be: + * 0：usart_hc32f4_rx_error_isr + * 1：usart_hc32f4_rx_full_isr + * 2：usart_hc32f4_tx_empty_isr + * 3：usart_hc32f4_tx_complete_isr + * 4：usart_hc32f4_rx_timeout_isr + * others or user_data = NULL：set cb for all interrupt handlers + */ +static void uart_hc32_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, + void *user_data) +{ + uint32_t i; + struct uart_hc32_data *data = dev->data; + + if ((user_data == NULL) || (*(uint32_t *)user_data >= HC32_UART_INT_NUM)) { + for (i = 0; i < HC32_UART_INT_NUM; i++) { + data->cb[i].user_cb = cb; + data->cb[i].user_data = user_data; + } + } else { + i = *(uint32_t *)user_data; + data->cb[i].user_cb = cb; + data->cb[i].user_data = user_data; + } +} + +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +static const struct uart_driver_api uart_hc32_driver_api = { + .poll_in = uart_hc32_poll_in, + .poll_out = uart_hc32_poll_out, + .err_check = uart_hc32_err_check, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = uart_hc32_configure, + .config_get = uart_hc32_config_get, +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + .fifo_fill = uart_hc32_fifo_fill, + .fifo_read = uart_hc32_fifo_read, + .irq_tx_enable = uart_hc32_irq_tx_enable, + .irq_tx_disable = uart_hc32_irq_tx_disable, + .irq_tx_ready = uart_hc32_irq_tx_ready, + .irq_tx_complete = uart_hc32_irq_tx_complete, + .irq_rx_enable = uart_hc32_irq_rx_enable, + .irq_rx_disable = uart_hc32_irq_rx_disable, + .irq_rx_ready = uart_hc32_irq_rx_ready, + .irq_err_enable = uart_hc32_irq_err_enable, + .irq_err_disable = uart_hc32_irq_err_disable, + .irq_is_pending = uart_hc32_irq_is_pending, + .irq_update = uart_hc32_irq_update, + .irq_callback_set = uart_hc32_irq_callback_set, +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +}; + +static int uart_hc32_registers_configure(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + struct uart_hc32_data *data = dev->data; + struct uart_config *uart_cfg = data->uart_cfg; + stc_usart_uart_init_t stcUartInit; + + USART_FuncCmd(config->usart, HC32_UART_FUNC, DISABLE); + + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32ClockDiv = USART_CLK_DIV16; + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + stcUartInit.u32Baudrate = uart_cfg->baudrate; + stcUartInit.u32StopBit = uart_hc32_cfg2ll_stopbits(uart_cfg->stop_bits); + stcUartInit.u32Parity = uart_hc32_cfg2ll_parity(uart_cfg->parity); + + (void)USART_UART_Init(config->usart, &stcUartInit, NULL); + USART_FuncCmd(config->usart, USART_TX | USART_RX, ENABLE); + + return 0; +} + +static inline void __uart_hc32_get_clock(const struct device *dev) +{ + struct uart_hc32_data *data = dev->data; + const struct device *const clk = DEVICE_DT_GET(HC32_CLOCK_CONTROL_NODE); + + data->clock = clk; +} + +static int uart_hc32_clocks_enable(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + struct uart_hc32_data *data = dev->data; + int err; + + __uart_hc32_get_clock(dev); + + if (!device_is_ready(data->clock)) { + LOG_ERR("clock control device not ready"); + return -ENODEV; + } + + /* enable clock */ + err = clock_control_on(data->clock, (clock_control_subsys_t)(config->clk_cfg)); + if (err != 0) { + LOG_ERR("Could not enable UART clock"); + return err; + } + return 0; +} + +/** + * @brief Initialize UART channel + * + * This routine is called to reset the chip in a quiescent state. + * It is assumed that this function is called only once per UART. + * + * @param dev UART device struct + * + * @return 0 + */ +static int uart_hc32_init(const struct device *dev) +{ + const struct uart_hc32_config *config = dev->config; + int err; + + err = uart_hc32_clocks_enable(dev); + if (err < 0) { + return err; + } + + /* Configure dt provided device signals when available */ + err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT); + if (err < 0) { + return err; + } + + err = uart_hc32_registers_configure(dev); + if (err < 0) { + return err; + } + +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + if ((uart_irq_config_func_t)NULL != config->irq_config_func) { + config->irq_config_func(dev); + } +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + + return 0; +} + +#define DT_USART_HAS_INTR(node_id) IS_ENABLED(DT_CAT4(node_id, _P_, interrupts, _EXISTS)) + +#define DT_IS_INTR_EXIST(index) DT_USART_HAS_INTR(DT_INST(index, xhsc_hc32_uart)) + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + +#define DT_IS_HC32_USART_INT_DEF(node_id, isr_name) \ + IS_ENABLED(DT_CAT4(node_id, _IRQ_NAME_, isr_name, _VAL_irq_EXISTS)) + +#define DT_IS_HC32_UART_INTR_EXIST(index, isr_name) \ + DT_IS_HC32_USART_INT_DEF(DT_INST(index, xhsc_hc32_uart), isr_name) + +#define USART_IRQ_ISR_CONFIG(isr_name, index) \ + IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, isr_name, irq), \ + DT_INST_IRQ_BY_NAME(index, isr_name, priority), \ + DT_CAT4(usart_hc32_, isr_name, _isr_, index), DEVICE_DT_INST_GET(index), 0); \ + hc32_intc_irq_signin(DT_INST_IRQ_BY_NAME(index, isr_name, irq), \ + DT_INST_IRQ_BY_NAME(index, isr_name, int_src)); \ + irq_enable(DT_INST_IRQ_BY_NAME(index, isr_name, irq)); + +#define HC32_UART_IRQ_HANDLER_DECL(index) \ + static void usart_hc32_config_func_##index(const struct device *dev); \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, ore), \ + (static void usart_hc32_ore_isr_##index(const struct device *dev);) \ + , ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, rxne), \ + (static void usart_hc32_rxne_isr_##index(const struct device *dev);) \ + , ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, tc), \ + (static void usart_hc32_tc_isr_##index(const struct device *dev);) \ + , ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, txe), \ + (static void usart_hc32_txe_isr_##index(const struct device *dev);) \ + , ()) + +#define HC32_UART_IRQ_HANDLER_DEF_BY_NAME(index, name, cb_idx) \ + static void usart_hc32_##name##_isr_##index(const struct device *dev) \ + { \ + struct uart_hc32_data *const data = dev->data; \ + \ + if (data->cb[cb_idx].user_cb) { \ + data->cb[cb_idx].user_cb(dev, data->cb[cb_idx].user_data); \ + } \ + } + +#define HC32_UART_IRQ_HANDLER_DEF(index) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, ore), \ + (HC32_UART_IRQ_HANDLER_DEF_BY_NAME(index, ore, HC32_UART_IDX_EI)), \ + ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, rxne), \ + (HC32_UART_IRQ_HANDLER_DEF_BY_NAME(index, rxne, HC32_UART_IDX_EI)), \ + ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, tc), \ + (HC32_UART_IRQ_HANDLER_DEF_BY_NAME(index, tc, HC32_UART_IDX_EI)), \ + ()) \ + COND_CODE_1(DT_IS_HC32_UART_INTR_EXIST(index, txe), \ + (HC32_UART_IRQ_HANDLER_DEF_BY_NAME(index, txe, HC32_UART_IDX_EI)), \ + ()) \ + \ + static void usart_hc32_config_func_##index(const struct device *dev) \ + { \ + COND_CODE_1( \ + DT_IS_HC32_UART_INTR_EXIST(index, ore), \ + (USART_IRQ_ISR_CONFIG(ore, index)), ()) \ + COND_CODE_1( \ + DT_IS_HC32_UART_INTR_EXIST(index, rxne), \ + (USART_IRQ_ISR_CONFIG(rxne, index)), ()) \ + COND_CODE_1( \ + DT_IS_HC32_UART_INTR_EXIST(index, tc), \ + (USART_IRQ_ISR_CONFIG(tc, index)), ()) \ + COND_CODE_1( \ + DT_IS_HC32_UART_INTR_EXIST(index, txe), \ + (USART_IRQ_ISR_CONFIG(txe, index)), ()) \ + } + +#define HC32_UART_IRQ_HANDLER_FUNC(index) .irq_config_func = usart_hc32_config_func_##index, +#define HC32_UART_IRQ_HANDLER_NULL(index) .irq_config_func = (uart_irq_config_func_t)NULL, + +#define HC32_UART_IRQ_HANDLER_PRE_FUNC(index) \ + COND_CODE_1( \ + DT_IS_INTR_EXIST(index), \ + (HC32_UART_IRQ_HANDLER_FUNC(index)), \ + (HC32_UART_IRQ_HANDLER_NULL(index))) + +#define HC32_UART_IRQ_HANDLER_PRE_DECL(index) \ + COND_CODE_1( \ + DT_IS_INTR_EXIST(index), \ + (HC32_UART_IRQ_HANDLER_DECL(index)), \ + ()) + +#define HC32_UART_IRQ_HANDLER_PRE_DEF(index) \ + COND_CODE_1( \ + DT_IS_INTR_EXIST(index), \ + (HC32_UART_IRQ_HANDLER_DEF(index)), \ + ()) +#else /* CONFIG_UART_INTERRUPT_DRIVEN */ +#define HC32_UART_IRQ_HANDLER_PRE_DECL(index) +#define HC32_UART_IRQ_HANDLER_PRE_DEF(index) +#define HC32_UART_IRQ_HANDLER_PRE_FUNC(index) +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +#define HC32_UART_CLOCK_DECL(index) \ + static struct hc32_modules_clock_sys uart_fcg_config_##index[] = \ + HC32_MODULES_CLOCKS(DT_DRV_INST(index)); + +#define HC32_UART_INIT(index) \ + HC32_UART_CLOCK_DECL(index) \ + HC32_UART_IRQ_HANDLER_PRE_DECL(index) \ + PINCTRL_DT_INST_DEFINE(index); \ + static struct uart_config uart_cfg_##index = { \ + .baudrate = DT_INST_PROP_OR(index, current_speed, HC32_UART_DEFAULT_BAUDRATE), \ + .parity = DT_INST_ENUM_IDX_OR(index, parity, HC32_UART_DEFAULT_PARITY), \ + .stop_bits = DT_INST_ENUM_IDX_OR(index, stop_bits, HC32_UART_DEFAULT_STOP_BITS), \ + .data_bits = DT_INST_ENUM_IDX_OR(index, data_bits, HC32_UART_DEFAULT_DATA_BITS), \ + .flow_ctrl = DT_INST_PROP(index, hw_flow_control) ? UART_CFG_FLOW_CTRL_RTS_CTS \ + : UART_CFG_FLOW_CTRL_NONE, \ + }; \ + static const struct uart_hc32_config uart_hc32_cfg_##index = { \ + .usart = (CM_USART_TypeDef *)DT_INST_REG_ADDR(index), \ + .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ + .clk_cfg = uart_fcg_config_##index, \ + HC32_UART_IRQ_HANDLER_PRE_FUNC(index)}; \ + static struct uart_hc32_data uart_hc32_data_##index = { \ + .uart_cfg = &uart_cfg_##index, \ + }; \ + DEVICE_DT_INST_DEFINE(index, &uart_hc32_init, NULL, &uart_hc32_data_##index, \ + &uart_hc32_cfg_##index, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ + &uart_hc32_driver_api); \ + HC32_UART_IRQ_HANDLER_PRE_DEF(index) + +DT_INST_FOREACH_STATUS_OKAY(HC32_UART_INIT) diff --git a/drivers/serial/uart_hc32.h b/drivers/serial/uart_hc32.h new file mode 100644 index 0000000000000..a76cad9d4a49d --- /dev/null +++ b/drivers/serial/uart_hc32.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Driver for interrupt/event controller in HC32 MCUs + */ + +#ifndef ZEPHYR_DRIVERS_SERIAL_UART_HC32_H_ +#define ZEPHYR_DRIVERS_SERIAL_UART_HC32_H_ + +#include +#include +#include + +#include + +#define HC32_UART_DEFAULT_BAUDRATE 115200 +#define HC32_UART_DEFAULT_PARITY UART_CFG_PARITY_NONE +#define HC32_UART_DEFAULT_STOP_BITS UART_CFG_STOP_BITS_1 +#define HC32_UART_DEFAULT_DATA_BITS UART_CFG_DATA_BITS_8 + +#define HC32_UART_FUNC (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_INT_TX_EMPTY) + +#if CONFIG_UART_INTERRUPT_DRIVEN +enum UART_TYPE { + HC32_UART_IDX_EI, + HC32_UART_IDX_RI, + HC32_UART_IDX_TI, + HC32_UART_IDX_TCI, + HC32_UART_INT_NUM +}; +#endif /* UART_INTERRUPT_DRIVEN */ + +/* device config */ +struct uart_hc32_config { + /* USART instance */ + CM_USART_TypeDef *usart; + /* clock subsystem driving this peripheral */ + struct hc32_modules_clock_sys *clk_cfg; + /* pin muxing */ + const struct pinctrl_dev_config *pin_cfg; +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + uart_irq_config_func_t irq_config_func; +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +}; + +struct hc32_usart_cb_data { + /** Callback function */ + uart_irq_callback_user_data_t user_cb; + /** User data. */ + void *user_data; +}; + +/* driver data */ +struct uart_hc32_data { + /* clock device */ + const struct device *clock; + /* uart config */ + struct uart_config *uart_cfg; +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) + struct hc32_usart_cb_data cb[HC32_UART_INT_NUM]; +#endif + +#ifdef CONFIG_UART_ASYNC_API + const struct device *uart_dev; + uart_callback_t async_cb; + void *async_user_data; + uint8_t *rx_next_buffer; + size_t rx_next_buffer_len; +#endif +}; + +#endif /* ZEPHYR_DRIVERS_SERIAL_UART_HC32_H_ */ diff --git a/dts/arm/xhsc/f4/hc32f4a0.dtsi b/dts/arm/xhsc/f4/hc32f4a0.dtsi new file mode 100644 index 0000000000000..0112205138090 --- /dev/null +++ b/dts/arm/xhsc/f4/hc32f4a0.dtsi @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + flash-controller@40010400 { + compatible = "xhsc,hc32-flash-controller"; + reg = <0x40010400 0x0400>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 0x200000>; + erase-block-size = <8192>; + write-block-size = <4>; + }; + }; + + /* The on-chip SRAM is split into SRAM0 and SRAMH regions that form a + * contiguous block in the memory map, however misaligned accesses + * across the 0x2000_0000 boundary are not supported in the Arm + * Cortex-M4 architecture. + */ + sramh: memory@1ffe0000 { + device_type = "memory"; + compatible ="zephyr,memory-region", "mmio-sram"; + zephyr,memory-region = "SRAMH"; + reg = <0x1ffe0000 DT_SIZE_K(128)>; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(384)>; + }; + + sramb: memory@200F0000 { + device_type = "memory"; + compatible = "zephyr,memory-region","mmio-sram"; + zephyr,memory-region = "SRAMB"; + reg = <0x200F0000 DT_SIZE_K(4)>; + }; + + soc { + clocks: clock@40048400{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40048400 0x400>; + compatible = "xhsc,hc32-clock-control"; + clock-conf = ; + + clk_xtal: clock_xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <8000000>; + }; + + clk_xtal32: clock_xtal32 { + #clock-cells = <0>; + compatible = "xhsc,hc32-clock-xtal32"; + clock-frequency = <32768>; + drive-strength = <0>; + }; + + clk_hrc: clock_hrc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + }; + + clk_mrc: clock_mrc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <8000000>; + }; + + clk_lrc: clock_lrc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_pll: clock_pll { + #clock-cells = <0>; + compatible = "xhsc,hc32-clock-pll"; + clock-frequency = <240000000>; + clocks = <&clk_xtal>; + div-m = <1>; + mul-n = <120>; + div-p = <4>; + div-q = <4>; + div-r = <4>; + }; + + clk_sys: clock_system { + compatible = "xhsc,hc32-clock-sys"; + clocks = <&clk_pll>; + div-hclk = <1>; + div-exclk = <2>; + div-pclk0 = <1>; + div-pclk1 = <2>; + div-pclk2 = <4>; + div-pclk3 = <4>; + div-pclk4 = <2>; + }; + + bus_fcg: pwc_fcg@40048000 { + #clock-cells = <3>; + compatible = "xhsc,hc32-bus-fcg"; + reg = <0x40048000 DT_SIZE_K(1)>; + }; + }; + + pinctrl: pin-controller@40053c00 { + compatible = "xhsc,hc32-pinctrl"; + reg = <0x40053c00 0x400>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + gpioa: gpio@40053c00 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053c00 0x40>; + }; + + gpiob: gpio@40053c40 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053c40 0x40>; + }; + + gpioc: gpio@40053c80 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053c80 0x40>; + }; + + gpiod: gpio@40053cc0 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053cc0 0x40>; + }; + + gpioe: gpio@40053d00 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053d00 0x40>; + }; + + gpiof: gpio@40053d40 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053d40 0x40>; + }; + + gpiog: gpio@40053d80 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053d80 0x40>; + }; + + gpioh: gpio@40053dc0 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053dc0 0x40>; + }; + + gpioi: gpio@40053e00 { + compatible = "xhsc,hc32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40053e00 0x40>; + }; + }; + + intc: interrupt-controller@40051000 { + compatible = "xhsc,hc32-intc"; + reg = <0x40051000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + status = "okay"; + + extint { + compatible = "xhsc,hc32-extint"; + interrupt-parent = <&intc>; + extint-nums = <16>; + extint-chs = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "extint0", "extint1", "extint2", "extint3", + "extint4", "extint5", "extint6", "extint7", + "extint8", "extint9", "extint10", "extint11", + "extint12", "extint13", "extint14", "extint15"; + status = "okay"; + }; + }; + + usart1: serial@4001cc00 { + compatible = "xhsc,hc32-uart"; + reg = <0x4001cc00 0x400>; + clocks = <&bus_fcg HC32_CLK_BUS_PCLK1 HC32_CLK_FCG3 \ + HC32_FCG3_PERIPH_USART1>; + status = "disabled"; + }; + + usart2: serial@4001d000 { + compatible = "xhsc,hc32-uart"; + reg = <0x4001d000 0x400>; + clocks = <&bus_fcg HC32_CLK_BUS_PCLK1 HC32_CLK_FCG3 \ + HC32_FCG3_PERIPH_USART2>; + status = "disabled"; + }; + + usart3: serial@4001d400 { + compatible = "xhsc,hc32-uart"; + reg = <0x4001d400 0x400>; + clocks = <&bus_fcg HC32_CLK_BUS_PCLK1 HC32_CLK_FCG3 \ + HC32_FCG3_PERIPH_USART3>; + status = "disabled"; + }; + + usart4: serial@4001d800 { + compatible = "xhsc,hc32-uart"; + reg = <0x4001d800 0x400>; + clocks = <&bus_fcg HC32_CLK_BUS_PCLK1 HC32_CLK_FCG3 \ + HC32_FCG3_PERIPH_USART4>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/bindings/clock/xhsc,hc32-bus-fcg.yaml b/dts/bindings/clock/xhsc,hc32-bus-fcg.yaml new file mode 100644 index 0000000000000..7ab51b71d3b44 --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-bus-fcg.yaml @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: | + HC32 Bus FCG + enable peripherals clock.get cells value ref macro HC32_MODULES_CLOCKS + +compatible: "xhsc,hc32-bus-fcg" + +include: [clock-controller.yaml, base.yaml] + +properties: + "#clock-cells": + const: 3 + +clock-cells: + - bus + - fcg + - bits diff --git a/dts/bindings/clock/xhsc,hc32-clock-control.yaml b/dts/bindings/clock/xhsc,hc32-clock-control.yaml new file mode 100644 index 0000000000000..1260e63d97d2c --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-control.yaml @@ -0,0 +1,15 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 Clock Control + +compatible: "xhsc,hc32-clock-control" + +include: [base.yaml, pinctrl-device.yaml] + +properties: + + clock-conf: + type: array + description: | + clock control configuration diff --git a/dts/bindings/clock/xhsc,hc32-clock-hrc.yaml b/dts/bindings/clock/xhsc,hc32-clock-hrc.yaml new file mode 100644 index 0000000000000..7dae8a98d8c5a --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-hrc.yaml @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 Hrc Clock + +compatible: "xhsc,hc32-clock-hrc" + +include: [fixed-clock.yaml] diff --git a/dts/bindings/clock/xhsc,hc32-clock-mrc.yaml b/dts/bindings/clock/xhsc,hc32-clock-mrc.yaml new file mode 100644 index 0000000000000..41d26669ba23b --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-mrc.yaml @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 Mrc Clock + +compatible: "xhsc,hc32-clock-mrc" + +include: [fixed-clock.yaml] diff --git a/dts/bindings/clock/xhsc,hc32-clock-pll.yaml b/dts/bindings/clock/xhsc,hc32-clock-pll.yaml new file mode 100644 index 0000000000000..465426cdbda71 --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-pll.yaml @@ -0,0 +1,53 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 PLL Clock + +compatible: "xhsc,hc32-clock-pll" + +include: [clock-controller.yaml, base.yaml] + +properties: + + clocks: + required: true + + clock-frequency: + type: int + required: true + + div-m: + type: int + required: true + description: | + Division factor for PLL + input clock + Valid range: 1 - 24 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 20 - 480 + + div-p: + type: int + description: | + PLL division factor for pll_p_ck + Valid range: 2 - 16 + + div-q: + type: int + description: | + PLL division factor for pll_q_ck + Valid range: 2 - 16 + + div-r: + type: int + description: | + PLL division factor for pll_r_ck + Valid range: 2 - 16 + + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/xhsc,hc32-clock-sys.yaml b/dts/bindings/clock/xhsc,hc32-clock-sys.yaml new file mode 100644 index 0000000000000..abfb40dadee12 --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-sys.yaml @@ -0,0 +1,107 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 System Clock + +compatible: "xhsc,hc32-clock-sys" + +include: [base.yaml] + +properties: + div-hclk: + type: int + required: true + description: | + Division factor for HCLK + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-exclk: + type: int + required: true + description: | + Division factor for ExMC CLK + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-pclk0: + type: int + required: true + description: | + Division factor for PCLK0 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-pclk1: + type: int + required: true + description: | + Division factor for PCLK1 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-pclk2: + type: int + required: true + description: | + Division factor for PCLK2 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-pclk3: + type: int + required: true + description: | + Division factor for PCLK3 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + + div-pclk4: + type: int + required: true + description: | + Division factor for PCLK4 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 diff --git a/dts/bindings/clock/xhsc,hc32-clock-xtal.yaml b/dts/bindings/clock/xhsc,hc32-clock-xtal.yaml new file mode 100644 index 0000000000000..995c7b78be263 --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-xtal.yaml @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 XTAL Clock + +compatible: "xhsc,hc32-clock-xtal" + +include: [fixed-clock.yaml] diff --git a/dts/bindings/clock/xhsc,hc32-clock-xtal32.yaml b/dts/bindings/clock/xhsc,hc32-clock-xtal32.yaml new file mode 100644 index 0000000000000..700416d733017 --- /dev/null +++ b/dts/bindings/clock/xhsc,hc32-clock-xtal32.yaml @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 XTAL32 Clock + +compatible: "xhsc,hc32-clock-xtal32" + +include: [fixed-clock.yaml] + +properties: + drive-strength: + type: int + required: true + enum: + - 0 # Medium drive strength, equals to DDL macro CLK_XTAL32_DRV_MID + - 1 # High drive strength, equals to DDL macro CLK_XTAL32_DRV_HIGH + description: | + Configure the driving current of the external low-speed crystal + based on varying capacitances. diff --git a/dts/bindings/flash_controller/xhsc,hc32-flash-controller.yaml b/dts/bindings/flash_controller/xhsc,hc32-flash-controller.yaml new file mode 100644 index 0000000000000..f3b93709cdc5c --- /dev/null +++ b/dts/bindings/flash_controller/xhsc,hc32-flash-controller.yaml @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: HC32 F4 flash controller + +compatible: "xhsc,hc32-flash-controller" + +include: flash-controller.yaml diff --git a/dts/bindings/gpio/xhsc,hc32-gpio.yaml b/dts/bindings/gpio/xhsc,hc32-gpio.yaml new file mode 100644 index 0000000000000..a421fd778c5c7 --- /dev/null +++ b/dts/bindings/gpio/xhsc,hc32-gpio.yaml @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: XHSC HC32 GPIO + +compatible: "xhsc,hc32-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#gpio-cells": + const: 2 + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/interrupt-controller/xhsc,hc32-extint.yaml b/dts/bindings/interrupt-controller/xhsc,hc32-extint.yaml new file mode 100644 index 0000000000000..9a0c72e07340f --- /dev/null +++ b/dts/bindings/interrupt-controller/xhsc,hc32-extint.yaml @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: XHSC HC32 family Interrupt Controller + +compatible: "xhsc,hc32-extint" + +include: [base.yaml] + +properties: + extint-nums: + type: int + required: true + description: Number of extint supported by the interrupt controller. + + extint-chs: + type: array + required: true + description: Description of the external channel for each interrupt vector. diff --git a/dts/bindings/interrupt-controller/xhsc,hc32-intc.yaml b/dts/bindings/interrupt-controller/xhsc,hc32-intc.yaml new file mode 100644 index 0000000000000..7700e288ec079 --- /dev/null +++ b/dts/bindings/interrupt-controller/xhsc,hc32-intc.yaml @@ -0,0 +1,20 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: XHSC HC32 family Interrupt Controller + +compatible: "xhsc,hc32-intc" + +include: [base.yaml, interrupt-controller.yaml] + +properties: + reg: + required: true + + "#interrupt-cells": + const: 3 + +interrupt-cells: + - irq + - priority + - int_src diff --git a/dts/bindings/pinctrl/xhsc,hc32-pinctrl.yaml b/dts/bindings/pinctrl/xhsc,hc32-pinctrl.yaml new file mode 100644 index 0000000000000..f088c4a5db84a --- /dev/null +++ b/dts/bindings/pinctrl/xhsc,hc32-pinctrl.yaml @@ -0,0 +1,57 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +title: XHSC HC32 Pinctrl + +description: | + Based on pincfg-node.yaml binding. + + Note: `bias-disable` and `drive-push-pull` are default pin configurations. + They will be applied in case no `bias-foo` or `driver-bar` properties + are set. + +compatible: "xhsc,hc32-pinctrl" +include: base.yaml + +child-binding: + description: | + hc32 pin controller pin configuration state nodes. + child-binding: + description: + hc32 pin controller pin configuration group. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-up + - drive-push-pull + - drive-open-drain + - input-enable + - output-enable + - output-high + - output-low + - input-schmitt-enable + - input-schmitt-disable + + properties: + pinmux: + required: true + type: array + description: | + Each array element represents pin muxing information of an individual + pin. + + drive-strength: + type: string + default: "low" + enum: + - "low" + - "medium" + - "high" + description: | + Pin output drive strength. + 0 (low) - sets pin to low drive strength, default set. + 1 (medium) - sets pin to medium drive strength + 2 (high) - sets pin to high drive strength + Default is "low" because it is the reset value. diff --git a/dts/bindings/serial/xhsc,hc32-uart.yaml b/dts/bindings/serial/xhsc,hc32-uart.yaml new file mode 100644 index 0000000000000..2743c96b0ab92 --- /dev/null +++ b/dts/bindings/serial/xhsc,hc32-uart.yaml @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +compatible: "xhsc,hc32-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + clocks: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index db92063114842..cb3ba6bc899ce 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -771,6 +771,7 @@ wurth Wurth Elektronik x-powers X-Powers xen Xen Hypervisor xes Extreme Engineering Solutions (X-ES) +xhsc Xiaohua Semiconductor Co., Ltd. xiaomi Xiaomi Technology Co., Ltd. xillybus Xillybus Ltd. xingbangda Shenzhen Xingbangda Display Technology Co., Ltd diff --git a/include/zephyr/drivers/clock_control/hc32_clock_control.h b/include/zephyr/drivers/clock_control/hc32_clock_control.h new file mode 100644 index 0000000000000..dc0b0c5286d15 --- /dev/null +++ b/include/zephyr/drivers/clock_control/hc32_clock_control.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_HC32_CLOCK_CONTROL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_HC32_CLOCK_CONTROL_H_ + +#include "soc.h" +#include +#if defined(HC32F460) +#include +#elif defined(HC32F4A0) +#include +#endif + +#define HC32_HCLK_DIV_FN(v) CLK_HCLK_DIV##v +#define HC32_HCLK_DIV(v) HC32_HCLK_DIV_FN(v) +#define HC32_EXCLK_DIV_FN(v) CLK_EXCLK_DIV##v +#define HC32_EXCLK_DIV(v) HC32_EXCLK_DIV_FN(v) +#define HC32_PCLK_FN(n, v) CLK_PCLK##n##_DIV##v +#define HC32_PCLK(n, v) HC32_PCLK_FN(n, v) + +#define HC32_CLK_MODULES_BIT(bit) (1UL << (bit)) +#define HC32_CLK_MODULES_OFFSET(n) (4 * n) + +#define HC32_CLOCK_CONTROL_NODE DT_NODELABEL(clk_sys) +#define HC32_CLOCK_SYSTEM_NODE DT_NODELABEL(clocks) + +#define HC32_HCLK_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_hclk) +#define HC32_EXCLK_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_exclk) +#define HC32_PCLK0_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_pclk0) +#define HC32_PCLK1_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_pclk1) +#define HC32_PCLK2_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_pclk2) +#define HC32_PCLK3_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_pclk3) +#define HC32_PCLK4_PRESCALER DT_PROP(DT_NODELABEL(clk_sys), div_pclk4) + +#define SYS_CLK_FREQ DT_PROP(DT_CLOCKS_CTLR(DT_NODELABEL(clk_sys)), clock_frequency) +#define CORE_CLK_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_hclk) +#if (CORE_CLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) +#error "please confirm current cpu clock" +#endif +#define PCLK0_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_pclk0) +#define PCLK1_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_pclk1) +#define PCLK2_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_pclk2) +#define PCLK3_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_pclk3) +#define PCLK4_FREQ SYS_CLK_FREQ / DT_PROP(DT_NODELABEL(clk_sys), div_pclk4) + +#define DT_HC32_CLOCKS_CTLR DT_CLOCKS_CTLR(DT_NODELABEL(clk_sys)) +#if DT_SAME_NODE(DT_HC32_CLOCKS_CTLR, DT_NODELABEL(clk_pll)) +#define HC32_SYSCLK_SRC_PLL 1 +#elif DT_SAME_NODE(DT_HC32_CLOCKS_CTLR, DT_NODELABEL(clk_xtal)) +#define HC32_SYSCLK_SRC_XTAL 1 +#elif DT_SAME_NODE(DT_HC32_CLOCKS_CTLR, DT_NODELABEL(clk_hrc)) +#define HC32_SYSCLK_SRC_HRC 1 +#elif DT_SAME_NODE(DT_HC32_CLOCKS_CTLR, DT_NODELABEL(clk_mrc)) +#define HC32_SYSCLK_SRC_MRC 1 +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_pll), xhsc_hc32_clock_pll, okay) && \ + DT_NODE_HAS_PROP(DT_NODELABEL(clk_pll), clocks) +#if DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(clk_pll)), DT_NODELABEL(clk_xtal)) +#define HC32_PLL_SRC_XTAL 1 +#else +#define HC32_PLL_SRC_HRC 1 +#endif +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_pll), xhsc_hc32_clock_pll, okay) +#define HC32_PLL_ENABLED 1 +#define HC32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(clk_pll), div_m) +#define HC32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(clk_pll), mul_n) +#define HC32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(clk_pll), div_p) +#define HC32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(clk_pll), div_p, 1) +#define HC32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(clk_pll), div_q) +#define HC32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(clk_pll), div_q, 1) +#define HC32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(clk_pll), div_r) +#define HC32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(clk_pll), div_r, 1) +#define HC32_PLL_FREQ DT_PROP(DT_NODELABEL(clk_pll), clock_frequency) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_xtal), fixed_clock, okay) +#define HC32_XTAL_ENABLED 1 +#define HC32_XTAL_FREQ DT_PROP(DT_NODELABEL(clk_xtal), clock_frequency) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_xtal32), fixed_clock, okay) +#define HC32_XTAL32_ENABLED 1 +#define HC32_XTAL32_FREQ DT_PROP(DT_NODELABEL(clk_xtal32), clock_frequency) +#define HC32_XTAL32_DRV DT_PROP(DT_NODELABEL(clk_xtal32), drive_strength) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hrc), fixed_clock, okay) +#define HC32_HRC_ENABLED 1 +#define HC32_HRC_FREQ DT_PROP(DT_NODELABEL(clk_hrc), clock_frequency) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_mrc), fixed_clock, okay) +#define HC32_MRC_ENABLED 1 +#define HC32_MRC_FREQ DT_PROP(DT_NODELABEL(clk_mrc), clock_frequency) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lrc), fixed_clock, okay) +#define HC32_LRC_ENABLED 1 +#define HC32_LRC_FREQ DT_PROP(DT_NODELABEL(clk_lrc), clock_frequency) +#endif + +#define HC32_MODULES_CLOCK_INFO(clk_index, node_id) \ + {.bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus), \ + .fcg = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, fcg), \ + .bits = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits)} + +#define HC32_MODULES_CLOCKS(node_id) \ + {LISTIFY(DT_NUM_CLOCKS(node_id), HC32_MODULES_CLOCK_INFO, (,), node_id) } + +struct hc32_modules_clock_sys { + uint32_t bus; + uint32_t fcg; + uint32_t bits; +}; +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_HC32_CLOCK_CONTROL_H_ */ diff --git a/include/zephyr/drivers/interrupt_controller/intc_extint_hc32.h b/include/zephyr/drivers/interrupt_controller/intc_extint_hc32.h new file mode 100644 index 0000000000000..324aef4a2d305 --- /dev/null +++ b/include/zephyr/drivers/interrupt_controller/intc_extint_hc32.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Driver for external interrupt/event controller in HC32 MCUs + */ + +#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_EXTINT_HC32_H_ +#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_EXTINT_HC32_H_ + +#include + +/** + * @brief external trigger flags + */ +enum hc32_extint_trigger { + HC32_EXTINT_TRIG_FALLING = 0x0, /* trigger on falling edge */ + HC32_EXTINT_TRIG_RISING = 0x1, /* trigger on rising edge */ + HC32_EXTINT_TRIG_BOTH = 0x2, /* trigger on falling edge */ + HC32_EXTINT_TRIG_LOW_LVL = 0x3, /* trigger on low level */ + HC32_EXTINT_TRIG_NOT_SUPPT, /* trigger not supported */ +}; + +/* callback for exti interrupt */ +typedef void (*hc32_extint_callback_t)(int pin, void *user); + +typedef void (*hc32_extint_enable_t)(const struct device *dev, int port, int pin); +typedef void (*hc32_extint_disable_t)(const struct device *dev, int port, int pin); +typedef void (*hc32_extint_trigger_t)(const struct device *dev, int pin, int trigger); +typedef int (*hc32_extint_set_callback_t)(const struct device *dev, int pin, + hc32_extint_callback_t cb, void *user); +typedef void (*hc32_extint_unset_callback_t)(const struct device *dev, int pin); + +struct hc32_extint_driver_api { + hc32_extint_enable_t extint_enable; + hc32_extint_disable_t extint_disable; + hc32_extint_trigger_t extint_set_trigger; + hc32_extint_set_callback_t extint_set_cb; + hc32_extint_unset_callback_t extint_unset_cb; +}; + +#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_EXTINT_HC32_H_ */ diff --git a/include/zephyr/drivers/interrupt_controller/intc_hc32.h b/include/zephyr/drivers/interrupt_controller/intc_hc32.h new file mode 100644 index 0000000000000..bfc84bdf6f5b7 --- /dev/null +++ b/include/zephyr/drivers/interrupt_controller/intc_hc32.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Driver for interrupt/event controller in HC32 MCUs + */ + +#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_HC32_H_ +#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_HC32_H_ + +#include + +/* intc config */ +int hc32_intc_irq_signin(int irqn, int intsrc); +int hc32_intc_irq_signout(int irqn); + +#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_HC32_H_ */ diff --git a/include/zephyr/dt-bindings/clock/hc32f4_common_clock.h b/include/zephyr/dt-bindings/clock/hc32f4_common_clock.h new file mode 100644 index 0000000000000..426715c87baa1 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/hc32f4_common_clock.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4_COMMON_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4_COMMON_CLOCK_H_ + +#define HC32_CLK_FCG0 0 +#define HC32_CLK_FCG1 1 +#define HC32_CLK_FCG2 2 +#define HC32_CLK_FCG3 3 +#define HC32_CLK_FCG_AVALID 0xFF + +#define HC32_CLK_SRC_HRC (0x00) +#define HC32_CLK_SRC_MRC (0x01) +#define HC32_CLK_SRC_LRC (0x02) +#define HC32_CLK_SRC_XTAL (0x03) +#define HC32_CLK_SRC_XTAL32 (0x04) +#define HC32_CLK_SRC_PLL (0x05) +#define HC32_CLK_BUS_HCLK (0x07) +#define HC32_CLK_BUS_PCLK0 (0x08) +#define HC32_CLK_BUS_PCLK1 (0x09) +#define HC32_CLK_BUS_PCLK2 (0x0A) +#define HC32_CLK_BUS_PCLK3 (0x0B) +#define HC32_CLK_BUS_PCLK4 (0x0C) +#define HC32_SYS_CLK (0x0D) + +#define HC32_CLK_CONF_PERI (0) +#define HC32_CLK_CONF_TPIU (1) +#define HC32_CLK_CONF_SRC (2) +#define HC32_CLK_CONF_MCO (3) +#define HC32_CLK_CONF_MIN HC32_CLK_CONF_PERI +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4_COMMON_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/hc32f4a0_clock.h b/include/zephyr/dt-bindings/clock/hc32f4a0_clock.h new file mode 100644 index 0000000000000..184961f3c191f --- /dev/null +++ b/include/zephyr/dt-bindings/clock/hc32f4a0_clock.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4A0_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4A0_CLOCK_H_ + +#include "hc32f4_common_clock.h" + +#define HC32_FCG0_PERIPH_SRAMH 0 +#define HC32_FCG0_PERIPH_SRAM1 4 +#define HC32_FCG0_PERIPH_SRAM2 5 +#define HC32_FCG0_PERIPH_SRAM3 6 +#define HC32_FCG0_PERIPH_SRAM4 7 +#define HC32_FCG0_PERIPH_SRAMB 10 +#define HC32_FCG0_PERIPH_KEY 13 +#define HC32_FCG0_PERIPH_DMA1 14 +#define HC32_FCG0_PERIPH_DMA2 15 +#define HC32_FCG0_PERIPH_FCM 16 +#define HC32_FCG0_PERIPH_AOS 17 +#define HC32_FCG0_PERIPH_CTC 18 +#define HC32_FCG0_PERIPH_MAU 19 +#define HC32_FCG0_PERIPH_AES 20 +#define HC32_FCG0_PERIPH_HASH 21 +#define HC32_FCG0_PERIPH_TRNG 22 +#define HC32_FCG0_PERIPH_CRC 23 +#define HC32_FCG0_PERIPH_DCU1 24 +#define HC32_FCG0_PERIPH_DCU2 25 +#define HC32_FCG0_PERIPH_DCU3 26 +#define HC32_FCG0_PERIPH_DCU4 27 +#define HC32_FCG0_PERIPH_DCU5 28 +#define HC32_FCG0_PERIPH_DCU6 29 +#define HC32_FCG0_PERIPH_DCU7 30 +#define HC32_FCG0_PERIPH_DCU8 31 + +#define HC32_FCG1_PERIPH_CAN1 0 +#define HC32_FCG1_PERIPH_CAN2 1 +#define HC32_FCG1_PERIPH_ETHMAC 2 +#define HC32_FCG1_PERIPH_QSPI 3 +#define HC32_FCG1_PERIPH_I2C1 4 +#define HC32_FCG1_PERIPH_I2C2 5 +#define HC32_FCG1_PERIPH_I2C3 6 +#define HC32_FCG1_PERIPH_I2C4 7 +#define HC32_FCG1_PERIPH_I2C5 8 +#define HC32_FCG1_PERIPH_I2C6 9 +#define HC32_FCG1_PERIPH_SDIOC1 10 +#define HC32_FCG1_PERIPH_SDIOC2 11 +#define HC32_FCG1_PERIPH_I2S1 12 +#define HC32_FCG1_PERIPH_I2S2 13 +#define HC32_FCG1_PERIPH_I2S3 14 +#define HC32_FCG1_PERIPH_I2S4 15 +#define HC32_FCG1_PERIPH_SPI1 16 +#define HC32_FCG1_PERIPH_SPI2 17 +#define HC32_FCG1_PERIPH_SPI3 18 +#define HC32_FCG1_PERIPH_SPI4 19 +#define HC32_FCG1_PERIPH_SPI5 20 +#define HC32_FCG1_PERIPH_SPI6 21 +#define HC32_FCG1_PERIPH_USBFS 22 +#define HC32_FCG1_PERIPH_USBHS 23 +#define HC32_FCG1_PERIPH_FMAC1 24 +#define HC32_FCG1_PERIPH_FMAC2 25 +#define HC32_FCG1_PERIPH_FMAC3 26 +#define HC32_FCG1_PERIPH_FMAC4 27 + +#define HC32_FCG2_PERIPH_TMR6_1 0 +#define HC32_FCG2_PERIPH_TMR6_2 1 +#define HC32_FCG2_PERIPH_TMR6_3 2 +#define HC32_FCG2_PERIPH_TMR6_4 3 +#define HC32_FCG2_PERIPH_TMR6_5 4 +#define HC32_FCG2_PERIPH_TMR6_6 5 +#define HC32_FCG2_PERIPH_TMR6_7 6 +#define HC32_FCG2_PERIPH_TMR6_8 7 +#define HC32_FCG2_PERIPH_TMR4_1 8 +#define HC32_FCG2_PERIPH_TMR4_2 9 +#define HC32_FCG2_PERIPH_TMR4_3 10 +#define HC32_FCG2_PERIPH_HRPWM 11 +#define HC32_FCG2_PERIPH_TMR0_1 12 +#define HC32_FCG2_PERIPH_TMR0_2 13 +#define HC32_FCG2_PERIPH_EMB 15 +#define HC32_FCG2_PERIPH_TMR2_1 16 +#define HC32_FCG2_PERIPH_TMR2_2 17 +#define HC32_FCG2_PERIPH_TMR2_3 18 +#define HC32_FCG2_PERIPH_TMR2_4 19 +#define HC32_FCG2_PERIPH_TMRA_1 20 +#define HC32_FCG2_PERIPH_TMRA_2 21 +#define HC32_FCG2_PERIPH_TMRA_3 22 +#define HC32_FCG2_PERIPH_TMRA_4 23 +#define HC32_FCG2_PERIPH_TMRA_5 24 +#define HC32_FCG2_PERIPH_TMRA_6 25 +#define HC32_FCG2_PERIPH_TMRA_7 26 +#define HC32_FCG2_PERIPH_TMRA_8 27 +#define HC32_FCG2_PERIPH_TMRA_9 28 +#define HC32_FCG2_PERIPH_TMRA_10 29 +#define HC32_FCG2_PERIPH_TMRA_11 30 +#define HC32_FCG2_PERIPH_TMRA_12 31 + +#define HC32_FCG3_PERIPH_ADC1 0 +#define HC32_FCG3_PERIPH_ADC2 1 +#define HC32_FCG3_PERIPH_ADC3 2 +#define HC32_FCG3_PERIPH_CMBIAS 3 +#define HC32_FCG3_PERIPH_DAC1 4 +#define HC32_FCG3_PERIPH_DAC2 5 +#define HC32_FCG3_PERIPH_CMP12 8 +#define HC32_FCG3_PERIPH_CMP34 9 +#define HC32_FCG3_PERIPH_OTS 12 +#define HC32_FCG3_PERIPH_DVP 15 +#define HC32_FCG3_PERIPH_EXMC_SMC 16 +#define HC32_FCG3_PERIPH_EXMC_DMC 17 +#define HC32_FCG3_PERIPH_EXMC_NMC 18 +#define HC32_FCG3_PERIPH_USART1 20 +#define HC32_FCG3_PERIPH_USART2 21 +#define HC32_FCG3_PERIPH_USART3 22 +#define HC32_FCG3_PERIPH_USART4 23 +#define HC32_FCG3_PERIPH_USART5 24 +#define HC32_FCG3_PERIPH_USART6 25 +#define HC32_FCG3_PERIPH_USART7 26 +#define HC32_FCG3_PERIPH_USART8 27 +#define HC32_FCG3_PERIPH_USART9 28 +#define HC32_FCG3_PERIPH_USART10 29 + +#define HC32_CLK_CONF_USB (4) +#define HC32_CLK_CONF_I2S (5) +#define HC32_CLK_CONF_CAN (6) +#define HC32_CLK_CONF_MAX HC32_CLK_CONF_CAN +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_HC32F4A0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-int-evt.h b/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-int-evt.h new file mode 100644 index 0000000000000..89e581dcb03e6 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-int-evt.h @@ -0,0 +1,1168 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INT_EVT_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INT_EVT_H_ + +/** + * @brief Interrupt Vector Number + */ +#define NonMaskableInt_IRQn -14 /* Non Maskable */ +#define HardFault_IRQn -13 /* Hard Fault */ +#define MemoryManagement_IRQn -12 /* MemManage Fault */ +#define BusFault_IRQn -11 /* Bus Fault */ +#define UsageFault_IRQn -10 /* Usage Fault */ +#define SVCall_IRQn -5 /* SVCall */ +#define DebugMonitor_IRQn -4 /* DebugMonitor */ +#define PendSV_IRQn -2 /* Pend SV */ +#define SysTick_IRQn -1 /* System Tick */ +#define INT000_IRQn 0 +#define INT001_IRQn 1 +#define INT002_IRQn 2 +#define INT003_IRQn 3 +#define INT004_IRQn 4 +#define INT005_IRQn 5 +#define INT006_IRQn 6 +#define INT007_IRQn 7 +#define INT008_IRQn 8 +#define INT009_IRQn 9 +#define INT010_IRQn 10 +#define INT011_IRQn 11 +#define INT012_IRQn 12 +#define INT013_IRQn 13 +#define INT014_IRQn 14 +#define INT015_IRQn 15 +#define INT016_IRQn 16 +#define INT017_IRQn 17 +#define INT018_IRQn 18 +#define INT019_IRQn 19 +#define INT020_IRQn 20 +#define INT021_IRQn 21 +#define INT022_IRQn 22 +#define INT023_IRQn 23 +#define INT024_IRQn 24 +#define INT025_IRQn 25 +#define INT026_IRQn 26 +#define INT027_IRQn 27 +#define INT028_IRQn 28 +#define INT029_IRQn 29 +#define INT030_IRQn 30 +#define INT031_IRQn 31 +#define INT032_IRQn 32 +#define INT033_IRQn 33 +#define INT034_IRQn 34 +#define INT035_IRQn 35 +#define INT036_IRQn 36 +#define INT037_IRQn 37 +#define INT038_IRQn 38 +#define INT039_IRQn 39 +#define INT040_IRQn 40 +#define INT041_IRQn 41 +#define INT042_IRQn 42 +#define INT043_IRQn 43 +#define INT044_IRQn 44 +#define INT045_IRQn 45 +#define INT046_IRQn 46 +#define INT047_IRQn 47 +#define INT048_IRQn 48 +#define INT049_IRQn 49 +#define INT050_IRQn 50 +#define INT051_IRQn 51 +#define INT052_IRQn 52 +#define INT053_IRQn 53 +#define INT054_IRQn 54 +#define INT055_IRQn 55 +#define INT056_IRQn 56 +#define INT057_IRQn 57 +#define INT058_IRQn 58 +#define INT059_IRQn 59 +#define INT060_IRQn 60 +#define INT061_IRQn 61 +#define INT062_IRQn 62 +#define INT063_IRQn 63 +#define INT064_IRQn 64 +#define INT065_IRQn 65 +#define INT066_IRQn 66 +#define INT067_IRQn 67 +#define INT068_IRQn 68 +#define INT069_IRQn 69 +#define INT070_IRQn 70 +#define INT071_IRQn 71 +#define INT072_IRQn 72 +#define INT073_IRQn 73 +#define INT074_IRQn 74 +#define INT075_IRQn 75 +#define INT076_IRQn 76 +#define INT077_IRQn 77 +#define INT078_IRQn 78 +#define INT079_IRQn 79 +#define INT080_IRQn 80 +#define INT081_IRQn 81 +#define INT082_IRQn 82 +#define INT083_IRQn 83 +#define INT084_IRQn 84 +#define INT085_IRQn 85 +#define INT086_IRQn 86 +#define INT087_IRQn 87 +#define INT088_IRQn 88 +#define INT089_IRQn 89 +#define INT090_IRQn 90 +#define INT091_IRQn 91 +#define INT092_IRQn 92 +#define INT093_IRQn 93 +#define INT094_IRQn 94 +#define INT095_IRQn 95 +#define INT096_IRQn 96 +#define INT097_IRQn 97 +#define INT098_IRQn 98 +#define INT099_IRQn 99 +#define INT100_IRQn 100 +#define INT101_IRQn 101 +#define INT102_IRQn 102 +#define INT103_IRQn 103 +#define INT104_IRQn 104 +#define INT105_IRQn 105 +#define INT106_IRQn 106 +#define INT107_IRQn 107 +#define INT108_IRQn 108 +#define INT109_IRQn 109 +#define INT110_IRQn 110 +#define INT111_IRQn 111 +#define INT112_IRQn 112 +#define INT113_IRQn 113 +#define INT114_IRQn 114 +#define INT115_IRQn 115 +#define INT116_IRQn 116 +#define INT117_IRQn 117 +#define INT118_IRQn 118 +#define INT119_IRQn 119 +#define INT120_IRQn 120 +#define INT121_IRQn 121 +#define INT122_IRQn 122 +#define INT123_IRQn 123 +#define INT124_IRQn 124 +#define INT125_IRQn 125 +#define INT126_IRQn 126 +#define INT127_IRQn 127 +#define INT128_IRQn 128 +#define INT129_IRQn 129 +#define INT130_IRQn 130 +#define INT131_IRQn 131 +#define INT132_IRQn 132 +#define INT133_IRQn 133 +#define INT134_IRQn 134 +#define INT135_IRQn 135 +#define INT136_IRQn 136 +#define INT137_IRQn 137 +#define INT138_IRQn 138 +#define INT139_IRQn 139 +#define INT140_IRQn 140 +#define INT141_IRQn 141 +#define INT142_IRQn 142 +#define INT143_IRQn 143 + +/** + * @brief Interrupt Priority Level + */ +#define DDL_IRQ_PRIO_00 (0U) +#define DDL_IRQ_PRIO_01 (1U) +#define DDL_IRQ_PRIO_02 (2U) +#define DDL_IRQ_PRIO_03 (3U) +#define DDL_IRQ_PRIO_04 (4U) +#define DDL_IRQ_PRIO_05 (5U) +#define DDL_IRQ_PRIO_06 (6U) +#define DDL_IRQ_PRIO_07 (7U) +#define DDL_IRQ_PRIO_08 (8U) +#define DDL_IRQ_PRIO_09 (9U) +#define DDL_IRQ_PRIO_10 (10U) +#define DDL_IRQ_PRIO_11 (11U) +#define DDL_IRQ_PRIO_12 (12U) +#define DDL_IRQ_PRIO_13 (13U) +#define DDL_IRQ_PRIO_14 (14U) +/* kernal used */ +/* #define DDL_IRQ_PRIO_15 (15U) */ + +#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_10) + +/** + * @brief Interrupt Source Number + */ +#define INT_SRC_SWI_IRQ0 0U /* SWI_IRQ0 */ +#define INT_SRC_SWI_IRQ1 1U /* SWI_IRQ1 */ +#define INT_SRC_SWI_IRQ2 2U /* SWI_IRQ2 */ +#define INT_SRC_SWI_IRQ3 3U /* SWI_IRQ3 */ +#define INT_SRC_SWI_IRQ4 4U /* SWI_IRQ4 */ +#define INT_SRC_SWI_IRQ5 5U /* SWI_IRQ5 */ +#define INT_SRC_SWI_IRQ6 6U /* SWI_IRQ6 */ +#define INT_SRC_SWI_IRQ7 7U /* SWI_IRQ7 */ +#define INT_SRC_SWI_IRQ8 8U /* SWI_IRQ8 */ +#define INT_SRC_SWI_IRQ9 9U /* SWI_IRQ9 */ +#define INT_SRC_SWI_IRQ10 10U /* SWI_IRQ10 */ +#define INT_SRC_SWI_IRQ11 11U /* SWI_IRQ11 */ +#define INT_SRC_SWI_IRQ12 12U /* SWI_IRQ12 */ +#define INT_SRC_SWI_IRQ13 13U /* SWI_IRQ13 */ +#define INT_SRC_SWI_IRQ14 14U /* SWI_IRQ14 */ +#define INT_SRC_SWI_IRQ15 15U /* SWI_IRQ15 */ +#define INT_SRC_SWI_IRQ16 16U /* SWI_IRQ16 */ +#define INT_SRC_SWI_IRQ17 17U /* SWI_IRQ17 */ +#define INT_SRC_SWI_IRQ18 18U /* SWI_IRQ18 */ +#define INT_SRC_SWI_IRQ19 19U /* SWI_IRQ19 */ +#define INT_SRC_SWI_IRQ20 20U /* SWI_IRQ20 */ +#define INT_SRC_SWI_IRQ21 21U /* SWI_IRQ21 */ +#define INT_SRC_SWI_IRQ22 22U /* SWI_IRQ22 */ +#define INT_SRC_SWI_IRQ23 23U /* SWI_IRQ23 */ +#define INT_SRC_SWI_IRQ24 24U /* SWI_IRQ24 */ +#define INT_SRC_SWI_IRQ25 25U /* SWI_IRQ25 */ +#define INT_SRC_SWI_IRQ26 26U /* SWI_IRQ26 */ +#define INT_SRC_SWI_IRQ27 27U /* SWI_IRQ27 */ +#define INT_SRC_SWI_IRQ28 28U /* SWI_IRQ28 */ +#define INT_SRC_SWI_IRQ29 29U /* SWI_IRQ29 */ +#define INT_SRC_SWI_IRQ30 30U /* SWI_IRQ30 */ +#define INT_SRC_SWI_IRQ31 31U /* SWI_IRQ31 */ + +/* External Interrupt. */ +#define INT_SRC_PORT_EIRQ0 0U /* PORT_EIRQ0 */ +#define INT_SRC_PORT_EIRQ1 1U /* PORT_EIRQ1 */ +#define INT_SRC_PORT_EIRQ2 2U /* PORT_EIRQ2 */ +#define INT_SRC_PORT_EIRQ3 3U /* PORT_EIRQ3 */ +#define INT_SRC_PORT_EIRQ4 4U /* PORT_EIRQ4 */ +#define INT_SRC_PORT_EIRQ5 5U /* PORT_EIRQ5 */ +#define INT_SRC_PORT_EIRQ6 6U /* PORT_EIRQ6 */ +#define INT_SRC_PORT_EIRQ7 7U /* PORT_EIRQ7 */ +#define INT_SRC_PORT_EIRQ8 8U /* PORT_EIRQ8 */ +#define INT_SRC_PORT_EIRQ9 9U /* PORT_EIRQ9 */ +#define INT_SRC_PORT_EIRQ10 10U /* PORT_EIRQ10 */ +#define INT_SRC_PORT_EIRQ11 11U /* PORT_EIRQ11 */ +#define INT_SRC_PORT_EIRQ12 12U /* PORT_EIRQ12 */ +#define INT_SRC_PORT_EIRQ13 13U /* PORT_EIRQ13 */ +#define INT_SRC_PORT_EIRQ14 14U /* PORT_EIRQ14 */ +#define INT_SRC_PORT_EIRQ15 15U /* PORT_EIRQ15 */ + +/* DMA_1 */ +#define INT_SRC_DMA1_TC0 32U /* DMA_1_TC0 */ +#define INT_SRC_DMA1_TC1 33U /* DMA_1_TC1 */ +#define INT_SRC_DMA1_TC2 34U /* DMA_1_TC2 */ +#define INT_SRC_DMA1_TC3 35U /* DMA_1_TC3 */ +#define INT_SRC_DMA1_TC4 36U /* DMA_1_TC4 */ +#define INT_SRC_DMA1_TC5 37U /* DMA_1_TC5 */ +#define INT_SRC_DMA1_TC6 38U /* DMA_1_TC6 */ +#define INT_SRC_DMA1_TC7 39U /* DMA_1_TC7 */ +#define INT_SRC_DMA1_BTC0 40U /* DMA_1_BTC0 */ +#define INT_SRC_DMA1_BTC1 41U /* DMA_1_BTC1 */ +#define INT_SRC_DMA1_BTC2 42U /* DMA_1_BTC2 */ +#define INT_SRC_DMA1_BTC3 43U /* DMA_1_BTC3 */ +#define INT_SRC_DMA1_BTC4 44U /* DMA_1_BTC4 */ +#define INT_SRC_DMA1_BTC5 45U /* DMA_1_BTC5 */ +#define INT_SRC_DMA1_BTC6 46U /* DMA_1_BTC6 */ +#define INT_SRC_DMA1_BTC7 47U /* DMA_1_BTC7 */ +#define INT_SRC_DMA1_ERR 48U /* DMA_1_ERR */ +/* EFM */ +#define INT_SRC_EFM_PEERR 49U /* EFM_PEERR */ +#define INT_SRC_EFM_RDCOL 50U /* EFM_RDCOL */ +#define INT_SRC_EFM_OPTEND 51U /* EFM_OPTEND */ +/* QSPI */ +#define INT_SRC_QSPI_INTR 54U /* QSPI_INTR */ +/* DCU */ +#define INT_SRC_DCU1 55U /* DCU1 */ +#define INT_SRC_DCU2 56U /* DCU2 */ +#define INT_SRC_DCU3 57U /* DCU3 */ +#define INT_SRC_DCU4 58U /* DCU4 */ +#define INT_SRC_DCU5 59U /* DCU5 */ +#define INT_SRC_DCU6 60U /* DCU6 */ +#define INT_SRC_DCU7 61U /* DCU7 */ +#define INT_SRC_DCU8 62U /* DCU8 */ +/* DMA2 */ +#define INT_SRC_DMA2_TC0 64U /* DMA_2_TC0 */ +#define INT_SRC_DMA2_TC1 65U /* DMA_2_TC1 */ +#define INT_SRC_DMA2_TC2 66U /* DMA_2_TC2 */ +#define INT_SRC_DMA2_TC3 67U /* DMA_2_TC3 */ +#define INT_SRC_DMA2_TC4 68U /* DMA_2_TC4 */ +#define INT_SRC_DMA2_TC5 69U /* DMA_2_TC5 */ +#define INT_SRC_DMA2_TC6 70U /* DMA_2_TC6 */ +#define INT_SRC_DMA2_TC7 71U /* DMA_2_TC7 */ +#define INT_SRC_DMA2_BTC0 72U /* DMA_2_BTC0 */ +#define INT_SRC_DMA2_BTC1 73U /* DMA_2_BTC1 */ +#define INT_SRC_DMA2_BTC2 74U /* DMA_2_BTC2 */ +#define INT_SRC_DMA2_BTC3 75U /* DMA_2_BTC3 */ +#define INT_SRC_DMA2_BTC4 76U /* DMA_2_BTC4 */ +#define INT_SRC_DMA2_BTC5 77U /* DMA_2_BTC5 */ +#define INT_SRC_DMA2_BTC6 78U /* DMA_2_BTC6 */ +#define INT_SRC_DMA2_BTC7 79U /* DMA_2_BTC7 */ +#define INT_SRC_DMA2_ERR 80U /* DMA_2_ERR */ +/* MAU */ +#define INT_SRC_MAU_SQRT 83U /* MAU_SQRT */ +/* DVP */ +#define INT_SRC_DVP_FRAMSTA 84U /* DVP_FRAMSTA */ +#define INT_SRC_DVP_LINESTA 85U /* DVP_LINESTA */ +#define INT_SRC_DVP_LINEEND 86U /* DVP_LINEEND */ +#define INT_SRC_DVP_FRAMEND 87U /* DVP_FRAMEND */ +#define INT_SRC_DVP_SQUERR 88U /* DVP_SQUERR */ +#define INT_SRC_DVP_FIFOERR 89U /* DVP_FIFOERR */ +/* FMAC */ +#define INT_SRC_FMAC_1 91U /* FMAC_1_FIR */ +#define INT_SRC_FMAC_2 92U /* FMAC_2_FIR */ +#define INT_SRC_FMAC_3 93U /* FMAC_3_FIR */ +#define INT_SRC_FMAC_4 94U /* FMAC_4_FIR */ +/* TIMER0 */ +#define INT_SRC_TMR0_1_CMP_A 96U /* TMR0_1_CMPA */ +#define INT_SRC_TMR0_1_CMP_B 97U /* TMR0_1_CMPB */ +#define INT_SRC_TMR0_2_CMP_A 98U /* TMR0_2_CMPA */ +#define INT_SRC_TMR0_2_CMP_B 99U /* TMR0_2_CMPB */ +/* TIMER2 */ +#define INT_SRC_TMR2_1_CMP_A 100U /* TMR2_1_CMPA */ +#define INT_SRC_TMR2_1_CMP_B 101U /* TMR2_1_CMPB */ +#define INT_SRC_TMR2_1_OVF_A 102U /* TMR2_1_OVFA */ +#define INT_SRC_TMR2_1_OVF_B 103U /* TMR2_1_OVFB */ +#define INT_SRC_TMR2_2_CMP_A 104U /* TMR2_2_CMPA */ +#define INT_SRC_TMR2_2_CMP_B 105U /* TMR2_2_CMPB */ +#define INT_SRC_TMR2_2_OVF_A 106U /* TMR2_2_OVFA */ +#define INT_SRC_TMR2_2_OVF_B 107U /* TMR2_2_OVFB */ +#define INT_SRC_TMR2_3_CMP_A 108U /* TMR2_3_CMPA */ +#define INT_SRC_TMR2_3_CMP_B 109U /* TMR2_3_CMPB */ +#define INT_SRC_TMR2_3_OVF_A 110U /* TMR2_3_OVFA */ +#define INT_SRC_TMR2_3_OVF_B 111U /* TMR2_3_OVFB */ +#define INT_SRC_TMR2_4_CMP_A 112U /* TMR2_4_CMPA */ +#define INT_SRC_TMR2_4_CMP_B 113U /* TMR2_4_CMPB */ +#define INT_SRC_TMR2_4_OVF_A 114U /* TMR2_4_OVFA */ +#define INT_SRC_TMR2_4_OVF_B 115U /* TMR2_4_OVFB */ +/* RTC */ +#define INT_SRC_RTC_TP 120U /* RTC_TP */ +#define INT_SRC_RTC_ALM 121U /* RTC_ALM */ +#define INT_SRC_RTC_PRD 122U /* RTC_PRD */ +/* XTAL */ +#define INT_SRC_XTAL_STOP 125U /* XTAL_STOP */ +/* WKTM */ +#define INT_SRC_WKTM_PRD 126U /* WKTM_PRD */ +/* SWDT */ +#define INT_SRC_SWDT_REFUDF 127U /* SWDT_REFUDF */ +/* TIMER6_1 */ +#define INT_SRC_TMR6_1_GCMP_A 128U /* TMR6_1_GCMA */ +#define INT_SRC_TMR6_1_GCMP_B 129U /* TMR6_1_GCMB */ +#define INT_SRC_TMR6_1_GCMP_C 130U /* TMR6_1_GCMC */ +#define INT_SRC_TMR6_1_GCMP_D 131U /* TMR6_1_GCMD */ +#define INT_SRC_TMR6_1_GCMP_E 132U /* TMR6_1_GCME */ +#define INT_SRC_TMR6_1_GCMP_F 133U /* TMR6_1_GCMF */ +#define INT_SRC_TMR6_1_OVF 134U /* TMR6_1_GOVF */ +#define INT_SRC_TMR6_1_UDF 135U /* TMR6_1_GUDF */ +/* TIMER4_1 */ +#define INT_SRC_TMR4_1_GCMP_UH 136U /* TMR4_1_GCMUH */ +#define INT_SRC_TMR4_1_GCMP_UL 137U /* TMR4_1_GCMUL */ +#define INT_SRC_TMR4_1_GCMP_VH 138U /* TMR4_1_GCMVH */ +#define INT_SRC_TMR4_1_GCMP_VL 139U /* TMR4_1_GCMVL */ +#define INT_SRC_TMR4_1_GCMP_WH 140U /* TMR4_1_GCMWH */ +#define INT_SRC_TMR4_1_GCMP_WL 141U /* TMR4_1_GCMWL */ +#define INT_SRC_TMR4_1_OVF 142U /* TMR4_1_GOVF */ +#define INT_SRC_TMR4_1_UDF 143U /* TMR4_1_GUDF */ +/* TIMER6_2 */ +#define INT_SRC_TMR6_2_GCMP_A 144U /* TMR6_2_GCMA */ +#define INT_SRC_TMR6_2_GCMP_B 145U /* TMR6_2_GCMB */ +#define INT_SRC_TMR6_2_GCMP_C 146U /* TMR6_2_GCMC */ +#define INT_SRC_TMR6_2_GCMP_D 147U /* TMR6_2_GCMD */ +#define INT_SRC_TMR6_2_GCMP_E 148U /* TMR6_2_GCME */ +#define INT_SRC_TMR6_2_GCMP_F 149U /* TMR6_2_GCMF */ +#define INT_SRC_TMR6_2_OVF 150U /* TMR6_2_GOVF */ +#define INT_SRC_TMR6_2_UDF 151U /* TMR6_2_GUDF */ +/* TIMER4_2 */ +#define INT_SRC_TMR4_2_GCMP_UH 152U /* TMR4_2_GCMUH */ +#define INT_SRC_TMR4_2_GCMP_UL 153U /* TMR4_2_GCMUL */ +#define INT_SRC_TMR4_2_GCMP_VH 154U /* TMR4_2_GCMVH */ +#define INT_SRC_TMR4_2_GCMP_VL 155U /* TMR4_2_GCMVL */ +#define INT_SRC_TMR4_2_GCMP_WH 156U /* TMR4_2_GCMWH */ +#define INT_SRC_TMR4_2_GCMP_WL 157U /* TMR4_2_GCMWL */ +#define INT_SRC_TMR4_2_OVF 158U /* TMR4_2_GOVF */ +#define INT_SRC_TMR4_2_UDF 159U /* TMR4_2_GUDF */ +/* TIMER6_3 */ +#define INT_SRC_TMR6_3_GCMP_A 160U /* TMR6_3_GCMA */ +#define INT_SRC_TMR6_3_GCMP_B 161U /* TMR6_3_GCMB */ +#define INT_SRC_TMR6_3_GCMP_C 162U /* TMR6_3_GCMC */ +#define INT_SRC_TMR6_3_GCMP_D 163U /* TMR6_3_GCMD */ +#define INT_SRC_TMR6_3_GCMP_E 164U /* TMR6_3_GCME */ +#define INT_SRC_TMR6_3_GCMP_F 165U /* TMR6_3_GCMF */ +#define INT_SRC_TMR6_3_OVF 166U /* TMR6_3_GOVF */ +#define INT_SRC_TMR6_3_UDF 167U /* TMR6_3_GUDF */ +/* TIMER4_3 */ +#define INT_SRC_TMR4_3_GCMP_UH 168U /* TMR4_3_GCMUH */ +#define INT_SRC_TMR4_3_GCMP_UL 169U /* TMR4_3_GCMUL */ +#define INT_SRC_TMR4_3_GCMP_VH 170U /* TMR4_3_GCMVH */ +#define INT_SRC_TMR4_3_GCMP_VL 171U /* TMR4_3_GCMVL */ +#define INT_SRC_TMR4_3_GCMP_WH 172U /* TMR4_3_GCMWH */ +#define INT_SRC_TMR4_3_GCMP_WL 173U /* TMR4_3_GCMWL */ +#define INT_SRC_TMR4_3_OVF 174U /* TMR4_3_GOVF */ +#define INT_SRC_TMR4_3_UDF 175U /* TMR4_3_GUDF */ +/* TIMER6_1 */ +#define INT_SRC_TMR6_1_DTE 176U /* TMR6_1_GDTE */ +#define INT_SRC_TMR6_1_SCMP_A 179U /* TMR6_1_SCMA */ +#define INT_SRC_TMR6_1_SCMP_B 180U /* TMR6_1_SCMB */ +/* TIMER4_1 */ +#define INT_SRC_TMR4_1_RELOAD_U 181U /* TMR4_1_RLOU */ +#define INT_SRC_TMR4_1_RELOAD_V 182U /* TMR4_1_RLOV */ +#define INT_SRC_TMR4_1_RELOAD_W 183U /* TMR4_1_RLOW */ +/* TIMER6_2 */ +#define INT_SRC_TMR6_2_DTE 184U /* TMR6_2_GDTE */ +#define INT_SRC_TMR6_2_SCMP_A 187U /* TMR6_2_SCMA */ +#define INT_SRC_TMR6_2_SCMP_B 188U /* TMR6_2_SCMB */ +/* TIMER4_2 */ +#define INT_SRC_TMR4_2_RELOAD_U 189U /* TMR4_2_RLOU */ +#define INT_SRC_TMR4_2_RELOAD_V 190U /* TMR4_2_RLOV */ +#define INT_SRC_TMR4_2_RELOAD_W 191U /* TMR4_2_RLOW */ +/* TIMER6_3 */ +#define INT_SRC_TMR6_3_DTE 192U /* TMR6_3_GDTE */ +#define INT_SRC_TMR6_3_SCMP_A 195U /* TMR6_3_SCMA */ +#define INT_SRC_TMR6_3_SCMP_B 196U /* TMR6_3_SCMB */ +/* TIMER4_3 */ +#define INT_SRC_TMR4_3_RELOAD_U 197U /* TMR4_3_RLOU */ +#define INT_SRC_TMR4_3_RELOAD_V 198U /* TMR4_3_RLOV */ +#define INT_SRC_TMR4_3_RELOAD_W 199U /* TMR4_3_RLOW */ +/* TIMER6_4 TIMER6_5 */ +#define INT_SRC_TMR6_4_GCMP_A 208U /* TMR6_4_GCMA */ +#define INT_SRC_TMR6_4_GCMP_B 209U /* TMR6_4_GCMB */ +#define INT_SRC_TMR6_4_GCMP_C 210U /* TMR6_4_GCMC */ +#define INT_SRC_TMR6_4_GCMP_D 211U /* TMR6_4_GCMD */ +#define INT_SRC_TMR6_4_GCMP_E 212U /* TMR6_4_GCME */ +#define INT_SRC_TMR6_4_GCMP_F 213U /* TMR6_4_GCMF */ +#define INT_SRC_TMR6_4_OVF 214U /* TMR6_4_GOVF */ +#define INT_SRC_TMR6_4_UDF 215U /* TMR6_4_GUDF */ +#define INT_SRC_TMR6_4_DTE 216U /* TMR6_4_GDTE */ +#define INT_SRC_TMR6_4_SCMP_A 219U /* TMR6_4_SCMA */ +#define INT_SRC_TMR6_4_SCMP_B 220U /* TMR6_4_SCMB */ +#define INT_SRC_TMR6_5_GCMP_A 224U /* TMR6_5_GCMA */ +#define INT_SRC_TMR6_5_GCMP_B 225U /* TMR6_5_GCMB */ +#define INT_SRC_TMR6_5_GCMP_C 226U /* TMR6_5_GCMC */ +#define INT_SRC_TMR6_5_GCMP_D 227U /* TMR6_5_GCMD */ +#define INT_SRC_TMR6_5_GCMP_E 228U /* TMR6_5_GCME */ +#define INT_SRC_TMR6_5_GCMP_F 229U /* TMR6_5_GCMF */ +#define INT_SRC_TMR6_5_OVF 230U /* TMR6_5_GOVF */ +#define INT_SRC_TMR6_5_UDF 231U /* TMR6_5_GUDF */ +#define INT_SRC_TMR6_5_DTE 232U /* TMR6_5_GDTE */ +#define INT_SRC_TMR6_5_SCMP_A 235U /* TMR6_5_SCMA */ +#define INT_SRC_TMR6_5_SCMP_B 236U /* TMR6_5_SCMB */ +/* TIMERA_1 */ +#define INT_SRC_TMRA_1_OVF 237U /* TMRA_1_OVF */ +#define INT_SRC_TMRA_1_UDF 238U /* TMRA_1_UDF */ +#define INT_SRC_TMRA_1_CMP 239U /* TMRA_1_CMP */ +/* TIMER6_6 */ +#define INT_SRC_TMR6_6_GCMP_A 240U /* TMR6_6_GCMA */ +#define INT_SRC_TMR6_6_GCMP_B 241U /* TMR6_6_GCMB */ +#define INT_SRC_TMR6_6_GCMP_C 242U /* TMR6_6_GCMC */ +#define INT_SRC_TMR6_6_GCMP_D 243U /* TMR6_6_GCMD */ +#define INT_SRC_TMR6_6_GCMP_E 244U /* TMR6_6_GCME */ +#define INT_SRC_TMR6_6_GCMP_F 245U /* TMR6_6_GCMF */ +#define INT_SRC_TMR6_6_OVF 246U /* TMR6_6_GOVF */ +#define INT_SRC_TMR6_6_UDF 247U /* TMR6_6_GUDF */ +#define INT_SRC_TMR6_6_DTE 248U /* TMR6_6_GDTE */ +#define INT_SRC_TMR6_6_SCMP_A 251U /* TMR6_6_SCMA */ +#define INT_SRC_TMR6_6_SCMP_B 252U /* TMR6_6_SCMB */ +/* TIMERA_2 */ +#define INT_SRC_TMRA_2_OVF 253U /* TMRA_2_OVF */ +#define INT_SRC_TMRA_2_UDF 254U /* TMRA_2_UDF */ +#define INT_SRC_TMRA_2_CMP 255U /* TMRA_2_CMP */ +/* TIMER6_7 */ +#define INT_SRC_TMR6_7_GCMP_A 256U /* TMR6_7_GCMA */ +#define INT_SRC_TMR6_7_GCMP_B 257U /* TMR6_7_GCMB */ +#define INT_SRC_TMR6_7_GCMP_C 258U /* TMR6_7_GCMC */ +#define INT_SRC_TMR6_7_GCMP_D 259U /* TMR6_7_GCMD */ +#define INT_SRC_TMR6_7_GCMP_E 260U /* TMR6_7_GCME */ +#define INT_SRC_TMR6_7_GCMP_F 261U /* TMR6_7_GCMF */ +#define INT_SRC_TMR6_7_OVF 262U /* TMR6_7_GOVF */ +#define INT_SRC_TMR6_7_UDF 263U /* TMR6_7_GUDF */ +#define INT_SRC_TMR6_7_DTE 264U /* TMR6_7_GDTE */ +#define INT_SRC_TMR6_7_SCMP_A 267U /* TMR6_7_SCMA */ +#define INT_SRC_TMR6_7_SCMP_B 268U /* TMR6_7_SCMB */ +/* TIMERA_3 */ +#define INT_SRC_TMRA_3_OVF 269U /* TMRA_3_OVF */ +#define INT_SRC_TMRA_3_UDF 270U /* TMRA_3_UDF */ +#define INT_SRC_TMRA_3_CMP 271U /* TMRA_3_CMP */ +/* TIMER6_8 */ +#define INT_SRC_TMR6_8_GCMP_A 272U /* TMR6_8_GCMA */ +#define INT_SRC_TMR6_8_GCMP_B 273U /* TMR6_8_GCMB */ +#define INT_SRC_TMR6_8_GCMP_C 274U /* TMR6_8_GCMC */ +#define INT_SRC_TMR6_8_GCMP_D 275U /* TMR6_8_GCMD */ +#define INT_SRC_TMR6_8_GCMP_E 276U /* TMR6_8_GCME */ +#define INT_SRC_TMR6_8_GCMP_F 277U /* TMR6_8_GCMF */ +#define INT_SRC_TMR6_8_OVF 278U /* TMR6_8_GOVF */ +#define INT_SRC_TMR6_8_UDF 279U /* TMR6_8_GUDF */ +#define INT_SRC_TMR6_8_DTE 280U /* TMR6_8_GDTE */ +#define INT_SRC_TMR6_8_SCMP_A 283U /* TMR6_8_SCMA */ +#define INT_SRC_TMR6_8_SCMP_B 284U /* TMR6_8_SCMB */ +/* TIMERA_4 */ +#define INT_SRC_TMRA_4_OVF 285U /* TMRA_4_OVF */ +#define INT_SRC_TMRA_4_UDF 286U /* TMRA_4_UDF */ +#define INT_SRC_TMRA_4_CMP 287U /* TMRA_4_CMP */ +/* EMB */ +#define INT_SRC_EMB_GR0 288U /* EMB_GR0 */ +#define INT_SRC_EMB_GR1 289U /* EMB_GR1 */ +#define INT_SRC_EMB_GR2 290U /* EMB_GR2 */ +#define INT_SRC_EMB_GR3 291U /* EMB_GR3 */ +#define INT_SRC_EMB_GR4 292U /* EMB_GR4 */ +#define INT_SRC_EMB_GR5 293U /* EMB_GR5 */ +#define INT_SRC_EMB_GR6 294U /* EMB_GR6 */ +/* USBHS */ +#define INT_SRC_USBHS_EP1_OUT 295U /* USBHS_EP1_OUT */ +#define INT_SRC_USBHS_EP1_IN 296U /* USBHS_EP1_IN */ +#define INT_SRC_USBHS_GLB 297U /* USBHS_GLB */ +#define INT_SRC_USBHS_WKUP 298U /* USBHS_WKUP */ +/* USART1 USART2 */ +#define INT_SRC_USART1_EI 300U /* USART_1_EI */ +#define INT_SRC_USART1_RI 301U /* USART_1_RI */ +#define INT_SRC_USART1_TI 302U /* USART_1_TI */ +#define INT_SRC_USART1_TCI 303U /* USART_1_TCI */ +#define INT_SRC_USART1_RTO 304U /* USART_1_RTO */ +#define INT_SRC_USART2_EI 305U /* USART_2_EI */ +#define INT_SRC_USART2_RI 306U /* USART_2_RI */ +#define INT_SRC_USART2_TI 307U /* USART_2_TI */ +#define INT_SRC_USART2_TCI 308U /* USART_2_TCI */ +#define INT_SRC_USART2_RTO 309U /* USART_2_RTO */ +/* SPI1 SPI2 */ +#define INT_SRC_SPI1_SPRI 310U /* SPI_1_SPRI */ +#define INT_SRC_SPI1_SPTI 311U /* SPI_1_SPTI */ +#define INT_SRC_SPI1_SPII 312U /* SPI_1_SPII */ +#define INT_SRC_SPI1_SPEI 313U /* SPI_1_SPEI */ +#define INT_SRC_SPI2_SPRI 315U /* SPI_2_SPRI */ +#define INT_SRC_SPI2_SPTI 316U /* SPI_2_SPTI */ +#define INT_SRC_SPI2_SPII 317U /* SPI_2_SPII */ +#define INT_SRC_SPI2_SPEI 318U /* SPI_2_SPEI */ +/* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA*/ +#define INT_SRC_TMRA_5_OVF 320U /* TMRA_5_OVF */ +#define INT_SRC_TMRA_5_UDF 321U /* TMRA_5_UDF */ +#define INT_SRC_TMRA_5_CMP 322U /* TMRA_5_CMP */ +#define INT_SRC_TMRA_6_OVF 323U /* TMRA_6_OVF */ +#define INT_SRC_TMRA_6_UDF 324U /* TMRA_6_UDF */ +#define INT_SRC_TMRA_6_CMP 325U /* TMRA_6_CMP */ +#define INT_SRC_TMRA_7_OVF 326U /* TMRA_7_OVF */ +#define INT_SRC_TMRA_7_UDF 327U /* TMRA_7_UDF */ +#define INT_SRC_TMRA_7_CMP 328U /* TMRA_7_CMP */ +#define INT_SRC_TMRA_8_OVF 329U /* TMRA_8_OVF */ +#define INT_SRC_TMRA_8_UDF 330U /* TMRA_8_UDF */ +#define INT_SRC_TMRA_8_CMP 331U /* TMRA_8_CMP */ +/* USART3 USART4 */ +#define INT_SRC_USART3_EI 332U /* USART_3_EI */ +#define INT_SRC_USART3_RI 333U /* USART_3_RI */ +#define INT_SRC_USART3_TI 334U /* USART_3_TI */ +#define INT_SRC_USART3_TCI 335U /* USART_3_TCI */ +#define INT_SRC_USART4_EI 336U /* USART_4_EI */ +#define INT_SRC_USART4_RI 337U /* USART_4_RI */ +#define INT_SRC_USART4_TI 338U /* USART_4_TI */ +#define INT_SRC_USART4_TCI 339U /* USART_4_TCI */ +/* CAN1 CAN2 */ +#define INT_SRC_CAN1_HOST 340U /* CAN_1_HOST */ +#define INT_SRC_CAN2_HOST 341U /* CAN_2_HOST */ +/* SPI3 SPI4 */ +#define INT_SRC_SPI3_SPRI 342U /* SPI_3_SPRI */ +#define INT_SRC_SPI3_SPTI 343U /* SPI_3_SPTI */ +#define INT_SRC_SPI3_SPII 344U /* SPI_3_SPII */ +#define INT_SRC_SPI3_SPEI 345U /* SPI_3_SPEI */ +#define INT_SRC_SPI4_SPRI 347U /* SPI_4_SPRI */ +#define INT_SRC_SPI4_SPTI 348U /* SPI_4_SPTI */ +#define INT_SRC_SPI4_SPII 349U /* SPI_4_SPII */ +#define INT_SRC_SPI4_SPEI 350U /* SPI_4_SPEI */ +/* TIMERA_9 TIMERA_10 TIMER_11 TIMER */ +#define INT_SRC_TMRA_9_OVF 352U /* TMRA_9_OVF */ +#define INT_SRC_TMRA_9_UDF 353U /* TMRA_9_UDF */ +#define INT_SRC_TMRA_9_CMP 354U /* TMRA_9_CMP */ +#define INT_SRC_TMRA_10_OVF 355U /* TMRA_10_OVF */ +#define INT_SRC_TMRA_10_UDF 356U /* TMRA_10_UDF */ +#define INT_SRC_TMRA_10_CMP 357U /* TMRA_10_CMP */ +#define INT_SRC_TMRA_11_OVF 358U /* TMRA_11_OVF */ +#define INT_SRC_TMRA_11_UDF 359U /* TMRA_11_UDF */ +#define INT_SRC_TMRA_11_CMP 360U /* TMRA_11_CMP */ +#define INT_SRC_TMRA_12_OVF 361U /* TMRA_12_OVF */ +#define INT_SRC_TMRA_12_UDF 362U /* TMRA_12_UDF */ +#define INT_SRC_TMRA_12_CMP 363U /* TMRA_12_CMP */ +/* USART5 USART6 */ +#define INT_SRC_USART5_BRKWKPI 364U /* USART_5_BRKWKPI */ +#define INT_SRC_USART5_EI 365U /* USART_5_EI */ +#define INT_SRC_USART5_RI 366U /* USART_5_RI */ +#define INT_SRC_USART5_TI 367U /* USART_5_TI */ +#define INT_SRC_USART5_TCI 368U /* USART_5_TCI */ +#define INT_SRC_USART6_EI 369U /* USART_6_EI */ +#define INT_SRC_USART6_RI 370U /* USART_6_RI */ +#define INT_SRC_USART6_TI 371U /* USART_6_TI */ +#define INT_SRC_USART6_TCI 372U /* USART_6_TCI */ +#define INT_SRC_USART6_RTO 373U /* USART_6_RTO */ +/* SPI5 SPI6 */ +#define INT_SRC_SPI5_SPRI 374U /* SPI_5_SPRI */ +#define INT_SRC_SPI5_SPTI 375U /* SPI_5_SPTI */ +#define INT_SRC_SPI5_SPII 376U /* SPI_5_SPII */ +#define INT_SRC_SPI5_SPEI 377U /* SPI_5_SPEI */ +#define INT_SRC_SPI6_SPRI 379U /* SPI_6_SPRI */ +#define INT_SRC_SPI6_SPTI 380U /* SPI_6_SPTI */ +#define INT_SRC_SPI6_SPII 381U /* SPI_6_SPII */ +#define INT_SRC_SPI6_SPEI 382U /* SPI_6_SPEI */ +/* I2S1 I2S2 */ +#define INT_SRC_I2S1_TXIRQOUT 384U /* I2S_1_TXIRQOUT */ +#define INT_SRC_I2S1_RXIRQOUT 385U /* I2S_1_RXIRQOUT */ +#define INT_SRC_I2S1_ERRIRQOUT 386U /* I2S_1_ERRIRQOUT */ +#define INT_SRC_I2S2_TXIRQOUT 387U /* I2S_2_TXIRQOUT */ +#define INT_SRC_I2S2_RXIRQOUT 388U /* I2S_2_RXIRQOUT */ +#define INT_SRC_I2S2_ERRIRQOUT 389U /* I2S_2_ERRIRQOUT */ +/* USART7 USART8 */ +#define INT_SRC_USART7_EI 390U /* USART_7_EI */ +#define INT_SRC_USART7_RI 391U /* USART_7_RI */ +#define INT_SRC_USART7_TI 392U /* USART_7_TI */ +#define INT_SRC_USART7_TCI 393U /* USART_7_TCI */ +#define INT_SRC_USART7_RTO 394U /* USART_7_RTO */ +#define INT_SRC_USART8_EI 395U /* USART_8_EI */ +#define INT_SRC_USART8_RI 396U /* USART_8_RI */ +#define INT_SRC_USART8_TI 397U /* USART_8_TI */ +#define INT_SRC_USART8_TCI 398U /* USART_8_TCI */ +/* USBFS */ +#define INT_SRC_USBFS_GLB 399U /* USBFS_GLB */ +#define INT_SRC_USBFS_WKUP 400U /* USBFS_WKUP */ +/* HASH */ +#define INT_SRC_HASH 401U /* HASH_INT */ +/* SDIOC */ +#define INT_SRC_SDIOC1_SD 404U /* SDIOC_1_SD */ +#define INT_SRC_SDIOC2_SD 407U /* SDIOC_2_SD */ +/* EVENT PORT */ +#define INT_SRC_EVENT_PORT1 408U /* EVENT_PORT1 */ +#define INT_SRC_EVENT_PORT2 409U /* EVENT_PORT2 */ +#define INT_SRC_EVENT_PORT3 410U /* EVENT_PORT3 */ +#define INT_SRC_EVENT_PORT4 411U /* EVENT_PORT4 */ +/* ETHER */ +#define INT_SRC_ETH_GLB_INT 412U /* ETH_GLB_INT */ +#define INT_SRC_ETH_WKP_INT 413U /* ETH_WKP_INT */ +/* I2S3 I2S4 */ +#define INT_SRC_I2S3_TXIRQOUT 416U /* I2S_3_TXIRQOUT */ +#define INT_SRC_I2S3_RXIRQOUT 417U /* I2S_3_RXIRQOUT */ +#define INT_SRC_I2S3_ERRIRQOUT 418U /* I2S_3_ERRIRQOUT */ +#define INT_SRC_I2S4_TXIRQOUT 419U /* I2S_4_TXIRQOUT */ +#define INT_SRC_I2S4_RXIRQOUT 420U /* I2S_4_RXIRQOUT */ +#define INT_SRC_I2S4_ERRIRQOUT 421U /* I2S_4_ERRIRQOUT */ +/* USART9 USART10 */ +#define INT_SRC_USART9_EI 422U /* USART_9_EI */ +#define INT_SRC_USART9_RI 423U /* USART_9_RI */ +#define INT_SRC_USART9_TI 424U /* USART_9_TI */ +#define INT_SRC_USART9_TCI 425U /* USART_9_TCI */ +#define INT_SRC_USART10_BRKWKPI 426U /* USART_10_BRKWKPI */ +#define INT_SRC_USART10_EI 427U /* USART_10_EI */ +#define INT_SRC_USART10_RI 428U /* USART_10_RI */ +#define INT_SRC_USART10_TI 429U /* USART_10_TI */ +#define INT_SRC_USART10_TCI 430U /* USART_10_TCI */ +/* I2C1 I2C2 I2C3 */ +#define INT_SRC_I2C1_RXI 432U /* I2C_1_RXI */ +#define INT_SRC_I2C1_TXI 433U /* I2C_1_TXI */ +#define INT_SRC_I2C1_TEI 434U /* I2C_1_TEI */ +#define INT_SRC_I2C1_EEI 435U /* I2C_1_EEI */ +#define INT_SRC_I2C2_RXI 436U /* I2C_2_RXI */ +#define INT_SRC_I2C2_TXI 437U /* I2C_2_TXI */ +#define INT_SRC_I2C2_TEI 438U /* I2C_2_TEI */ +#define INT_SRC_I2C2_EEI 439U /* I2C_2_EEI */ +#define INT_SRC_I2C3_RXI 440U /* I2C_3_RXI */ +#define INT_SRC_I2C3_TXI 441U /* I2C_3_TXI */ +#define INT_SRC_I2C3_TEI 442U /* I2C_3_TEI */ +#define INT_SRC_I2C3_EEI 443U /* I2C_3_EEI */ +/* ACMP */ +#define INT_SRC_CMP1 444U /* CMP1 */ +#define INT_SRC_CMP2 445U /* CMP2 */ +#define INT_SRC_CMP3 446U /* CMP3 */ +#define INT_SRC_CMP4 447U /* CMP4 */ +/* I2C4 I2C5 I2C6 */ +#define INT_SRC_I2C4_RXI 448U /* I2C_4_RXI */ +#define INT_SRC_I2C4_TXI 449U /* I2C_4_TXI */ +#define INT_SRC_I2C4_TEI 450U /* I2C_4_TEI */ +#define INT_SRC_I2C4_EEI 451U /* I2C_4_EEI */ +#define INT_SRC_I2C5_RXI 452U /* I2C_5_RXI */ +#define INT_SRC_I2C5_TXI 453U /* I2C_5_TXI */ +#define INT_SRC_I2C5_TEI 454U /* I2C_5_TEI */ +#define INT_SRC_I2C5_EEI 455U /* I2C_5_EEI */ +#define INT_SRC_I2C6_RXI 456U /* I2C_6_RXI */ +#define INT_SRC_I2C6_TXI 457U /* I2C_6_TXI */ +#define INT_SRC_I2C6_TEI 458U /* I2C_6_TEI */ +#define INT_SRC_I2C6_EEI 459U /* I2C_6_EEI */ +/* USART1 */ +#define INT_SRC_USART1_WUPI 460U /* USART_1_WUPI */ +/* LVD */ +#define INT_SRC_LVD1 461U /* LVD1 */ +#define INT_SRC_LVD2 462U /* LVD2 */ +/* OTS */ +#define INT_SRC_OTS 463U /* OTS */ +/* FCM */ +#define INT_SRC_FCMFERRI 464U /* FCMFERRI */ +#define INT_SRC_FCMMENDI 465U /* FCMMENDI */ +#define INT_SRC_FCMCOVFI 466U /* FCMCOVFI */ +/* WDT */ +#define INT_SRC_WDT_REFUDF 467U /* WDT_REFUDF */ +/* CTC */ +#define INT_SRC_CTC_ERR 468U /* CTC_ERR */ +/* ADC */ +#define INT_SRC_ADC1_EOCA 480U /* ADC_1_EOCA */ +#define INT_SRC_ADC1_EOCB 481U /* ADC_1_EOCB */ +#define INT_SRC_ADC1_CMP0 482U /* ADC_1_CMP0 */ +#define INT_SRC_ADC1_CMP1 483U /* ADC_1_CMP1 */ +#define INT_SRC_ADC2_EOCA 484U /* ADC_2_EOCA */ +#define INT_SRC_ADC2_EOCB 485U /* ADC_2_EOCB */ +#define INT_SRC_ADC2_CMP0 486U /* ADC_2_CMP0 */ +#define INT_SRC_ADC2_CMP1 487U /* ADC_2_CMP1 */ +#define INT_SRC_ADC3_EOCA 488U /* ADC_3_EOCA */ +#define INT_SRC_ADC3_EOCB 489U /* ADC_3_EOCB */ +#define INT_SRC_ADC3_CMP0 490U /* ADC_3_CMP0 */ +#define INT_SRC_ADC3_CMP1 491U /* ADC_3_CMP1 */ +/* TRNG */ +#define INT_SRC_TRNG_END 492U /* TRNG_END */ +/* NFC */ +#define INT_SRC_NFC_INT 496U /* NFC_INT */ +#define INT_SRC_MAX 511U + +/** + * @brief Event Source Number + */ +#define EVT_SRC_SWI_IRQ0 0 /* SWI_IRQ0 */ +#define EVT_SRC_SWI_IRQ1 1 /* SWI_IRQ1 */ +#define EVT_SRC_SWI_IRQ2 2 /* SWI_IRQ2 */ +#define EVT_SRC_SWI_IRQ3 3 /* SWI_IRQ3 */ +#define EVT_SRC_SWI_IRQ4 4 /* SWI_IRQ4 */ +#define EVT_SRC_SWI_IRQ5 5 /* SWI_IRQ5 */ +#define EVT_SRC_SWI_IRQ6 6 /* SWI_IRQ6 */ +#define EVT_SRC_SWI_IRQ7 7 /* SWI_IRQ7 */ +#define EVT_SRC_SWI_IRQ8 8 /* SWI_IRQ8 */ +#define EVT_SRC_SWI_IRQ9 9 /* SWI_IRQ9 */ +#define EVT_SRC_SWI_IRQ10 10 /* SWI_IRQ10 */ +#define EVT_SRC_SWI_IRQ11 11 /* SWI_IRQ11 */ +#define EVT_SRC_SWI_IRQ12 12 /* SWI_IRQ12 */ +#define EVT_SRC_SWI_IRQ13 13 /* SWI_IRQ13 */ +#define EVT_SRC_SWI_IRQ14 14 /* SWI_IRQ14 */ +#define EVT_SRC_SWI_IRQ15 15 /* SWI_IRQ15 */ +#define EVT_SRC_SWI_IRQ16 16 /* SWI_IRQ16 */ +#define EVT_SRC_SWI_IRQ17 17 /* SWI_IRQ17 */ +#define EVT_SRC_SWI_IRQ18 18 /* SWI_IRQ18 */ +#define EVT_SRC_SWI_IRQ19 19 /* SWI_IRQ19 */ +#define EVT_SRC_SWI_IRQ20 20 /* SWI_IRQ20 */ +#define EVT_SRC_SWI_IRQ21 21 /* SWI_IRQ21 */ +#define EVT_SRC_SWI_IRQ22 22 /* SWI_IRQ22 */ +#define EVT_SRC_SWI_IRQ23 23 /* SWI_IRQ23 */ +#define EVT_SRC_SWI_IRQ24 24 /* SWI_IRQ24 */ +#define EVT_SRC_SWI_IRQ25 25 /* SWI_IRQ25 */ +#define EVT_SRC_SWI_IRQ26 26 /* SWI_IRQ26 */ +#define EVT_SRC_SWI_IRQ27 27 /* SWI_IRQ27 */ +#define EVT_SRC_SWI_IRQ28 28 /* SWI_IRQ28 */ +#define EVT_SRC_SWI_IRQ29 29 /* SWI_IRQ29 */ +#define EVT_SRC_SWI_IRQ30 30 /* SWI_IRQ30 */ +#define EVT_SRC_SWI_IRQ31 31 /* SWI_IRQ31 */ + +/* External Interrupt. */ +#define EVT_SRC_PORT_EIRQ0 0 /* PORT_EIRQ0 */ +#define EVT_SRC_PORT_EIRQ1 1 /* PORT_EIRQ1 */ +#define EVT_SRC_PORT_EIRQ2 2 /* PORT_EIRQ2 */ +#define EVT_SRC_PORT_EIRQ3 3 /* PORT_EIRQ3 */ +#define EVT_SRC_PORT_EIRQ4 4 /* PORT_EIRQ4 */ +#define EVT_SRC_PORT_EIRQ5 5 /* PORT_EIRQ5 */ +#define EVT_SRC_PORT_EIRQ6 6 /* PORT_EIRQ6 */ +#define EVT_SRC_PORT_EIRQ7 7 /* PORT_EIRQ7 */ +#define EVT_SRC_PORT_EIRQ8 8 /* PORT_EIRQ8 */ +#define EVT_SRC_PORT_EIRQ9 9 /* PORT_EIRQ9 */ +#define EVT_SRC_PORT_EIRQ10 10 /* PORT_EIRQ10 */ +#define EVT_SRC_PORT_EIRQ11 11 /* PORT_EIRQ11 */ +#define EVT_SRC_PORT_EIRQ12 12 /* PORT_EIRQ12 */ +#define EVT_SRC_PORT_EIRQ13 13 /* PORT_EIRQ13 */ +#define EVT_SRC_PORT_EIRQ14 14 /* PORT_EIRQ14 */ +#define EVT_SRC_PORT_EIRQ15 15 /* PORT_EIRQ15 */ + +/* DMA_1 */ +#define EVT_SRC_DMA1_TC0 32U /* DMA_1_TC0 */ +#define EVT_SRC_DMA1_TC1 33U /* DMA_1_TC1 */ +#define EVT_SRC_DMA1_TC2 34U /* DMA_1_TC2 */ +#define EVT_SRC_DMA1_TC3 35U /* DMA_1_TC3 */ +#define EVT_SRC_DMA1_TC4 36U /* DMA_1_TC4 */ +#define EVT_SRC_DMA1_TC5 37U /* DMA_1_TC5 */ +#define EVT_SRC_DMA1_TC6 38U /* DMA_1_TC6 */ +#define EVT_SRC_DMA1_TC7 39U /* DMA_1_TC7 */ +#define EVT_SRC_DMA1_BTC0 40U /* DMA_1_BTC0 */ +#define EVT_SRC_DMA1_BTC1 41U /* DMA_1_BTC1 */ +#define EVT_SRC_DMA1_BTC2 42U /* DMA_1_BTC2 */ +#define EVT_SRC_DMA1_BTC3 43U /* DMA_1_BTC3 */ +#define EVT_SRC_DMA1_BTC4 44U /* DMA_1_BTC4 */ +#define EVT_SRC_DMA1_BTC5 45U /* DMA_1_BTC5 */ +#define EVT_SRC_DMA1_BTC6 46U /* DMA_1_BTC6 */ +#define EVT_SRC_DMA1_BTC7 47U /* DMA_1_BTC7 */ +/* EFM */ +#define EVT_SRC_EFM_OPTEND 51U /* EFM_OPTEND */ +/* USBFS */ +#define EVT_SRC_USBFS_SOF 52U /* USBFS_SOF */ +/* USBHS */ +#define EVT_SRC_USBHS_SOF 53U /* USBHS_SOF */ +/* DCU */ +#define EVT_SRC_DCU1 55U /* DCU1 */ +#define EVT_SRC_DCU2 56U /* DCU2 */ +#define EVT_SRC_DCU3 57U /* DCU3 */ +#define EVT_SRC_DCU4 58U /* DCU4 */ +#define EVT_SRC_DCU5 59U /* DCU5 */ +#define EVT_SRC_DCU6 60U /* DCU6 */ +#define EVT_SRC_DCU7 61U /* DCU7 */ +#define EVT_SRC_DCU8 62U /* DCU8 */ +/* DMA_2 */ +#define EVT_SRC_DMA2_TC0 64U /* DMA_2_TC0 */ +#define EVT_SRC_DMA2_TC1 65U /* DMA_2_TC1 */ +#define EVT_SRC_DMA2_TC2 66U /* DMA_2_TC2 */ +#define EVT_SRC_DMA2_TC3 67U /* DMA_2_TC3 */ +#define EVT_SRC_DMA2_TC4 68U /* DMA_2_TC4 */ +#define EVT_SRC_DMA2_TC5 69U /* DMA_2_TC5 */ +#define EVT_SRC_DMA2_TC6 70U /* DMA_2_TC6 */ +#define EVT_SRC_DMA2_TC7 71U /* DMA_2_TC7 */ +#define EVT_SRC_DMA2_BTC0 72U /* DMA_2_BTC0 */ +#define EVT_SRC_DMA2_BTC1 73U /* DMA_2_BTC1 */ +#define EVT_SRC_DMA2_BTC2 74U /* DMA_2_BTC2 */ +#define EVT_SRC_DMA2_BTC3 75U /* DMA_2_BTC3 */ +#define EVT_SRC_DMA2_BTC4 76U /* DMA_2_BTC4 */ +#define EVT_SRC_DMA2_BTC5 77U /* DMA_2_BTC5 */ +#define EVT_SRC_DMA2_BTC6 78U /* DMA_2_BTC6 */ +#define EVT_SRC_DMA2_BTC7 79U /* DMA_2_BTC7 */ +/* MAU */ +#define EVT_SRC_MAU_SQRT 83U /* MAU_SQRT */ +/* DVP */ +#define EVT_SRC_DVP_FRAMSTA 84U /* DVP_FRAMSTA */ +#define EVT_SRC_DVP_LINESTA 85U /* DVP_LINESTA */ +#define EVT_SRC_DVP_LINEEND 86U /* DVP_LINEEND */ +#define EVT_SRC_DVP_FRAMEND 87U /* DVP_FRAMEND */ +#define EVT_SRC_DVP_SQUERR 88U /* DVP_SQUERR */ +#define EVT_SRC_DVP_FIFOERR 89U /* DVP_FIFOERR */ +#define EVT_SRC_DVP_DMAREQ 90U /* DVP_DMAREQ */ +/* FMAC */ +#define EVT_SRC_FMAC_1 91U /* FMAC_1_FIR */ +#define EVT_SRC_FMAC_2 92U /* FMAC_2_FIR */ +#define EVT_SRC_FMAC_3 93U /* FMAC_3_FIR */ +#define EVT_SRC_FMAC_4 94U /* FMAC_4_FIR */ +/* TIMER0 */ +#define EVT_SRC_TMR0_1_CMP_A 96U /* TMR0_1_CMPA */ +#define EVT_SRC_TMR0_1_CMP_B 97U /* TMR0_1_CMPB */ +#define EVT_SRC_TMR0_2_CMP_A 98U /* TMR0_2_CMPA */ +#define EVT_SRC_TMR0_2_CMP_B 99U /* TMR0_2_CMPB */ +/* TIMER2 */ +#define EVT_SRC_TMR2_1_CMP_A 100U /* TMR2_1_CMPA */ +#define EVT_SRC_TMR2_1_CMP_B 101U /* TMR2_1_CMPB */ +#define EVT_SRC_TMR2_1_OVF_A 102U /* TMR2_1_OVFA */ +#define EVT_SRC_TMR2_1_OVF_B 103U /* TMR2_1_OVFB */ +#define EVT_SRC_TMR2_2_CMP_A 104U /* TMR2_2_CMPA */ +#define EVT_SRC_TMR2_2_CMP_B 105U /* TMR2_2_CMPB */ +#define EVT_SRC_TMR2_2_OVF_A 106U /* TMR2_2_OVFA */ +#define EVT_SRC_TMR2_2_OVF_B 107U /* TMR2_2_OVFB */ +#define EVT_SRC_TMR2_3_CMP_A 108U /* TMR2_3_CMPA */ +#define EVT_SRC_TMR2_3_CMP_B 109U /* TMR2_3_CMPB */ +#define EVT_SRC_TMR2_3_OVF_A 110U /* TMR2_3_OVFA */ +#define EVT_SRC_TMR2_3_OVF_B 111U /* TMR2_3_OVFB */ +#define EVT_SRC_TMR2_4_CMP_A 112U /* TMR2_4_CMPA */ +#define EVT_SRC_TMR2_4_CMP_B 113U /* TMR2_4_CMPB */ +#define EVT_SRC_TMR2_4_OVF_A 114U /* TMR2_4_OVFA */ +#define EVT_SRC_TMR2_4_OVF_B 115U /* TMR2_4_OVFB */ +/* RTC */ +#define EVT_SRC_RTC_ALM 121U /* RTC_ALM */ +#define EVT_SRC_RTC_PRD 122U /* RTC_PRD */ +/* TIMER6_1 */ +#define EVT_SRC_TMR6_1_GCMP_A 128U /* TMR6_1_GCMA */ +#define EVT_SRC_TMR6_1_GCMP_B 129U /* TMR6_1_GCMB */ +#define EVT_SRC_TMR6_1_GCMP_C 130U /* TMR6_1_GCMC */ +#define EVT_SRC_TMR6_1_GCMP_D 131U /* TMR6_1_GCMD */ +#define EVT_SRC_TMR6_1_GCMP_E 132U /* TMR6_1_GCME */ +#define EVT_SRC_TMR6_1_GCMP_F 133U /* TMR6_1_GCMF */ +#define EVT_SRC_TMR6_1_OVF 134U /* TMR6_1_GOVF */ +#define EVT_SRC_TMR6_1_UDF 135U /* TMR6_1_GUDF */ +/* TIMER4_1 */ +#define EVT_SRC_TMR4_1_SCMP0 136U /* TMR4_1_SCM0 */ +#define EVT_SRC_TMR4_1_SCMP1 137U /* TMR4_1_SCM1 */ +#define EVT_SRC_TMR4_1_SCMP2 138U /* TMR4_1_SCM2 */ +#define EVT_SRC_TMR4_1_SCMP3 139U /* TMR4_1_SCM3 */ +#define EVT_SRC_TMR4_1_SCMP4 140U /* TMR4_1_SCM4 */ +#define EVT_SRC_TMR4_1_SCMP5 141U /* TMR4_1_SCM5 */ +/* TIMER6_2 */ +#define EVT_SRC_TMR6_2_GCMP_A 144U /* TMR6_2_GCMA */ +#define EVT_SRC_TMR6_2_GCMP_B 145U /* TMR6_2_GCMB */ +#define EVT_SRC_TMR6_2_GCMP_C 146U /* TMR6_2_GCMC */ +#define EVT_SRC_TMR6_2_GCMP_D 147U /* TMR6_2_GCMD */ +#define EVT_SRC_TMR6_2_GCMP_E 148U /* TMR6_2_GCME */ +#define EVT_SRC_TMR6_2_GCMP_F 149U /* TMR6_2_GCMF */ +#define EVT_SRC_TMR6_2_OVF 150U /* TMR6_2_GOVF */ +#define EVT_SRC_TMR6_2_UDF 151U /* TMR6_2_GUDF */ +/* TIMER4_2 */ +#define EVT_SRC_TMR4_2_SCMP0 152U /* TMR4_2_SCM0 */ +#define EVT_SRC_TMR4_2_SCMP1 153U /* TMR4_2_SCM1 */ +#define EVT_SRC_TMR4_2_SCMP2 154U /* TMR4_2_SCM2 */ +#define EVT_SRC_TMR4_2_SCMP3 155U /* TMR4_2_SCM3 */ +#define EVT_SRC_TMR4_2_SCMP4 156U /* TMR4_2_SCM4 */ +#define EVT_SRC_TMR4_2_SCMP5 157U /* TMR4_2_SCM5 */ +/* TIMER6_3 */ +#define EVT_SRC_TMR6_3_GCMP_A 160U /* TMR6_3_GCMA */ +#define EVT_SRC_TMR6_3_GCMP_B 161U /* TMR6_3_GCMB */ +#define EVT_SRC_TMR6_3_GCMP_C 162U /* TMR6_3_GCMC */ +#define EVT_SRC_TMR6_3_GCMP_D 163U /* TMR6_3_GCMD */ +#define EVT_SRC_TMR6_3_GCMP_E 164U /* TMR6_3_GCME */ +#define EVT_SRC_TMR6_3_GCMP_F 165U /* TMR6_3_GCMF */ +#define EVT_SRC_TMR6_3_OVF 166U /* TMR6_3_GOVF */ +#define EVT_SRC_TMR6_3_UDF 167U /* TMR6_3_GUDF */ +/* TIMER4_3 */ +#define EVT_SRC_TMR4_3_SCMP0 168U /* TMR4_3_SCM0 */ +#define EVT_SRC_TMR4_3_SCMP1 169U /* TMR4_3_SCM1 */ +#define EVT_SRC_TMR4_3_SCMP2 170U /* TMR4_3_SCM2 */ +#define EVT_SRC_TMR4_3_SCMP3 171U /* TMR4_3_SCM3 */ +#define EVT_SRC_TMR4_3_SCMP4 172U /* TMR4_3_SCM4 */ +#define EVT_SRC_TMR4_3_SCMP5 173U /* TMR4_3_SCM5 */ +/* TIMER6 */ +#define EVT_SRC_TMR6_1_SCMP_A 179U /* TMR6_1_SCMA */ +#define EVT_SRC_TMR6_1_SCMP_B 180U /* TMR6_1_SCMB */ +#define EVT_SRC_TMR6_2_SCMP_A 187U /* TMR6_2_SCMA */ +#define EVT_SRC_TMR6_2_SCMP_B 188U /* TMR6_2_SCMB */ +#define EVT_SRC_TMR6_3_SCMP_A 195U /* TMR6_3_SCMA */ +#define EVT_SRC_TMR6_3_SCMP_B 196U /* TMR6_3_SCMB */ +#define EVT_SRC_TMR6_4_GCMP_A 208U /* TMR6_4_GCMA */ +#define EVT_SRC_TMR6_4_GCMP_B 209U /* TMR6_4_GCMB */ +#define EVT_SRC_TMR6_4_GCMP_C 210U /* TMR6_4_GCMC */ +#define EVT_SRC_TMR6_4_GCMP_D 211U /* TMR6_4_GCMD */ +#define EVT_SRC_TMR6_4_GCMP_E 212U /* TMR6_4_GCME */ +#define EVT_SRC_TMR6_4_GCMP_F 213U /* TMR6_4_GCMF */ +#define EVT_SRC_TMR6_4_OVF 214U /* TMR6_4_GOVF */ +#define EVT_SRC_TMR6_4_UDF 215U /* TMR6_4_GUDF */ +#define EVT_SRC_TMR6_4_SCMP_A 219U /* TMR6_4_SCMA */ +#define EVT_SRC_TMR6_4_SCMP_B 220U /* TMR6_4_SCMB */ +#define EVT_SRC_TMR6_5_GCMP_A 224U /* TMR6_5_GCMA */ +#define EVT_SRC_TMR6_5_GCMP_B 225U /* TMR6_5_GCMB */ +#define EVT_SRC_TMR6_5_GCMP_C 226U /* TMR6_5_GCMC */ +#define EVT_SRC_TMR6_5_GCMP_D 227U /* TMR6_5_GCMD */ +#define EVT_SRC_TMR6_5_GCMP_E 228U /* TMR6_5_GCME */ +#define EVT_SRC_TMR6_5_GCMP_F 229U /* TMR6_5_GCMF */ +#define EVT_SRC_TMR6_5_OVF 230U /* TMR6_5_GOVF */ +#define EVT_SRC_TMR6_5_UDF 231U /* TMR6_5_GUDF */ +#define EVT_SRC_TMR6_5_SCMP_A 235U /* TMR6_5_SCMA */ +#define EVT_SRC_TMR6_5_SCMP_B 236U /* TMR6_5_SCMB */ +/* TIMERA_1 */ +#define EVT_SRC_TMRA_1_OVF 237U /* TMRA_1_OVF */ +#define EVT_SRC_TMRA_1_UDF 238U /* TMRA_1_UDF */ +#define EVT_SRC_TMRA_1_CMP 239U /* TMRA_1_CMP */ +/* TIMER6_6 */ +#define EVT_SRC_TMR6_6_GCMP_A 240U /* TMR6_6_GCMA */ +#define EVT_SRC_TMR6_6_GCMP_B 241U /* TMR6_6_GCMB */ +#define EVT_SRC_TMR6_6_GCMP_C 242U /* TMR6_6_GCMC */ +#define EVT_SRC_TMR6_6_GCMP_D 243U /* TMR6_6_GCMD */ +#define EVT_SRC_TMR6_6_GCMP_E 244U /* TMR6_6_GCME */ +#define EVT_SRC_TMR6_6_GCMP_F 245U /* TMR6_6_GCMF */ +#define EVT_SRC_TMR6_6_OVF 246U /* TMR6_6_GOVF */ +#define EVT_SRC_TMR6_6_UDF 247U /* TMR6_6_GUDF */ +#define EVT_SRC_TMR6_6_SCMP_A 251U /* TMR6_6_SCMA */ +#define EVT_SRC_TMR6_6_SCMP_B 252U /* TMR6_6_SCMB */ +/* TIMERA_2 */ +#define EVT_SRC_TMRA_2_OVF 253U /* TMRA_2_OVF */ +#define EVT_SRC_TMRA_2_UDF 254U /* TMRA_2_UDF */ +#define EVT_SRC_TMRA_2_CMP 255U /* TMRA_2_CMP */ +/* TIMER6_7 */ +#define EVT_SRC_TMR6_7_GCMP_A 256U /* TMR6_7_GCMA */ +#define EVT_SRC_TMR6_7_GCMP_B 257U /* TMR6_7_GCMB */ +#define EVT_SRC_TMR6_7_GCMP_C 258U /* TMR6_7_GCMC */ +#define EVT_SRC_TMR6_7_GCMP_D 259U /* TMR6_7_GCMD */ +#define EVT_SRC_TMR6_7_GCMP_E 260U /* TMR6_7_GCME */ +#define EVT_SRC_TMR6_7_GCMP_F 261U /* TMR6_7_GCMF */ +#define EVT_SRC_TMR6_7_OVF 262U /* TMR6_7_GOVF */ +#define EVT_SRC_TMR6_7_UDF 263U /* TMR6_7_GUDF */ +#define EVT_SRC_TMR6_7_SCMP_A 267U /* TMR6_7_SCMA */ +#define EVT_SRC_TMR6_7_SCMP_B 268U /* TMR6_7_SCMB */ +/* TIMERA_3 */ +#define EVT_SRC_TMRA_3_OVF 269U /* TMRA_3_OVF */ +#define EVT_SRC_TMRA_3_UDF 270U /* TMRA_3_UDF */ +#define EVT_SRC_TMRA_3_CMP 271U /* TMRA_3_CMP */ +/* TIMER6_8 */ +#define EVT_SRC_TMR6_8_GCMP_A 272U /* TMR6_8_GCMA */ +#define EVT_SRC_TMR6_8_GCMP_B 273U /* TMR6_8_GCMB */ +#define EVT_SRC_TMR6_8_GCMP_C 274U /* TMR6_8_GCMC */ +#define EVT_SRC_TMR6_8_GCMP_D 275U /* TMR6_8_GCMD */ +#define EVT_SRC_TMR6_8_GCMP_E 276U /* TMR6_8_GCME */ +#define EVT_SRC_TMR6_8_GCMP_F 277U /* TMR6_8_GCMF */ +#define EVT_SRC_TMR6_8_OVF 278U /* TMR6_8_GOVF */ +#define EVT_SRC_TMR6_8_UDF 279U /* TMR6_8_GUDF */ +#define EVT_SRC_TMR6_8_SCMP_A 283U /* TMR6_8_SCMA */ +#define EVT_SRC_TMR6_8_SCMP_B 284U /* TMR6_8_SCMB */ +/* TIMERA_4 */ +#define EVT_SRC_TMRA_4_OVF 285U /* TMRA_4_OVF */ +#define EVT_SRC_TMRA_4_UDF 286U /* TMRA_4_UDF */ +#define EVT_SRC_TMRA_4_CMP 287U /* TMRA_4_CMP */ +/* AOS_STRG */ +#define EVT_SRC_AOS_STRG 299U /* AOS_STRG */ +/* USART1 USART2 */ +#define EVT_SRC_USART1_EI 300U /* USART_1_EI */ +#define EVT_SRC_USART1_RI 301U /* USART_1_RI */ +#define EVT_SRC_USART1_TI 302U /* USART_1_TI */ +#define EVT_SRC_USART1_TCI 303U /* USART_1_TCI */ +#define EVT_SRC_USART1_RTO 304U /* USART_1_RTO */ +#define EVT_SRC_USART2_EI 305U /* USART_2_EI */ +#define EVT_SRC_USART2_RI 306U /* USART_2_RI */ +#define EVT_SRC_USART2_TI 307U /* USART_2_TI */ +#define EVT_SRC_USART2_TCI 308U /* USART_2_TCI */ +#define EVT_SRC_USART2_RTO 309U /* USART_2_RTO */ +/* SPI1 SPI2 */ +#define EVT_SRC_SPI1_SPRI 310U /* SPI_1_SPRI */ +#define EVT_SRC_SPI1_SPTI 311U /* SPI_1_SPTI */ +#define EVT_SRC_SPI1_SPII 312U /* SPI_1_SPII */ +#define EVT_SRC_SPI1_SPEI 313U /* SPI_1_SPEI */ +#define EVT_SRC_SPI1_SPEND 314U /* SPI_1_SPEND */ +#define EVT_SRC_SPI2_SPRI 315U /* SPI_2_SPRI */ +#define EVT_SRC_SPI2_SPTI 316U /* SPI_2_SPTI */ +#define EVT_SRC_SPI2_SPII 317U /* SPI_2_SPII */ +#define EVT_SRC_SPI2_SPEI 318U /* SPI_2_SPEI */ +#define EVT_SRC_SPI2_SPEND 319U /* SPI_2_SPEND */ +/* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */ +#define EVT_SRC_TMRA_5_OVF 320U /* TMRA_5_OVF */ +#define EVT_SRC_TMRA_5_UDF 321U /* TMRA_5_UDF */ +#define EVT_SRC_TMRA_5_CMP 322U /* TMRA_5_CMP */ +#define EVT_SRC_TMRA_6_OVF 323U /* TMRA_6_OVF */ +#define EVT_SRC_TMRA_6_UDF 324U /* TMRA_6_UDF */ +#define EVT_SRC_TMRA_6_CMP 325U /* TMRA_6_CMP */ +#define EVT_SRC_TMRA_7_OVF 326U /* TMRA_7_OVF */ +#define EVT_SRC_TMRA_7_UDF 327U /* TMRA_7_UDF */ +#define EVT_SRC_TMRA_7_CMP 328U /* TMRA_7_CMP */ +#define EVT_SRC_TMRA_8_OVF 329U /* TMRA_8_OVF */ +#define EVT_SRC_TMRA_8_UDF 330U /* TMRA_8_UDF */ +#define EVT_SRC_TMRA_8_CMP 331U /* TMRA_8_CMP */ +/* USART3 USART4 */ +#define EVT_SRC_USART3_EI 332U /* USART_3_EI */ +#define EVT_SRC_USART3_RI 333U /* USART_3_RI */ +#define EVT_SRC_USART3_TI 334U /* USART_3_TI */ +#define EVT_SRC_USART3_TCI 335U /* USART_3_TCI */ +#define EVT_SRC_USART4_EI 336U /* USART_4_EI */ +#define EVT_SRC_USART4_RI 337U /* USART_4_RI */ +#define EVT_SRC_USART4_TI 338U /* USART_4_TI */ +#define EVT_SRC_USART4_TCI 339U /* USART_4_TCI */ +/* SPI3 SPI4 */ +#define EVT_SRC_SPI3_SPRI 342U /* SPI_3_SPRI */ +#define EVT_SRC_SPI3_SPTI 343U /* SPI_3_SPTI */ +#define EVT_SRC_SPI3_SPII 344U /* SPI_3_SPII */ +#define EVT_SRC_SPI3_SPEI 345U /* SPI_3_SPEI */ +#define EVT_SRC_SPI3_SPEND 346U /* SPI_3_SPEND */ +#define EVT_SRC_SPI4_SPRI 347U /* SPI_4_SPRI */ +#define EVT_SRC_SPI4_SPTI 348U /* SPI_4_SPTI */ +#define EVT_SRC_SPI4_SPII 349U /* SPI_4_SPII */ +#define EVT_SRC_SPI4_SPEI 350U /* SPI_4_SPEI */ +#define EVT_SRC_SPI4_SPEND 351U /* SPI_4_SPEND */ +/* TIMERA_9 TIMERA_10 TIMERA_11 TIMERA_12 */ +#define EVT_SRC_TMRA_9_OVF 352U /* TMRA_9_OVF */ +#define EVT_SRC_TMRA_9_UDF 353U /* TMRA_9_UDF */ +#define EVT_SRC_TMRA_9_CMP 354U /* TMRA_9_CMP */ +#define EVT_SRC_TMRA_10_OVF 355U /* TMRA_10_OVF */ +#define EVT_SRC_TMRA_10_UDF 356U /* TMRA_10_UDF */ +#define EVT_SRC_TMRA_10_CMP 357U /* TMRA_10_CMP */ +#define EVT_SRC_TMRA_11_OVF 358U /* TMRA_11_OVF */ +#define EVT_SRC_TMRA_11_UDF 359U /* TMRA_11_UDF */ +#define EVT_SRC_TMRA_11_CMP 360U /* TMRA_11_CMP */ +#define EVT_SRC_TMRA_12_OVF 361U /* TMRA_12_OVF */ +#define EVT_SRC_TMRA_12_UDF 362U /* TMRA_12_UDF */ +#define EVT_SRC_TMRA_12_CMP 363U /* TMRA_12_CMP */ +/* USART5 USART6 */ +#define EVT_SRC_USART5_BRKWKPI 364U /* USART_5_BRKWKPI */ +#define EVT_SRC_USART5_EI 365U /* USART_5_EI */ +#define EVT_SRC_USART5_RI 366U /* USART_5_RI */ +#define EVT_SRC_USART5_TI 367U /* USART_5_TI */ +#define EVT_SRC_USART5_TCI 368U /* USART_5_TCI */ +#define EVT_SRC_USART6_EI 369U /* USART_6_EI */ +#define EVT_SRC_USART6_RI 370U /* USART_6_RI */ +#define EVT_SRC_USART6_TI 371U /* USART_6_TI */ +#define EVT_SRC_USART6_TCI 372U /* USART_6_TCI */ +#define EVT_SRC_USART6_RTO 373U /* USART_6_RTO */ +/* SPI5 SPI6 */ +#define EVT_SRC_SPI5_SPRI 374U /* SPI_5_SPRI */ +#define EVT_SRC_SPI5_SPTI 375U /* SPI_5_SPTI */ +#define EVT_SRC_SPI5_SPII 376U /* SPI_5_SPII */ +#define EVT_SRC_SPI5_SPEI 377U /* SPI_5_SPEI */ +#define EVT_SRC_SPI5_SPEND 378U /* SPI_5_SPEND */ +#define EVT_SRC_SPI6_SPRI 379U /* SPI_6_SPRI */ +#define EVT_SRC_SPI6_SPTI 380U /* SPI_6_SPTI */ +#define EVT_SRC_SPI6_SPII 381U /* SPI_6_SPII */ +#define EVT_SRC_SPI6_SPEI 382U /* SPI_6_SPEI */ +#define EVT_SRC_SPI6_SPEND 383U /* SPI_6_SPEND */ +/* I2S1 I2S2 */ +#define EVT_SRC_I2S1_TXIRQOUT 384U /* I2S_1_TXIRQOUT */ +#define EVT_SRC_I2S1_RXIRQOUT 385U /* I2S_1_RXIRQOUT */ +#define EVT_SRC_I2S2_TXIRQOUT 387U /* I2S_2_TXIRQOUT */ +#define EVT_SRC_I2S2_RXIRQOUT 388U /* I2S_2_RXIRQOUT */ +/* USART7 USART8 */ +#define EVT_SRC_USART7_EI 390U /* USART_7_EI */ +#define EVT_SRC_USART7_RI 391U /* USART_7_RI */ +#define EVT_SRC_USART7_TI 392U /* USART_7_TI */ +#define EVT_SRC_USART7_TCI 393U /* USART_7_TCI */ +#define EVT_SRC_USART7_RTO 394U /* USART_7_RTO */ +#define EVT_SRC_USART8_EI 395U /* USART_8_EI */ +#define EVT_SRC_USART8_RI 396U /* USART_8_RI */ +#define EVT_SRC_USART8_TI 397U /* USART_8_TI */ +#define EVT_SRC_USART8_TCI 398U /* USART_8_TCI */ +/* HASH */ +#define EVT_SRC_HASH 401U /* HASH_INT */ +/* SDIOC */ +#define EVT_SRC_SDIOC1_DMAR 402U /* SDIOC_1_DMAR */ +#define EVT_SRC_SDIOC1_DMAW 403U /* SDIOC_1_DMAW */ +#define EVT_SRC_SDIOC2_DMAR 405U /* SDIOC_2_DMAR */ +#define EVT_SRC_SDIOC2_DMAW 406U /* SDIOC_2_DMAW */ +/* EVENT PORT */ +#define EVT_SRC_EVENT_PORT1 408U /* EVENT_PORT1 */ +#define EVT_SRC_EVENT_PORT2 409U /* EVENT_PORT2 */ +#define EVT_SRC_EVENT_PORT3 410U /* EVENT_PORT3 */ +#define EVT_SRC_EVENT_PORT4 411U /* EVENT_PORT4 */ +/* ETHER */ +#define EVT_SRC_ETH_PPS_OUT_0 414U /* ETH_PPS_OUT_0 */ +#define EVT_SRC_ETH_PPS_OUT_1 415U /* ETH_PPS_OUT_1 */ +/* I2S3 I2S4 */ +#define EVT_SRC_I2S3_TXIRQOUT 416U /* I2S_3_TXIRQOUT */ +#define EVT_SRC_I2S3_RXIRQOUT 417U /* I2S_3_RXIRQOUT */ +#define EVT_SRC_I2S4_TXIRQOUT 419U /* I2S_4_TXIRQOUT */ +#define EVT_SRC_I2S4_RXIRQOUT 420U /* I2S_4_RXIRQOUT */ +/* USART9 USART10 */ +#define EVT_SRC_USART9_EI 422U /* USART_9_EI */ +#define EVT_SRC_USART9_RI 423U /* USART_9_RI */ +#define EVT_SRC_USART9_TI 424U /* USART_9_TI */ +#define EVT_SRC_USART9_TCI 425U /* USART_9_TCI */ +#define EVT_SRC_USART10_BRKWKPI 426U /* USART_10_BRKWKPI */ +#define EVT_SRC_USART10_EI 427U /* USART_10_EI */ +#define EVT_SRC_USART10_RI 428U /* USART_10_RI */ +#define EVT_SRC_USART10_TI 429U /* USART_10_TI */ +#define EVT_SRC_USART10_TCI 430U /* USART_10_TCI */ +/* I2C1 I2C2 I2C3 */ +#define EVT_SRC_I2C1_RXI 432U /* I2C_1_RXI */ +#define EVT_SRC_I2C1_TXI 433U /* I2C_1_TXI */ +#define EVT_SRC_I2C1_TEI 434U /* I2C_1_TEI */ +#define EVT_SRC_I2C1_EEI 435U /* I2C_1_EEI */ +#define EVT_SRC_I2C2_RXI 436U /* I2C_2_RXI */ +#define EVT_SRC_I2C2_TXI 437U /* I2C_2_TXI */ +#define EVT_SRC_I2C2_TEI 438U /* I2C_2_TEI */ +#define EVT_SRC_I2C2_EEI 439U /* I2C_2_EEI */ +#define EVT_SRC_I2C3_RXI 440U /* I2C_3_RXI */ +#define EVT_SRC_I2C3_TXI 441U /* I2C_3_TXI */ +#define EVT_SRC_I2C3_TEI 442U /* I2C_3_TEI */ +#define EVT_SRC_I2C3_EEI 443U /* I2C_3_EEI */ +/* ACMP */ +#define EVT_SRC_CMP1 444U /* CMP1 */ +#define EVT_SRC_CMP2 445U /* CMP2 */ +#define EVT_SRC_CMP3 446U /* CMP3 */ +#define EVT_SRC_CMP4 447U /* CMP4 */ +/* I2C4 I2C5 I2C6 */ +#define EVT_SRC_I2C4_RXI 448U /* I2C_4_RXI */ +#define EVT_SRC_I2C4_TXI 449U /* I2C_4_TXI */ +#define EVT_SRC_I2C4_TEI 450U /* I2C_4_TEI */ +#define EVT_SRC_I2C4_EEI 451U /* I2C_4_EEI */ +#define EVT_SRC_I2C5_RXI 452U /* I2C_5_RXI */ +#define EVT_SRC_I2C5_TXI 453U /* I2C_5_TXI */ +#define EVT_SRC_I2C5_TEI 454U /* I2C_5_TEI */ +#define EVT_SRC_I2C5_EEI 455U /* I2C_5_EEI */ +#define EVT_SRC_I2C6_RXI 456U /* I2C_6_RXI */ +#define EVT_SRC_I2C6_TXI 457U /* I2C_6_TXI */ +#define EVT_SRC_I2C6_TEI 458U /* I2C_6_TEI */ +#define EVT_SRC_I2C6_EEI 459U /* I2C_6_EEI */ +/* LVD */ +#define EVT_SRC_LVD1 461U /* LVD1 */ +#define EVT_SRC_LVD2 462U /* LVD2 */ +/* OTS */ +#define EVT_SRC_OTS 463U /* OTS */ +/* WDT */ +#define EVT_SRC_WDT_REFUDF 467U /* WDT_REFUDF */ +/* ADC */ +#define EVT_SRC_ADC1_EOCA 480U /* ADC_1_EOCA */ +#define EVT_SRC_ADC1_EOCB 481U /* ADC_1_EOCB */ +#define EVT_SRC_ADC1_CMP0 482U /* ADC_1_CMP0 */ +#define EVT_SRC_ADC1_CMP1 483U /* ADC_1_CMP1 */ +#define EVT_SRC_ADC2_EOCA 484U /* ADC_2_EOCA */ +#define EVT_SRC_ADC2_EOCB 485U /* ADC_2_EOCB */ +#define EVT_SRC_ADC2_CMP0 486U /* ADC_2_CMP0 */ +#define EVT_SRC_ADC2_CMP1 487U /* ADC_2_CMP1 */ +#define EVT_SRC_ADC3_EOCA 488U /* ADC_3_EOCA */ +#define EVT_SRC_ADC3_EOCB 489U /* ADC_3_EOCB */ +#define EVT_SRC_ADC3_CMP0 490U /* ADC_3_CMP0 */ +#define EVT_SRC_ADC3_CMP1 491U /* ADC_3_CMP1 */ +/* TRNG */ +#define EVT_SRC_TRNG_END 492U /* TRNG_END */ +#define EVT_SRC_MAX 511U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INT_EVT_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-intc.h b/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-intc.h new file mode 100644 index 0000000000000..bde0f5f3ee4f6 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/hc32f4a0-intc.h @@ -0,0 +1,714 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INTC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INTC_H_ + +#include + +/* Ext ch0 */ +#define HC32_EXTINT0_IRQ_NUM INT128_IRQn +#define HC32_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch1 */ +#define HC32_EXTINT1_IRQ_NUM INT128_IRQn +#define HC32_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch2 */ +#define HC32_EXTINT2_IRQ_NUM INT128_IRQn +#define HC32_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch3 */ +#define HC32_EXTINT3_IRQ_NUM INT128_IRQn +#define HC32_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch4 */ +#define HC32_EXTINT4_IRQ_NUM INT128_IRQn +#define HC32_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch5 */ +#define HC32_EXTINT5_IRQ_NUM INT128_IRQn +#define HC32_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch6 */ +#define HC32_EXTINT6_IRQ_NUM INT128_IRQn +#define HC32_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch7 */ +#define HC32_EXTINT7_IRQ_NUM INT128_IRQn +#define HC32_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch8 */ +#define HC32_EXTINT8_IRQ_NUM INT128_IRQn +#define HC32_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch9 */ +#define HC32_EXTINT9_IRQ_NUM INT128_IRQn +#define HC32_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch10 */ +#define HC32_EXTINT10_IRQ_NUM INT128_IRQn +#define HC32_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch11 */ +#define HC32_EXTINT11_IRQ_NUM INT128_IRQn +#define HC32_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch12 */ +#define HC32_EXTINT12_IRQ_NUM INT128_IRQn +#define HC32_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch13 */ +#define HC32_EXTINT13_IRQ_NUM INT128_IRQn +#define HC32_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch14 */ +#define HC32_EXTINT14_IRQ_NUM INT128_IRQn +#define HC32_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* Ext ch15 */ +#define HC32_EXTINT15_IRQ_NUM INT128_IRQn +#define HC32_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define HC32_DMA1_CH0_IRQ_NUM INT038_IRQn +#define HC32_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define HC32_DMA1_CH1_IRQ_NUM INT039_IRQn +#define HC32_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define HC32_DMA1_CH2_IRQ_NUM INT040_IRQn +#define HC32_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define HC32_DMA1_CH3_IRQ_NUM INT041_IRQn +#define HC32_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 err */ +#define HC32_DMA1_ERR_IRQ_NUM INT042_IRQn +#define HC32_DMA1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define HC32_DMA1_CH4_IRQ_NUM INT043_IRQn +#define HC32_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define HC32_DMA1_CH5_IRQ_NUM INT008_IRQn +#define HC32_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define HC32_DMA1_CH6_IRQ_NUM INT007_IRQn +#define HC32_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define HC32_DMA1_CH7_IRQ_NUM INT006_IRQn +#define HC32_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define HC32_DMA2_CH0_IRQ_NUM INT044_IRQn +#define HC32_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define HC32_DMA2_CH1_IRQ_NUM INT045_IRQn +#define HC32_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define HC32_DMA2_CH2_IRQ_NUM INT046_IRQn +#define HC32_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define HC32_DMA2_CH3_IRQ_NUM INT047_IRQn +#define HC32_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 err */ +#define HC32_DMA2_ERR_IRQ_NUM INT048_IRQn +#define HC32_DMA2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define HC32_DMA2_CH4_IRQ_NUM INT049_IRQn +#define HC32_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define HC32_DMA2_CH5_IRQ_NUM INT005_IRQn +#define HC32_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define HC32_DMA2_CH6_IRQ_NUM INT004_IRQn +#define HC32_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define HC32_DMA2_CH7_IRQ_NUM INT003_IRQn +#define HC32_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* USART */ +#define HC32_UART1_RXERR_IRQ_NUM INT010_IRQn +#define HC32_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART1_RX_IRQ_NUM INT014_IRQn +#define HC32_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART1_TX_IRQ_NUM INT015_IRQn +#define HC32_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART1_TX_CPLT_IRQ_NUM INT016_IRQn +#define HC32_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART1_RXTO_IRQ_NUM INT011_IRQn +#define HC32_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART2_RXERR_IRQ_NUM INT086_IRQn +#define HC32_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART2_RX_IRQ_NUM INT087_IRQn +#define HC32_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART2_TX_IRQ_NUM INT088_IRQn +#define HC32_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART2_TX_CPLT_IRQ_NUM INT089_IRQn +#define HC32_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART2_RXTO_IRQ_NUM INT090_IRQn +#define HC32_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART3_RXERR_IRQ_NUM INT092_IRQn +#define HC32_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART3_RX_IRQ_NUM INT093_IRQn +#define HC32_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART3_TX_IRQ_NUM INT094_IRQn +#define HC32_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART3_TX_CPLT_IRQ_NUM INT095_IRQn +#define HC32_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART3_RXTO_IRQ_NUM INT096_IRQn +#define HC32_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART4_RXERR_IRQ_NUM INT092_IRQn +#define HC32_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART4_RX_IRQ_NUM INT093_IRQn +#define HC32_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART4_TX_IRQ_NUM INT094_IRQn +#define HC32_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART4_RXTO_IRQ_NUM INT096_IRQn +#define HC32_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_UART4_TX_CPLT_IRQ_NUM INT095_IRQn +#define HC32_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* SPI */ +#define HC32_SPI1_ERR_IRQ_NUM INT086_IRQn +#define HC32_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI1_RBF_IRQ_NUM INT087_IRQn +#define HC32_SPI1_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI1_TBE_IRQ_NUM INT088_IRQn +#define HC32_SPI1_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI2_ERR_IRQ_NUM INT089_IRQn +#define HC32_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI2_RBF_IRQ_NUM INT090_IRQn +#define HC32_SPI2_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI2_TBE_IRQ_NUM INT091_IRQn +#define HC32_SPI2_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI3_ERR_IRQ_NUM INT092_IRQn +#define HC32_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI3_RBF_IRQ_NUM INT093_IRQn +#define HC32_SPI3_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI3_TBE_IRQ_NUM INT094_IRQn +#define HC32_SPI3_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI4_ERR_IRQ_NUM INT095_IRQn +#define HC32_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI4_RBF_IRQ_NUM INT096_IRQn +#define HC32_SPI4_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI4_TBE_IRQ_NUM INT097_IRQn +#define HC32_SPI4_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI5_ERR_IRQ_NUM INT098_IRQn +#define HC32_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI5_RBF_IRQ_NUM INT099_IRQn +#define HC32_SPI5_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI5_TBE_IRQ_NUM INT100_IRQn +#define HC32_SPI5_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI6_ERR_IRQ_NUM INT101_IRQn +#define HC32_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI6_RBF_IRQ_NUM INT102_IRQn +#define HC32_SPI6_RBF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_SPI6_TBE_IRQ_NUM INT103_IRQn +#define HC32_SPI6_TBE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* RTC */ +#define HC32_RTC_ALARM_IRQ_NUM INT050_IRQn +#define HC32_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_RTC_PRD_IRQ_NUM INT051_IRQn +#define HC32_RTC_PRD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA1*/ +#define HC32_TMRA1_OVF_IRQ_NUM INT074_IRQn +#define HC32_TMRA1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA1_UDF_IRQ_NUM INT075_IRQn +#define HC32_TMRA1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA1_CMP_IRQ_NUM INT076_IRQn +#define HC32_TMRA1_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA2*/ +#define HC32_TMRA2_OVF_IRQ_NUM INT077_IRQn +#define HC32_TMRA2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA2_UDF_IRQ_NUM INT078_IRQn +#define HC32_TMRA2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA2_CMP_IRQ_NUM INT079_IRQn +#define HC32_TMRA2_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA3*/ +#define HC32_TMRA3_OVF_IRQ_NUM INT080_IRQn +#define HC32_TMRA3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA3_UDF_IRQ_NUM INT081_IRQn +#define HC32_TMRA3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA3_CMP_IRQ_NUM INT082_IRQn +#define HC32_TMRA3_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA4*/ +#define HC32_TMRA4_OVF_IRQ_NUM INT083_IRQn +#define HC32_TMRA4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA4_UDF_IRQ_NUM INT084_IRQn +#define HC32_TMRA4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA4_CMP_IRQ_NUM INT085_IRQn +#define HC32_TMRA4_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA5*/ +#define HC32_TMRA5_OVF_IRQ_NUM INT092_IRQn +#define HC32_TMRA5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA5_UDF_IRQ_NUM INT093_IRQn +#define HC32_TMRA5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA5_CMP_IRQ_NUM INT094_IRQn +#define HC32_TMRA5_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA6*/ +#define HC32_TMRA6_OVF_IRQ_NUM INT092_IRQn +#define HC32_TMRA6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA6_UDF_IRQ_NUM INT093_IRQn +#define HC32_TMRA6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA6_CMP_IRQ_NUM INT094_IRQn +#define HC32_TMRA6_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA7*/ +#define HC32_TMRA7_OVF_IRQ_NUM INT095_IRQn +#define HC32_TMRA7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA7_UDF_IRQ_NUM INT096_IRQn +#define HC32_TMRA7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA7_CMP_IRQ_NUM INT097_IRQn +#define HC32_TMRA7_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA8*/ +#define HC32_TMRA8_OVF_IRQ_NUM INT095_IRQn +#define HC32_TMRA8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA8_UDF_IRQ_NUM INT096_IRQn +#define HC32_TMRA8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA8_CMP_IRQ_NUM INT097_IRQn +#define HC32_TMRA8_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA9*/ +#define HC32_TMRA9_OVF_IRQ_NUM INT098_IRQn +#define HC32_TMRA9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA9_UDF_IRQ_NUM INT099_IRQn +#define HC32_TMRA9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA9_CMP_IRQ_NUM INT100_IRQn +#define HC32_TMRA9_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA10*/ +#define HC32_TMRA10_OVF_IRQ_NUM INT098_IRQn +#define HC32_TMRA10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA10_UDF_IRQ_NUM INT099_IRQn +#define HC32_TMRA10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA10_CMP_IRQ_NUM INT100_IRQn +#define HC32_TMRA10_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA11*/ +#define HC32_TMRA11_OVF_IRQ_NUM INT101_IRQn +#define HC32_TMRA11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA11_UDF_IRQ_NUM INT102_IRQn +#define HC32_TMRA11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA11_CMP_IRQ_NUM INT103_IRQn +#define HC32_TMRA11_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* TimerA12*/ +#define HC32_TMRA12_OVF_IRQ_NUM INT101_IRQn +#define HC32_TMRA12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA12_UDF_IRQ_NUM INT102_IRQn +#define HC32_TMRA12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMRA12_CMP_IRQ_NUM INT103_IRQn +#define HC32_TMRA12_CMP_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer41*/ +#define HC32_TMR41_CMP_UH_IRQ_NUM INT092_IRQn +#define HC32_TMR41_CMP_UH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_CMP_UL_IRQ_NUM INT093_IRQn +#define HC32_TMR41_CMP_UL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_CMP_VH_IRQ_NUM INT094_IRQn +#define HC32_TMR41_CMP_VH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_CMP_VL_IRQ_NUM INT095_IRQn +#define HC32_TMR41_CMP_VL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_CMP_WH_IRQ_NUM INT012_IRQn +#define HC32_TMR41_CMP_WH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_CMP_WL_IRQ_NUM INT013_IRQn +#define HC32_TMR41_CMP_WL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_OVF_IRQ_NUM INT096_IRQn +#define HC32_TMR41_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR41_UDF_IRQ_NUM INT097_IRQn +#define HC32_TMR41_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer42*/ +#define HC32_TMR42_CMP_UH_IRQ_NUM INT092_IRQn +#define HC32_TMR42_CMP_UH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_CMP_UL_IRQ_NUM INT093_IRQn +#define HC32_TMR42_CMP_UL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_CMP_VH_IRQ_NUM INT094_IRQn +#define HC32_TMR42_CMP_VH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_CMP_VL_IRQ_NUM INT095_IRQn +#define HC32_TMR42_CMP_VL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_CMP_WH_IRQ_NUM INT012_IRQn +#define HC32_TMR42_CMP_WH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_CMP_WL_IRQ_NUM INT013_IRQn +#define HC32_TMR42_CMP_WL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_OVF_IRQ_NUM INT096_IRQn +#define HC32_TMR42_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR42_UDF_IRQ_NUM INT097_IRQn +#define HC32_TMR42_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer43 */ +#define HC32_TMR43_CMP_UH_IRQ_NUM INT098_IRQn +#define HC32_TMR43_CMP_UH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_CMP_UL_IRQ_NUM INT099_IRQn +#define HC32_TMR43_CMP_UL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_CMP_VH_IRQ_NUM INT100_IRQn +#define HC32_TMR43_CMP_VH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_CMP_VL_IRQ_NUM INT101_IRQn +#define HC32_TMR43_CMP_VL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_CMP_WH_IRQ_NUM INT012_IRQn +#define HC32_TMR43_CMP_WH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_CMP_WL_IRQ_NUM INT013_IRQn +#define HC32_TMR43_CMP_WL_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_OVF_IRQ_NUM INT102_IRQn +#define HC32_TMR43_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR43_UDF_IRQ_NUM INT103_IRQn +#define HC32_TMR43_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer61 interrupt */ +#define HC32_TMR61_CMPA_IRQ_NUM INT056_IRQn +#define HC32_TMR61_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_CMPB_IRQ_NUM INT057_IRQn +#define HC32_TMR61_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_CMPC_IRQ_NUM INT058_IRQn +#define HC32_TMR61_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_CMPD_IRQ_NUM INT059_IRQn +#define HC32_TMR61_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_CMPE_IRQ_NUM INT060_IRQn +#define HC32_TMR61_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_CMPF_IRQ_NUM INT061_IRQn +#define HC32_TMR61_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_OVF_IRQ_NUM INT030_IRQn +#define HC32_TMR61_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR61_UDF_IRQ_NUM INT031_IRQn +#define HC32_TMR61_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer62 interrupt */ +#define HC32_TMR62_CMPA_IRQ_NUM INT056_IRQn +#define HC32_TMR62_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_CMPB_IRQ_NUM INT057_IRQn +#define HC32_TMR62_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_CMPC_IRQ_NUM INT058_IRQn +#define HC32_TMR62_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_CMPD_IRQ_NUM INT059_IRQn +#define HC32_TMR62_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_CMPE_IRQ_NUM INT060_IRQn +#define HC32_TMR62_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_CMPF_IRQ_NUM INT061_IRQn +#define HC32_TMR62_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_OVF_IRQ_NUM INT030_IRQn +#define HC32_TMR62_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR62_UDF_IRQ_NUM INT031_IRQn +#define HC32_TMR62_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer63 interrupt */ +#define HC32_TMR63_CMPA_IRQ_NUM INT062_IRQn +#define HC32_TMR63_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_CMPB_IRQ_NUM INT063_IRQn +#define HC32_TMR63_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_CMPC_IRQ_NUM INT064_IRQn +#define HC32_TMR63_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_CMPD_IRQ_NUM INT065_IRQn +#define HC32_TMR63_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_CMPE_IRQ_NUM INT066_IRQn +#define HC32_TMR63_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_CMPF_IRQ_NUM INT067_IRQn +#define HC32_TMR63_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_OVF_IRQ_NUM INT028_IRQn +#define HC32_TMR63_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR63_UDF_IRQ_NUM INT029_IRQn +#define HC32_TMR63_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer64 interrupt */ +#define HC32_TMR64_CMPA_IRQ_NUM INT068_IRQn +#define HC32_TMR64_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_CMPB_IRQ_NUM INT069_IRQn +#define HC32_TMR64_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_CMPC_IRQ_NUM INT070_IRQn +#define HC32_TMR64_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_CMPD_IRQ_NUM INT071_IRQn +#define HC32_TMR64_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_CMPE_IRQ_NUM INT072_IRQn +#define HC32_TMR64_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_CMPF_IRQ_NUM INT073_IRQn +#define HC32_TMR64_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_OVF_IRQ_NUM INT026_IRQn +#define HC32_TMR64_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR64_UDF_IRQ_NUM INT027_IRQn +#define HC32_TMR64_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer65 interrupt */ +#define HC32_TMR65_CMPA_IRQ_NUM INT074_IRQn +#define HC32_TMR65_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_CMPB_IRQ_NUM INT075_IRQn +#define HC32_TMR65_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_CMPC_IRQ_NUM INT076_IRQn +#define HC32_TMR65_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_CMPD_IRQ_NUM INT077_IRQn +#define HC32_TMR65_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_CMPE_IRQ_NUM INT078_IRQn +#define HC32_TMR65_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_CMPF_IRQ_NUM INT079_IRQn +#define HC32_TMR65_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_OVF_IRQ_NUM INT024_IRQn +#define HC32_TMR65_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR65_UDF_IRQ_NUM INT025_IRQn +#define HC32_TMR65_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer66 interrupt */ +#define HC32_TMR66_CMPA_IRQ_NUM INT074_IRQn +#define HC32_TMR66_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_CMPB_IRQ_NUM INT075_IRQn +#define HC32_TMR66_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_CMPC_IRQ_NUM INT076_IRQn +#define HC32_TMR66_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_CMPD_IRQ_NUM INT077_IRQn +#define HC32_TMR66_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_CMPE_IRQ_NUM INT078_IRQn +#define HC32_TMR66_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_CMPF_IRQ_NUM INT079_IRQn +#define HC32_TMR66_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_OVF_IRQ_NUM INT024_IRQn +#define HC32_TMR66_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR66_UDF_IRQ_NUM INT025_IRQn +#define HC32_TMR66_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer67 interrupt */ +#define HC32_TMR67_CMPA_IRQ_NUM INT080_IRQn +#define HC32_TMR67_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_CMPB_IRQ_NUM INT081_IRQn +#define HC32_TMR67_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_CMPC_IRQ_NUM INT082_IRQn +#define HC32_TMR67_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_CMPD_IRQ_NUM INT083_IRQn +#define HC32_TMR67_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_CMPE_IRQ_NUM INT084_IRQn +#define HC32_TMR67_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_CMPF_IRQ_NUM INT085_IRQn +#define HC32_TMR67_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_OVF_IRQ_NUM INT022_IRQn +#define HC32_TMR67_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR67_UDF_IRQ_NUM INT023_IRQn +#define HC32_TMR67_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* Timer68 interrupt */ +#define HC32_TMR68_CMPA_IRQ_NUM INT080_IRQn +#define HC32_TMR68_CMPA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_CMPB_IRQ_NUM INT081_IRQn +#define HC32_TMR68_CMPB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_CMPC_IRQ_NUM INT082_IRQn +#define HC32_TMR68_CMPC_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_CMPD_IRQ_NUM INT083_IRQn +#define HC32_TMR68_CMPD_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_CMPE_IRQ_NUM INT084_IRQn +#define HC32_TMR68_CMPE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_CMPF_IRQ_NUM INT085_IRQn +#define HC32_TMR68_CMPF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_OVF_IRQ_NUM INT022_IRQn +#define HC32_TMR68_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define HC32_TMR68_UDF_IRQ_NUM INT023_IRQn +#define HC32_TMR68_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* I2C share */ +#define HC32_I2C_IRQ_SHARE1_NUM INT141_IRQn +#define HC32_I2C_IRQ_SHARE1_PRIO DDL_IRQ_PRIO_DEFAULT +/* I2C1 */ +#define HC32_I2C1_EE_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C1_EE_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C1_TE_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C1_TE_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C1_TX_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C1_TX_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C1_RX_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C1_RX_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +/* I2C2 */ +#define HC32_I2C2_EE_IRQ_NUM INT110_IRQn +#define HC32_I2C2_EE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_I2C2_TE_IRQ_NUM INT111_IRQn +#define HC32_I2C2_TE_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_I2C2_TX_IRQ_NUM INT112_IRQn +#define HC32_I2C2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_I2C2_RX_IRQ_NUM INT113_IRQn +#define HC32_I2C2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* I2C3 */ +#define HC32_I2C3_EE_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C3_EE_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C3_TE_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C3_TE_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C3_TX_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C3_TX_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO +#define HC32_I2C3_RX_IRQ_NUM HC32_I2C_IRQ_SHARE1_NUM +#define HC32_I2C3_RX_IRQ_PRIO HC32_I2C_IRQ_SHARE1_PRIO + +#define HC32_I2C_IRQ_SHARE2_NUM INT142_IRQn +#define HC32_I2C_IRQ_SHARE2_PRIO DDL_IRQ_PRIO_DEFAULT +/* I2C4 */ +#define HC32_I2C4_EE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C4_EE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C4_TE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C4_TE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C4_TX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C4_TX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C4_RX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C4_RX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +/* I2C5 */ +#define HC32_I2C5_EE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C5_EE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C5_TE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C5_TE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C5_TX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C5_TX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C5_RX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C5_RX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +/* I2C6 */ +#define HC32_I2C6_EE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C6_EE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C6_TE_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C6_TE_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C6_TX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C6_TX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO +#define HC32_I2C6_RX_IRQ_NUM HC32_I2C_IRQ_SHARE2_NUM +#define HC32_I2C6_RX_IRQ_PRIO HC32_I2C_IRQ_SHARE2_PRIO + +/* ADC */ +#define HC32_ADC1_EOCA_IRQ_NUM INT122_IRQn +#define HC32_ADC1_EOCA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_ADC1_EOCB_IRQ_NUM INT123_IRQn +#define HC32_ADC1_EOCB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_ADC2_EOCA_IRQ_NUM INT122_IRQn +#define HC32_ADC2_EOCA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_ADC2_EOCB_IRQ_NUM INT123_IRQn +#define HC32_ADC2_EOCB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_ADC3_EOCA_IRQ_NUM INT122_IRQn +#define HC32_ADC3_EOCA_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define HC32_ADC3_EOCB_IRQ_NUM INT123_IRQn +#define HC32_ADC3_EOCB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* QSPI */ +#define HC32_QSPI_IRQ_NUM INT043_IRQn +#define HC32_QSPI_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_HC32F4A0_INTC_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/hc32-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/hc32-pinctrl.h new file mode 100644 index 0000000000000..77176e6a0fd17 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/hc32-pinctrl.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_HC32_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_HC32_PINCTRL_H_ + +#define HC32_PORT(_mux) (((_mux) >> HC32_PORT_SHIFT) & HC32_PORT_MSK) + +#define HC32_PIN(_mux) (((_mux) >> HC32_PIN_SHIFT) & HC32_PIN_MSK) + +#define HC32_MODE(_mux) (((_mux) >> HC32_MODE_SHIFT) & HC32_MODE_MSK) + +#define HC32_FUNC_NUM(_mux) (((_mux) >> HC32_FUNC_SHIFT) & HC32_FUNC_MSK) + +#define HC32_PIN_BIAS(_mux) (_mux & HC32_PUR_MSK) +#define HC32_PIN_DRV(_mux) (_mux & HC32_NOD_MSK) +#define HC32_OUT_LEVEL(_mux) (_mux & HC32_OTYPE_MSK) +#define HC32_PIN_EN_DIR(_mux) (_mux & HC32_DIREN_MSK) +#define HC32_PIN_DRIVER_STRENGTH(_mux) (_mux & HC32_STRENGTH_MSK) +#define HC32_INVERT(_mux) (_mux & HC32_INVERT_MSK) +#define HC32_CINSEL(_mux) (_mux & HC32_CINSEL_MSK) + +/* pinmux filed in pinctrl_soc_pin*/ +/* + * @brief Pin modes + */ +#define HC32_ANALOG 0x00U +#define HC32_GPIO 0x01U +#define HC32_FUNC 0x02U +#define HC32_SUBFUNC 0x03U + +/* + * @brief Macro to generate pinmux int using port, pin number and mode arguments + * This is inspired from Linux equivalent st,HC32f429-pinctrl binding + */ +#define HC32_FUNC_SHIFT 10U +#define HC32_FUNC_MSK 0xFFU +#define HC32_MODE_SHIFT 8U +#define HC32_MODE_MSK 0x03U +#define HC32_PIN_SHIFT 4U +#define HC32_PIN_MSK 0x0FU +#define HC32_PORT_SHIFT 0U +#define HC32_PORT_MSK 0x0FU + +/* + * @brief pinmux bit field. + * + * Fields: + * - cfg [24:31] + * - func_num [ 10 ：17] + * - mode [ 8 : 9 ] + * - pin [ 4 : 7 ] + * - port [ 0 : 3 ] + * + * @param port Port ('A'..'E', 'H') + * @param pin Pin (0..15) + * @param mode Mode (ANALOG, FUC, SUBFUC). + * @param func_num range:0--63. + * @param cfg configuration for pin + */ +#define HC32_PINMUX(port, pin, mode, func_num, cfg) \ + (((((port) - 'A') & HC32_PORT_MSK) << HC32_PORT_SHIFT) | \ + (((pin) & HC32_PIN_MSK) << HC32_PIN_SHIFT) | \ + (((HC32_##mode) & HC32_MODE_MSK) << HC32_MODE_SHIFT) | \ + (((func_num) & HC32_FUNC_MSK) << HC32_FUNC_SHIFT) | (cfg)) + +/* cfg filed in pinctrl_soc_pin*/ +/* + * @brief Definitions cfg bit pos and mask + */ +#define HC32_NO_PULL (0U << HC32_PUR_SHIFT) +#define HC32_PULL_UP (1U << HC32_PUR_SHIFT) + +#define HC32_PUSH_PULL (0U << HC32_NOD_SHIFT) +#define HC32_OPEN_DRAIN (1U << HC32_NOD_SHIFT) + +#define HC32_OUTPUT_LOW (0U << HC32_OTYPE_SHIFT) +#define HC32_OUTPUT_HIGH (1U << HC32_OTYPE_SHIFT) + +#define HC32_INPUT_ENABLE (0U << HC32_DIREN_SHIFT) +#define HC32_OUTPUT_ENABLE (1U << HC32_DIREN_SHIFT) + +#define HC32_DRIVER_STRENGTH_LOW (0U << HC32_STRENGTH_SHIFT) +#define HC32_DRIVER_STRENGTH_MEDIUM (1U << HC32_STRENGTH_SHIFT) +#define HC32_DRIVER_STRENGTH_HIGH (2U << HC32_STRENGTH_SHIFT) + +#define HC32_INVERT_DISABLE (0U << HC32_INVERT_SHIFT) +#define HC32_INVERT_ENABLE (1U << HC32_INVERT_SHIFT) + +#define HC32_CINSEL_SCHMITT (0U << HC32_CINSEL_SHIFT) +#define HC32_CINSEL_CMOS (1U << HC32_CINSEL_SHIFT) + +/* + * @brief Pin cfg bit field in pinmux. + * + * Fields: + * - CINSEL [31] + * - INVERT [30] + * - STRENGTH [28:29] + * - DIREN [ 27] + * - OTYPE [ 26 ] + * - NOD [ 25 ] + * - PUR [ 24 ] + */ + +/* PUR field position. */ +#define HC32_PUR_SHIFT 24U +/* PUR field mask. */ +#define HC32_PUR_MSK (1U << HC32_PUR_SHIFT) + +/* NOD field position. */ +#define HC32_NOD_SHIFT 25U +/* NOD field mask. */ +#define HC32_NOD_MSK (1U << HC32_NOD_SHIFT) + +/* Out default level field position. */ +#define HC32_OTYPE_SHIFT 26U +/* Out default level field mask. */ +#define HC32_OTYPE_MSK (1U << HC32_OTYPE_SHIFT) + +/* DIREN field position. */ +#define HC32_DIREN_SHIFT 27U +/* DIREN(I/O select) field mask. */ +#define HC32_DIREN_MSK (1U << HC32_DIREN_SHIFT) + +/* STRENGTH field position. */ +#define HC32_STRENGTH_SHIFT 28U +/* STRENGTH field mask. */ +#define HC32_STRENGTH_MSK (3U << HC32_STRENGTH_SHIFT) + +/* I/O invert data */ +#define HC32_INVERT_SHIFT 30U +#define HC32_INVERT_MSK (1U << HC32_INVERT_SHIFT) + +/* schmitt or CMOS select */ +#define HC32_CINSEL_SHIFT 31U +#define HC32_CINSEL_MSK (1U << HC32_CINSEL_SHIFT) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_HC32_PINCTRL_H_ */ diff --git a/modules/Kconfig b/modules/Kconfig index b66955981fa04..63809a1183b83 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -48,6 +48,7 @@ source "modules/zcbor/Kconfig" source "modules/Kconfig.mcuboot" source "modules/Kconfig.intel" source "modules/hostap/Kconfig" +source "modules/Kconfig.xhsc" comment "Unavailable modules, please install those via the project manifest." diff --git a/modules/Kconfig.xhsc b/modules/Kconfig.xhsc new file mode 100644 index 0000000000000..342af8ca2b521 --- /dev/null +++ b/modules/Kconfig.xhsc @@ -0,0 +1,179 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HAS_HC32_DDL + bool + select HAS_CMSIS_CORE + depends on SOC_FAMILY_XHSC_HC32 + +if HAS_HC32_DDL + +config HC32_DDL_DEBUG + bool + help + If enable assert function in hc32_ddl drivers + +config HC32_LL_ICG + bool + default y + +config HC32_LL_ADC + bool + +config HC32_LL_AES + bool + +config HC32_LL_AOS + bool + +config HC32_LL_CAN + bool + +config HC32_LL_CLK + bool + default y + +config HC32_LL_CMP + bool + +config HC32_LL_CRC + bool + +config HC32_LL_CTC + bool + +config HC32_LL_DAC + bool + +config HC32_LL_DBGC + bool + +config HC32_LL_DCU + bool + +config HC32_LL_DMA + bool + +config HC32_LL_DMC + bool + +config HC32_LL_DVP + bool + +config HC32_LL_EFM + bool + default y + +config HC32_LL_EMB + bool + +config HC32_LL_ETH + bool + +config HC32_LL_EVENT_PORT + bool + +config HC32_LL_FCG + bool + default y + +config HC32_LL_FCM + bool + +config HC32_LL_FMAC + bool + +config HC32_LL_GPIO + bool + default y + +config HC32_LL_HASH + bool + +config HC32_LL_HRPWM + bool + +config HC32_LL_I2C + bool + +config HC32_LL_I2S + bool + +config HC32_LL_INTERRUPTS + bool + +config HC32_LL_INTERRUPTS_SHARE + bool + +config HC32_LL_KEYSCAN + bool + +config HC32_LL_MAU + bool + +config HC32_LL_MPU + bool + +config HC32_LL_NFC + bool + +config HC32_LL_OTS + bool + +config HC32_LL_PWC + bool + default y + +config HC32_LL_QSPI + bool + +config HC32_LL_RMU + bool + +config HC32_LL_RTC + bool + +config HC32_LL_SDIOC + bool + +config HC32_LL_SMC + bool + +config HC32_LL_SPI + bool + +config HC32_LL_SRAM + bool + default y + +config HC32_LL_SWDT + bool + +config HC32_LL_TMR0 + bool + +config HC32_LL_TMR2 + bool + +config HC32_LL_TMR4 + bool + +config HC32_LL_TMR6 + bool + +config HC32_LL_TMRA + bool + +config HC32_LL_TRNG + bool + +config HC32_LL_USART + bool + +config HC32_LL_USB + bool + +config HC32_LL_WDT + bool + +endif diff --git a/soc/xhsc/hc32/CMakeLists.txt b/soc/xhsc/hc32/CMakeLists.txt new file mode 100644 index 0000000000000..c6bb9a7896f33 --- /dev/null +++ b/soc/xhsc/hc32/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) + +zephyr_linker_sources( + ROM_START + SORT_KEY ${CONFIG_HC32_FLASH_CONFIG_OFFSET} + flash_config.ld +) + +zephyr_linker_sources( + RAM_SECTIONS + SORT_KEY _noinit_user + user_noinit.ld +) diff --git a/soc/xhsc/hc32/Kconfig b/soc/xhsc/hc32/Kconfig new file mode 100644 index 0000000000000..62d6bfef2a5ae --- /dev/null +++ b/soc/xhsc/hc32/Kconfig @@ -0,0 +1,11 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_XHSC_HC32 + bool + +if SOC_FAMILY_XHSC_HC32 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_XHSC_HC32 diff --git a/soc/xhsc/hc32/Kconfig.defconfig b/soc/xhsc/hc32/Kconfig.defconfig new file mode 100644 index 0000000000000..64180a98c8cda --- /dev/null +++ b/soc/xhsc/hc32/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_XHSC_HC32 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_XHSC_HC32 diff --git a/soc/xhsc/hc32/Kconfig.soc b/soc/xhsc/hc32/Kconfig.soc new file mode 100644 index 0000000000000..46954d27cd2fb --- /dev/null +++ b/soc/xhsc/hc32/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_XHSC_HC32 + bool + +config SOC_FAMILY + default "xhsc_hc32" if SOC_FAMILY_XHSC_HC32 + +rsource "*/Kconfig.soc" diff --git a/soc/xhsc/hc32/common/CMakeLists.txt b/soc/xhsc/hc32/common/CMakeLists.txt new file mode 100644 index 0000000000000..20b05f2b077c7 --- /dev/null +++ b/soc/xhsc/hc32/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/xhsc/hc32/common/pinctrl_soc.h b/soc/xhsc/hc32/common/pinctrl_soc.h new file mode 100644 index 0000000000000..98974f39d3614 --- /dev/null +++ b/soc/xhsc/hc32/common/pinctrl_soc.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * HC32 SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_ARM_XHSC_HC32_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_XHSC_HC32_COMMON_PINCTRL_SOC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Type for HC32 pin. */ +typedef uint32_t pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize pinmux field. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_HC32_PINCFG(node_id) \ + (((HC32_NO_PULL * DT_PROP(node_id, bias_disable)) << HC32_PUR_SHIFT) | \ + ((HC32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << HC32_PUR_SHIFT) | \ + ((HC32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << HC32_NOD_SHIFT) | \ + ((HC32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << HC32_NOD_SHIFT) | \ + ((HC32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << HC32_OTYPE_SHIFT) | \ + ((HC32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << HC32_OTYPE_SHIFT) | \ + ((HC32_INPUT_ENABLE * DT_PROP(node_id, input_enable)) << HC32_DIREN_SHIFT) | \ + ((HC32_OUTPUT_ENABLE * DT_PROP(node_id, output_enable)) << HC32_DIREN_SHIFT) | \ + (DT_ENUM_IDX(node_id, drive_strength) << HC32_STRENGTH_SHIFT)) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + DT_PROP_BY_IDX(node_id, prop, idx) | Z_PINCTRL_HC32_PINCFG(node_id), + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param state_prop State property name. + * @param idx State property entry index. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_XHSC_HC32_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/xhsc/hc32/flash_config.ld b/soc/xhsc/hc32/flash_config.ld new file mode 100644 index 0000000000000..e00db35a0bab0 --- /dev/null +++ b/soc/xhsc/hc32/flash_config.ld @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. = CONFIG_HC32_FLASH_CONFIG_OFFSET; +KEEP(*(.icg_sec)) +KEEP(*(".icg_sec.*")) diff --git a/soc/xhsc/hc32/hc32f4xx/CMakeLists.txt b/soc/xhsc/hc32/hc32f4xx/CMakeLists.txt new file mode 100644 index 0000000000000..2556e20aa5a1a --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/xhsc/hc32/hc32f4xx/Kconfig b/soc/xhsc/hc32/hc32f4xx/Kconfig new file mode 100644 index 0000000000000..6620e693c78d5 --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/Kconfig @@ -0,0 +1,14 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_HC32F4XX + select ARM + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_HC32_DDL + select SOC_RESET_HOOK + help + Enable support for xhsc hc32f4xx MCU series diff --git a/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig b/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig new file mode 100644 index 0000000000000..311a792d379b8 --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_HC32F4XX + +rsource "Kconfig.defconfig.hc32*" + +endif # SOC_SERIES_HC32F4XX diff --git a/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig.hc32f4a0 b/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig.hc32f4a0 new file mode 100644 index 0000000000000..0a749bc1efc73 --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/Kconfig.defconfig.hc32f4a0 @@ -0,0 +1,19 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_HC32F4A0 + +config NUM_IRQS + default 143 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_nodelabel_int_prop,clk_pll,clock-frequency) + +config HC32_FLASH_CONFIG_OFFSET + hex + default 0x400 + +endif # SOC_HC32F4A0 diff --git a/soc/xhsc/hc32/hc32f4xx/Kconfig.soc b/soc/xhsc/hc32/hc32f4xx/Kconfig.soc new file mode 100644 index 0000000000000..d2313bbce4dd9 --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/Kconfig.soc @@ -0,0 +1,23 @@ +# Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_HC32F4XX + bool + select SOC_FAMILY_XHSC_HC32 + help + Enable support for XHSC HC32F4XX MCU series + +config SOC_SERIES + default "hc32f4xx" if SOC_SERIES_HC32F4XX + +config SOC_HC32F460 + bool + select SOC_SERIES_HC32F4XX + +config SOC_HC32F4A0 + bool + select SOC_SERIES_HC32F4XX + +config SOC + default "hc32f460" if SOC_HC32F460 + default "hc32f4a0" if SOC_HC32F4A0 diff --git a/soc/xhsc/hc32/hc32f4xx/soc.c b/soc/xhsc/hc32/hc32f4xx/soc.c new file mode 100644 index 0000000000000..a51a430e3306c --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/soc.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int xhsc_hc32f4_init(void) +{ + LL_PERIPH_WE(LL_PERIPH_ALL); + + /* Enable Flash cache for both instruction and data */ +#if defined(HC32F460) + EFM_CacheCmd(ENABLE); +#elif defined(HC32F4A0) + EFM_PrefetchCmd(ENABLE); + EFM_DCacheCmd(ENABLE); + EFM_ICacheCmd(ENABLE); +#endif + + return 0; +} + +SYS_INIT(xhsc_hc32f4_init, PRE_KERNEL_1, 0); diff --git a/soc/xhsc/hc32/hc32f4xx/soc.h b/soc/xhsc/hc32/hc32f4xx/soc.h new file mode 100644 index 0000000000000..5511cdb88c4cb --- /dev/null +++ b/soc/xhsc/hc32/hc32f4xx/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/xhsc/hc32/soc.yml b/soc/xhsc/hc32/soc.yml new file mode 100644 index 0000000000000..c0788596bee11 --- /dev/null +++ b/soc/xhsc/hc32/soc.yml @@ -0,0 +1,7 @@ +family: +- name: xhsc_hc32 + series: + - name: hc32f4xx + socs: + - name: hc32f460 + - name: hc32f4a0 diff --git a/soc/xhsc/hc32/user_noinit.ld b/soc/xhsc/hc32/user_noinit.ld new file mode 100644 index 0000000000000..302a1a6e3c185 --- /dev/null +++ b/soc/xhsc/hc32/user_noinit.ld @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2024-2025, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Copied from linker.ld */ + +SECTION_DATA_PROLOGUE(.user_noinit,,) +{ + . = ALIGN(4); + __user_noinit_start = .; + *(.user_noinit) + *(".user_noinit.*") + + . = ALIGN(4); + __user_noinit_end = .; +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +__user_noinit_size = __user_noinit_end - __user_noinit_start; +__user_noinit_load_start = LOADADDR(.user_noinit); diff --git a/west.yml b/west.yml index 8ddf3001a042d..cc15e225cc715 100644 --- a/west.yml +++ b/west.yml @@ -279,6 +279,11 @@ manifest: path: modules/hal/wurthelektronik groups: - hal + - name: hal_xhsc + revision: a84e04900616f68097d80cda2e89eaa8af3afadd + path: modules/hal/xhsc + groups: + - hal - name: hal_xtensa revision: ba3f1ce6b066c3e40a8e6cad3fba0068ecfcd4ba path: modules/hal/xtensa