diff --git a/boards/renesas/ek_ra4c1/Kconfig.ek_ra4c1 b/boards/renesas/ek_ra4c1/Kconfig.ek_ra4c1 new file mode 100644 index 0000000000000..5254952211d8a --- /dev/null +++ b/boards/renesas/ek_ra4c1/Kconfig.ek_ra4c1 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4C1 + select SOC_R7FA4C1BD3CFP diff --git a/boards/renesas/ek_ra4c1/board.cmake b/boards/renesas/ek_ra4c1/board.cmake new file mode 100644 index 0000000000000..f8e89969ca5ba --- /dev/null +++ b/boards/renesas/ek_ra4c1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4C1BD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4c1/board.yml b/boards/renesas/ek_ra4c1/board.yml new file mode 100644 index 0000000000000..130792c3d0e7d --- /dev/null +++ b/boards/renesas/ek_ra4c1/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_ra4c1 + full_name: RA4C1 Evaluation Kit + vendor: renesas + socs: + - name: r7fa4c1bd3cfp diff --git a/boards/renesas/ek_ra4c1/doc/ek_ra4c1.webp b/boards/renesas/ek_ra4c1/doc/ek_ra4c1.webp new file mode 100644 index 0000000000000..60f4e688ab409 Binary files /dev/null and b/boards/renesas/ek_ra4c1/doc/ek_ra4c1.webp differ diff --git a/boards/renesas/ek_ra4c1/doc/index.rst b/boards/renesas/ek_ra4c1/doc/index.rst new file mode 100644 index 0000000000000..b5fb42f66c08f --- /dev/null +++ b/boards/renesas/ek_ra4c1/doc/index.rst @@ -0,0 +1,123 @@ +.. zephyr:board:: ek_ra4c1 + +Overview +******** + +The EK-RA4C1, an Evaluation Kit for the RA4 Series, enables users to seamlessly evaluate +the features of the RA4C1 MCU group and develop embedded systems applications using +Flexible Software Package (FSP) and the e2 studio IDE. The users can use rich on-board +features along with their choice of popular ecosystems add-ons to bring their big ideas to life. + +The key features of the EK-RA4C1 board are categorized in three groups (consistent with +the architecture of the kit) as follows: + +**Renesas RA4C1 Microcontroller Group** + +- R7FA4C1BD3CFP MCU (referred to as RA MCU) +- 80 MHz, Arm® Cortex®-M33 core +- 512 KB Code Flash, 96 KB SRAM +- 100 pins, LQFP package +- Native pin access through 3 x 26-pin headers (not populated) +- Tamper Detection embedded into J4 +- Segment LCD Board Interface +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources – RA MCU oscillator and sub-clock oscillator crystals, +providing precision 8.000 MHz and 32,768 Hz reference clocks. Additional low-precision +clocks are available internal to the RA MCU + +**System Control and Ecosystem Access** + +- Two 5 V input sources + + - USB (Debug) + - External Power Supply 2-pin header (not populated) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD) + - Debug out (SWD, SWO and JTAG) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove® system (I2C/Analog) connectors (not populated) + - SparkFun® Qwiic® connector (not populated) + - Two Digilent PmodTM (SPI, UART and I2C) connectors + - Arduino™ (UNO R3) connector + - MikroElektronikaTM mikroBUS connector (not populated) + +- MCU boot configuration jumper +- Low Voltage Mode voltage input and operation + +**Special Feature Access** +- 32 MB (256 Mb) External Quad-SPI Flash +- CAN-FD (3-pin header) +- External Battery Connector +- Configuration Switch + +Hardware +******** + +Detailed hardware features can be found at: +- RA4C1 MCU: `RA4C1 Group User's Manual Hardware`_ +- EK-RA4C1 board: `EK-RA4C1 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4c1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4C1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4C1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +References +********** +- `EK-RA4C1 Website`_ +- `RA4C1 MCU group Website`_ + +.. _EK-RA4C1 Website: + http://www.renesas.com/ek-ra4c1 + +.. _RA4C1 MCU group Website: + http://www.renesas.com/ra4c1 + +.. _EK-RA4C1 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4c1-v1-users-manual + +.. _RA4C1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra4c1-group-users-manual-hardware diff --git a/boards/renesas/ek_ra4c1/ek_ra4c1-pinctrl.dtsi b/boards/renesas/ek_ra4c1/ek_ra4c1-pinctrl.dtsi new file mode 100644 index 0000000000000..0755444121e79 --- /dev/null +++ b/boards/renesas/ek_ra4c1/ek_ra4c1-pinctrl.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci4_default: sci4_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm4_default: pwm4_default { + group1 { + /* GTIOC4A GTIOC4B */ + psels = , + ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; +}; diff --git a/boards/renesas/ek_ra4c1/ek_ra4c1.dts b/boards/renesas/ek_ra4c1/ek_ra4c1.dts new file mode 100644 index 0000000000000..edbf989b45dcb --- /dev/null +++ b/boards/renesas/ek_ra4c1/ek_ra4c1.dts @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "ek_ra4c1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4C1"; + compatible = "renesas,ra4c1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash-controller = &flash; + zephyr,flash = &flash0; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,canbus = &canfd0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport6 10 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport5 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + + button1: s2 { + gpios = <&ioport1 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdt; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + clocks = <&xtal>; + div = <1>; + mul = <10 0>; + status = "okay"; +}; + +&canfdclk { + clocks = <&pll>; + div = <2>; + status = "okay"; +}; + +&sci4 { + pinctrl-0 = <&sci4_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart4: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&spi0 { + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc0 { + interrupts = <38 1>; + interrupt-names = "scanend"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq0 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq15 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4_default>; + pinctrl-names = "default"; + interrupts = <43 1>, <44 1>; + interrupt-names = "gtioca", "overflow"; + divider = ; + status = "okay"; +}; + +&iic1 { + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <45 1>, <46 1>, <47 1>, <48 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&canfd_global { + interrupts = <49 1>, <50 1>; + interrupt-names = "rxf", "glerr"; + status = "okay"; + + canfd0 { + interrupts = <51 12>, <52 12>, <53 12>; + interrupt-names = "err", "tx", "rx"; + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + rx-max-filters = <16>; + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; +}; + +&wdt { + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra4c1/ek_ra4c1.yaml b/boards/renesas/ek_ra4c1/ek_ra4c1.yaml new file mode 100644 index 0000000000000..31cec493f01fe --- /dev/null +++ b/boards/renesas/ek_ra4c1/ek_ra4c1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4c1 +name: Renesas EK-RA4C1 +type: mcu +arch: arm +ram: 96 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4c1/ek_ra4c1_defconfig b/boards/renesas/ek_ra4c1/ek_ra4c1_defconfig new file mode 100644 index 0000000000000..f26066de3e521 --- /dev/null +++ b/boards/renesas/ek_ra4c1/ek_ra4c1_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y diff --git a/dts/arm/renesas/ra/ra4/r7fa4c1bd3cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4c1bd3cfp.dtsi new file mode 100644 index 0000000000000..e4db3103afa4b --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4c1bd3cfp.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash: flash-controller@407e0000 { + compatible = "renesas,ra-flash-hp-controller"; + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <49 1>, <50 1>; + interrupt-names = "frdyi", "fiferr"; + flash-hardware-version = <4>; + #erase-block-cells = <2>; + + flash0: flash@0 { + compatible = "renesas,ra-nv-code-flash"; + reg = <0x0 DT_SIZE_K(512)>; + write-block-size = <8>; + erase-block-size = <2048>; + erase-blocks = <&flash 256 2048>; + programming-enable; + }; + + flash1: flash@8000000 { + compatible = "renesas,ra-nv-data-flash"; + reg = <0x8000000 DT_SIZE_K(8)>; + write-block-size = <1>; + erase-block-size = <256>; + programming-enable; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4c1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4c1bx.dtsi new file mode 100644 index 0000000000000..77c0dd78071c7 --- /dev/null +++ b/dts/arm/renesas/ra/ra4/r7fa4c1bx.dtsi @@ -0,0 +1,864 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + interrupt-parent = <&nvic>; + + system: system@4001e000 { + compatible = "renesas,ra-system"; + reg = <0x4001e000 0x1000>; + status = "okay"; + }; + + elc: elc@40082000 { + compatible = "renesas,ra-elc"; + reg = <0x40082000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(96)>; + }; + + ioport0: gpio@4001f000 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f000 0x20>; + port = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport1: gpio@4001f020 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f020 0x20>; + port = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport2: gpio@4001f040 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f040 0x20>; + port = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport3: gpio@4001f060 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f060 0x20>; + port = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport4: gpio@4001f080 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f080 0x20>; + port = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport5: gpio@4001f0a0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f0a0 0x20>; + port = <5>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport6: gpio@4001f0c0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f0c0 0x20>; + port = <6>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport7: gpio@4001f0e0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f0e0 0x20>; + port = <7>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + ioport8: gpio@4001f0f0 { + compatible = "renesas,ra-gpio-ioport"; + reg = <0x4001f0f0 0x20>; + port = <8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + pinctrl: pin-controller@4001f800 { + compatible = "renesas,ra-pinctrl-pfs"; + reg = <0x4001f800 0x3c0>; + status = "okay"; + }; + + sci0: sci@40118000 { + compatible = "renesas,ra-sci"; + reg = <0x40118000 0x100>; + clocks = <&pclka MSTPB 31>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <0>; + status = "disabled"; + }; + }; + + sci1: sci1@40118100 { + compatible = "renesas,ra-sci"; + reg = <0x40118100 0x100>; + clocks = <&pclka MSTPB 30>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <1>; + status = "disabled"; + }; + }; + + sci3: sci3@40118300 { + compatible = "renesas,ra-sci"; + reg = <0x40118300 0x100>; + clocks = <&pclka MSTPB 28>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <3>; + status = "disabled"; + }; + }; + + sci4: sci4@40118400 { + compatible = "renesas,ra-sci"; + reg = <0x40118400 0x100>; + clocks = <&pclka MSTPB 27>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <4>; + status = "disabled"; + }; + }; + + sci5: sci@40118500 { + compatible = "renesas,ra-sci"; + reg = <0x40118500 0x100>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci9: sci@40118900 { + compatible = "renesas,ra-sci"; + reg = <0x40118900 0x100>; + clocks = <&pclka MSTPB 22>; + status = "disabled"; + + uart { + compatible = "renesas,ra-sci-uart"; + channel = <9>; + status = "disabled"; + }; + }; + + spi0: spi@4011a000 { + compatible = "renesas,ra-spi"; + #address-cells = <1>; + #size-cells = <0>; + channel = <0>; + reg = <0x4011a000 0x100>; + status = "disabled"; + }; + + spi1: spi@4011a100 { + compatible = "renesas,ra-spi"; + #address-cells = <1>; + #size-cells = <0>; + channel = <1>; + reg = <0x4011a100 0x100>; + status = "disabled"; + }; + + spi2: spi@4011a200 { + compatible = "renesas,ra-spi"; + #address-cells = <1>; + #size-cells = <0>; + channel = <0>; + reg = <0x4011a200 0x100>; + status = "disabled"; + }; + + iic0: iic0@4009f000 { + compatible = "renesas,ra-iic"; + channel = <0>; + reg = <0x4009f000 0x100>; + status = "disabled"; + }; + + iic1: iic1@4009f100 { + compatible = "renesas,ra-iic"; + channel = <1>; + reg = <0x4009f100 0x100>; + status = "disabled"; + }; + + adc0: adc@40170000 { + compatible = "renesas,ra-adc"; + reg = <0x40170000 0x100>; + #io-channel-cells = <1>; + vref-mv = <3300>; + channel-available-mask = <0x3fe007f>; + status = "disabled"; + }; + + pwm0: pwm0@40169000 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 31>; + reg = <0x40169000 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm1@40169100 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 30>; + reg = <0x40169100 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm2@40169200 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 29>; + reg = <0x40169200 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm3@40169300 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 28>; + reg = <0x40169300 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm4@40169400 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 27>; + reg = <0x40169400 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm5@40169500 { + compatible = "renesas,ra-pwm"; + divider = ; + channel = ; + clocks = <&pclkd MSTPE 26>; + reg = <0x40169500 0x100>; + #pwm-cells = <3>; + status = "disabled"; + }; + + canfd_global: canfd_global@400b0000 { + compatible = "renesas,ra-canfd-global"; + clocks = <&pclkb 0 0>, <&pclka 0 0>; + clock-names = "opclk", "ramclk"; + dll-max-freq = ; + reg = <0x400b0000 0x2000>; + status = "disabled"; + + canfd0: canfd0 { + compatible = "renesas,ra-canfd"; + channel = <0>; + clocks = <&canfdclk MSTPC 27>; + clock-names = "dllclk"; + status = "disabled"; + }; + }; + + wdt: wdt@40083400 { + compatible = "renesas,ra-wdt"; + reg = <0x40083400 0xc>; + clocks = <&pclkb 0 0>; + status = "disabled"; + }; + + agt0: agtw@400e8000 { + compatible = "renesas,ra-agt"; + channel = <0>; + reg = <0x400e8000 0x100>; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <0>; + renesas,resolution = <32>; + status = "disabled"; + + counter { + compatible = "renesas,ra-agt-counter"; + status = "disabled"; + }; + }; + + agt1: agtw@400e8100 { + compatible = "renesas,ra-agt"; + channel = <1>; + reg = <0x400e8100 0x100>; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <0>; + renesas,resolution = <32>; + status = "disabled"; + + counter { + compatible = "renesas,ra-agt-counter"; + status = "disabled"; + }; + }; + + port_irq0: external-interrupt@40006000 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006000 0x1>; + channel = <0>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq1: external-interrupt@40006001 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006001 0x1>; + channel = <1>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq2: external-interrupt@40006002 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006002 0x1>; + channel = <2>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq3: external-interrupt@40006003 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006003 0x1>; + channel = <3>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq4: external-interrupt@40006004 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006004 0x1>; + channel = <4>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq5: external-interrupt@40006005 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006005 0x1>; + channel = <5>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq6: external-interrupt@40006006 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006006 0x1>; + channel = <6>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq7: external-interrupt@40006007 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006007 0x1>; + channel = <7>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq8: external-interrupt@40006008 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006008 0x1>; + channel = <8>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq9: external-interrupt@40006009 { + compatible = "renesas,ra-external-interrupt"; + reg = <0x40006009 0x1>; + channel = <9>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq10: external-interrupt@4000600a { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600a 0x1>; + channel = <10>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq11: external-interrupt@4000600b { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600b 0x1>; + channel = <11>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq12: external-interrupt@4000600c { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600c 0x1>; + channel = <12>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq13: external-interrupt@4000600d { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600d 0x1>; + channel = <13>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq14: external-interrupt@4000600e { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600e 0x1>; + channel = <14>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + port_irq15: external-interrupt@4000600f { + compatible = "renesas,ra-external-interrupt"; + reg = <0x4000600f 0x1>; + channel = <15>; + renesas,sample-clock-div = <64>; + #port-irq-cells = <0>; + status = "disabled"; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@100a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0xc>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0xc>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0xc>; + status = "okay"; + }; + }; + }; + + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,ra-cgc-external-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + clocks = <&xtal>; + div = <1>; + mul = <10 0>; + status = "disabled"; + }; + + pllrtc: pllrtc { + compatible = "renesas,ra-cgc-pllrtc"; + #clock-cells = <0>; + + /* PLLRTC */ + clocks = <&subclk>; + mul = <793 0>; + status = "disabled"; + }; + + utasel: utasel { + compatible = "renesas,ra-cgc-utasel"; + #clock-cells = <0>; + + /* UTESEL */ + clocks = <&hoco>; + status = "disabled"; + }; + + pclkblock: pclkblock@40084000 { + compatible = "renesas,ra-cgc-pclk-block"; + reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, + <0x4008400c 4>, <0x40084010 4>; + reg-names = "MSTPA", "MSTPB","MSTPC", + "MSTPD", "MSTPE"; + #clock-cells = <0>; + clocks = <&pll>; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clock-frequency = <80000000>; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + + uarta0: uarta0 { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + clocks = <&utasel>; + status = "disabled"; + }; + + uarta1: uarta1 { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + clocks = <&utasel>; + status = "disabled"; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; + +&ioport0 { + port-irqs = <&port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq10 &port_irq11>; + port-irq-names = "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq11"; + port-irq6-pins = <0>; + port-irq7-pins = <1>; + port-irq8-pins = <2>; + port-irq9-pins = <4>; + port-irq10-pins = <10>; + port-irq11-pins = <11>; +}; + +&ioport1 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq4 &port_irq10>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq4", + "port-irq10"; + port-irq0-pins = <5>; + port-irq1-pins = <1 4>; + port-irq2-pins = <0>; + port-irq3-pins = <10>; + port-irq4-pins = <11>; + port-irq10-pins = <13>; +}; + +&ioport2 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq12>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq12"; + port-irq0-pins = <6>; + port-irq1-pins = <5>; + port-irq2-pins = <13>; + port-irq3-pins = <12>; + port-irq12-pins = <8>; +}; + +&ioport3 { + port-irqs = <&port_irq5 &port_irq6 + &port_irq8 &port_irq9>; + port-irq-names = "port-irq5", + "port-irq6", + "port-irq8", + "port-irq9"; + port-irq5-pins = <2>; + port-irq6-pins = <1>; + port-irq8-pins = <5>; + port-irq9-pins = <4>; +}; + +&ioport4 { + port-irqs = <&port_irq0 &port_irq4 &port_irq5 + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; + port-irq-names = "port-irq0", + "port-irq4", + "port-irq5", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq14", + "port-irq15"; + port-irq0-pins = <0>; + port-irq4-pins = <2 11>; + port-irq5-pins = <1 10>; + port-irq6-pins = <9>; + port-irq7-pins = <8>; + port-irq8-pins = <15>; + port-irq9-pins = <14>; + port-irq14-pins = <3>; + port-irq15-pins = <4>; +}; + +&ioport5 { + port-irqs = <&port_irq11 &port_irq12 &port_irq13 + &port_irq14 &port_irq15>; + port-irq-names = "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq15"; + port-irq11-pins = <1>; + port-irq12-pins = <2>; + port-irq13-pins = <6>; + port-irq14-pins = <5>; + port-irq15-pins = <13>; +}; + +&ioport7 { + port-irqs = <&port_irq11>; + port-irq-names = "port-irq11"; + port-irq11-pins = <8>; +}; diff --git a/dts/bindings/clock/renesas,ra-cgc-pllrtc.yaml b/dts/bindings/clock/renesas,ra-cgc-pllrtc.yaml new file mode 100644 index 0000000000000..25ca5a821f022 --- /dev/null +++ b/dts/bindings/clock/renesas,ra-cgc-pllrtc.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA Clock Generation Circuit PLLRTC Clock + +compatible: "renesas,ra-cgc-pllrtc" + +include: [clock-controller.yaml, base.yaml] + +properties: + clocks: + required: true + mul: + required: true + type: array + + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/renesas,ra-cgc-utasel.yaml b/dts/bindings/clock/renesas,ra-cgc-utasel.yaml new file mode 100644 index 0000000000000..38d1380c1325d --- /dev/null +++ b/dts/bindings/clock/renesas,ra-cgc-utasel.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA Clock Generation Circuit UTASEL Clock + +compatible: "renesas,ra-cgc-utasel" + +include: [clock-controller.yaml, base.yaml] + +properties: + clocks: + required: true + + "#clock-cells": + const: 0 diff --git a/samples/boards/renesas/elc/boards/ek_ra4c1.overlay b/samples/boards/renesas/elc/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..1eb51154b859d --- /dev/null +++ b/samples/boards/renesas/elc/boards/ek_ra4c1.overlay @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + aliases { + pwm-gen = &pwm0; + pwm-cap = &pwm4; + elc-link = &elc; + }; +}; + +&pinctrl { + pwm0_default: pwm0_default { + group1 { + /* GTIOC0A*/ + psels = ; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + interrupts = <62 1>, <63 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&pwm0 { + renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + renesas-elc-names = "start", "stop"; + start-source = "GPT_SOURCE_GPT_A"; + stop-source = "GPT_SOURCE_GPT_B"; + status = "okay"; +}; + +&elc { + status = "okay"; +}; diff --git a/samples/drivers/counter/alarm/boards/ek_ra4c1.overlay b/samples/drivers/counter/alarm/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..4a695dff1f27d --- /dev/null +++ b/samples/drivers/counter/alarm/boards/ek_ra4c1.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <62 1>, <63 1>; + interrupt-names = "agti", "agtcmai"; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <4>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; diff --git a/soc/renesas/ra/ra4c1/CMakeLists.txt b/soc/renesas/ra/ra4c1/CMakeLists.txt new file mode 100644 index 0000000000000..9bada9b094e99 --- /dev/null +++ b/soc/renesas/ra/ra4c1/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4c1/Kconfig b/soc/renesas/ra/ra4c1/Kconfig new file mode 100644 index 0000000000000..6daafe2eabb2f --- /dev/null +++ b/soc/renesas/ra/ra4c1/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4C1 + select ARM + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M33 + select HAS_RENESAS_RA_FSP + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select ARMV8_M_DSP + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/ra/ra4c1/Kconfig.defconfig b/soc/renesas/ra/ra4c1/Kconfig.defconfig new file mode 100644 index 0000000000000..0bc773d1d09ed --- /dev/null +++ b/soc/renesas/ra/ra4c1/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4C1 + +config NUM_IRQS + default 64 + +DT_ICLK_PATH := $(dt_nodelabel_path,iclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + +endif # SOC_SERIES_RA4C1 diff --git a/soc/renesas/ra/ra4c1/Kconfig.soc b/soc/renesas/ra/ra4c1/Kconfig.soc new file mode 100644 index 0000000000000..b1a6831ad6fca --- /dev/null +++ b/soc/renesas/ra/ra4c1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4C1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4C1 series + +config SOC_R7FA4C1BD3CFP + bool + select SOC_SERIES_RA4C1 + help + R7FA4C1BD3CFP + +config SOC_SERIES + default "ra4c1" if SOC_SERIES_RA4C1 + +config SOC + default "r7fa4c1bd3cfp" if SOC_R7FA4C1BD3CFP diff --git a/soc/renesas/ra/ra4c1/ram_sections.ld b/soc/renesas/ra/ra4c1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4c1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4c1/sections.ld b/soc/renesas/ra/ra4c1/sections.ld new file mode 100644 index 0000000000000..b9f1e8bdeab99 --- /dev/null +++ b/soc/renesas/ra/ra4c1/sections.ld @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_conf)) + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)),) +{ + KEEP(*(.option_setting_ofs0)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel, DT_REG_ADDR(DT_NODELABEL(option_setting_dualsel)),) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sec)),) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_banksel_sec)),) +{ + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_bps_sec)),) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_pbps_sec)),) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sel)),) +{ + KEEP(*(.option_setting_ofs1_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_banksel_sel)),) +{ + KEEP(*(.option_setting_banksel_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_bps_sel)),) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#endif /* option_setting_ofs_conf */ diff --git a/soc/renesas/ra/ra4c1/soc.c b/soc/renesas/ra/ra4c1/soc.c new file mode 100644 index 0000000000000..ea781fafd7594 --- /dev/null +++ b/soc/renesas/ra/ra4c1/soc.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA4C1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 4; i++) { + g_protect_counters[i] = 0; + } + +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; +} diff --git a/soc/renesas/ra/ra4c1/soc.h b/soc/renesas/ra/ra4c1/soc.h new file mode 100644 index 0000000000000..925b6a248fe08 --- /dev/null +++ b/soc/renesas/ra/ra4c1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA4C1 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA4C1_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA4C1_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA4C1_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index 5dbbe26097d37..846034b9dda89 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -40,6 +40,9 @@ family: - name: ra4w1 socs: - name: r7fa4w1ad2cng + - name: ra4c1 + socs: + - name: r7fa4c1bd3cfp - name: ra6m1 socs: - name: r7fa6m1ad3cfp diff --git a/tests/boards/renesas/elc/boards/ek_ra4c1.overlay b/tests/boards/renesas/elc/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..157efbfb4e977 --- /dev/null +++ b/tests/boards/renesas/elc/boards/ek_ra4c1.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + elc-link = &elc; + }; +}; + +&elc { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..71c6e206e6146 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + io-channels = <&adc0 0>; + reference-mv = <3300>; + expected-accuracy = <32>; + }; +}; + +&adc0{ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..9aab1db0db5d2 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/ { + zephyr,user { + io-channels = <&adc0 0>, <&adc0 2>; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,resolution = <12>; + zephyr,acquisition-time = ; + zephyr,vref-mv = <3300>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,resolution = <12>; + zephyr,acquisition-time = ; + zephyr,vref-mv = <3300>; + }; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/ek_ra4c1.overlay b/tests/drivers/counter/counter_basic_api/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..0108a97db08e5 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/ek_ra4c1.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <62 1>, <63 1>; + interrupt-names = "agti", "agtcmai"; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <0>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.conf new file mode 100644 index 0000000000000..73896d54bcfda --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SENSOR_GY271_HMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..0dfb29aaae618 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4c1.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &iic1; + gy271 = &iic1; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..b2904c6067138 --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, + <&pwm4 0 0 PWM_POLARITY_NORMAL>; + }; +}; + +&pinctrl { + pwm0_default: pwm0_default { + group1 { + /* GTIOC0A*/ + psels = ; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + interrupts = <62 1>, <63 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.conf new file mode 100644 index 0000000000000..a231e084368be --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI_LOOPBACK_MODE_LOOP=y +CONFIG_SPI_INTERRUPT=y +CONFIG_SPI_RA_DTC=y diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..59314554dc355 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4c1.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi0 { + rx-dtc; + tx-dtc; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay new file mode 100644 index 0000000000000..b919990829d6b --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + interrupts = <60 1>, <61 1>, <62 1>, <63 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + dut: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/west.yml b/west.yml index fa531bc177c38..858b3321ca0f0 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 1ac809b55389ba3ce09dd1fbf2477a034134d112 + revision: pull/124/head groups: - hal - name: hal_rpi_pico