diff --git a/boards/firefly/roc_rk3588/Kconfig.roc_rk3588 b/boards/firefly/roc_rk3588/Kconfig.roc_rk3588 new file mode 100644 index 0000000000000..bb1d25b3a0ea1 --- /dev/null +++ b/boards/firefly/roc_rk3588/Kconfig.roc_rk3588 @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ROC_RK3588 + select SOC_RK3588 diff --git a/boards/firefly/roc_rk3588/board.yml b/boards/firefly/roc_rk3588/board.yml new file mode 100644 index 0000000000000..fbdf36cd6c1a8 --- /dev/null +++ b/boards/firefly/roc_rk3588/board.yml @@ -0,0 +1,8 @@ +board: + name: roc_rk3588 + full_name: ROC-RK3588 (Quad-core Cortex-A55) + vendor: firefly + socs: + - name: rk3588 + variants: + - name: smp diff --git a/boards/firefly/roc_rk3588/doc/index.rst b/boards/firefly/roc_rk3588/doc/index.rst new file mode 100644 index 0000000000000..ccaf835e427f0 --- /dev/null +++ b/boards/firefly/roc_rk3588/doc/index.rst @@ -0,0 +1,137 @@ +.. zephyr:board:: roc_rk3588 + +Overview +******** + +The ROC-RK3588 is an Octa-Core 64-Bit Mini Computer powered by Rockchip RK3588, which supports up to 32GB RAM. +It features M.2 PCIe3.0 interface for NVMe SSD expansion and provides rich interfaces including HDMI 2.1, DP1.4. +Supporting WiFi 6 wireless transmission and Gigabit Ethernet, it enables high-speed network connectivity. + +RK3588 octa-core 64-bit processor (4×Cortex-A76+4×Cortex-A55), with 8nm lithography process, +has frequency up to 2.4GHz. Integrated with ARM Mali-G610 MP4 quad-core GPU and built-in AI accelerator NPU, +it provides 6Tops computing power. Zephyr OS is ported to run on it. + + +- Board features: + + - RAM: Up to 32GB LPDDR4/LPDDR4x/LPDDR5 + - Storage: + + - Up to 128GB eMMC + - M.2 PCIe3.0 NVMe SSD (2242/2260/2280) + - TF-Card Slot + - Wireless: + + - Supports WiFi 6 (802.11 a/b/g/n/ac/ax) + - Supports BT 5.0 + - Display: + + - HDMI 2.1 (8K@60fps) + - HDMI 2.0 (4K@60fps) + - DP 1.4 (8K@30fps) + - USB: + + - Two USB 3.0 + - One USB 2.0 + - One USB-C (USB3.0 OTG / DP1.4) + - Network: + + - 1x 1000Mbps Ethernet (RJ45) + - Debug: + + - UART debug ports for board + - Other: + + - NPU with 6 TOPS computing power + - ARM Mali-G610 MP4 quad-core GPU + - Support OpenGL ES3.2/OpenCL 2.2/Vulkan1.1 + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A76 cores run up to 2.4 GHz and Cortex-A55 cores run up to 1.8 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Use U-Boot to load the zephyr.bin to the memory and kick it: + +.. code-block:: console + + tftp 0x50000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x50000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3588 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-2356-gfe6366b8045a *** + thread_a: Hello World from cpu 0 on roc_rk3588! + thread_b: Hello World from cpu 0 on roc_rk3588! + thread_a: Hello World from cpu 0 on roc_rk3588! + thread_b: Hello World from cpu 0 on roc_rk3588! + + +``roc_rk3588//smp`` support, use this configuration to run Zephyr smp applications and subsys tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3588//smp + :goals: run + +This will build an image with the shell_module sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-2356-gfe6366b8045a *** + I/TC: Secondary CPU 1 initializing + I/TC: Secondary CPU 1 switching to normal world boot + Secondary CPU core 1 (MPID:0x100) is up + I/TC: Secondary CPU 2 initializing + I/TC: Secondary CPU 2 switching to normal world boot + Secondary CPU core 2 (MPID:0x200) is up + I/TC: Secondary CPU 3 initializing + I/TC: Secondary CPU 3 switching to normal world boot + Secondary CPU core 3 (MPID:0x300) is up + thread_a: Hello World from cpu 0 on roc_rk3588! + thread_b: Hello World from cpu 1 on roc_rk3588! + thread_a: Hello World from cpu 0 on roc_rk3588! + thread_b: Hello World from cpu 1 on roc_rk3588! + +References +========== + +More information can refer to Firefly official website: +`Firefly website`_. + +.. _Firefly website: + https://en.t-firefly.com/product/industry/rocrk3588pc.html?theme=pc diff --git a/boards/firefly/roc_rk3588/roc_rk3588.dts b/boards/firefly/roc_rk3588/roc_rk3588.dts new file mode 100644 index 0000000000000..ab2e1212ea666 --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588.dts @@ -0,0 +1,36 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Firefly ROC-RK3588"; + compatible = "rockchip,rk3588"; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &dram; + }; + + dram: memory@50000000 { + compatible = "mmio-sram"; + device_type = "memory"; + reg = <0x50000000 DT_SIZE_M(1)>; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <1500000>; +}; + +&uart3 { + status = "disabled"; + current-speed = <115200>; +}; diff --git a/boards/firefly/roc_rk3588/roc_rk3588.yaml b/boards/firefly/roc_rk3588/roc_rk3588.yaml new file mode 100644 index 0000000000000..3305b571c84e1 --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588.yaml @@ -0,0 +1,12 @@ +identifier: roc_rk3588 +name: Rockchip ROC RK3588 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/firefly/roc_rk3588/roc_rk3588_defconfig b/boards/firefly/roc_rk3588/roc_rk3588_defconfig new file mode 100644 index 0000000000000..afc5f093789ae --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588_defconfig @@ -0,0 +1,20 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM_ARCH_TIMER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# ARMv8 NS world with cache management +CONFIG_ARMV8_A_NS=y +CONFIG_CACHE_MANAGEMENT=y + +CONFIG_TICKLESS_KERNEL=y diff --git a/boards/firefly/roc_rk3588/roc_rk3588_smp.dts b/boards/firefly/roc_rk3588/roc_rk3588_smp.dts new file mode 100644 index 0000000000000..3a0c27d13e35c --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588_smp.dts @@ -0,0 +1,6 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "roc_rk3588.dts" diff --git a/boards/firefly/roc_rk3588/roc_rk3588_smp.yaml b/boards/firefly/roc_rk3588/roc_rk3588_smp.yaml new file mode 100644 index 0000000000000..fdf59e56fca5e --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588_smp.yaml @@ -0,0 +1,14 @@ +identifier: roc_rk3568_pc/rk3568/smp +name: Rockchip ROC RK3568 PC SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/firefly/roc_rk3588/roc_rk3588_smp_defconfig b/boards/firefly/roc_rk3588/roc_rk3588_smp_defconfig new file mode 100644 index 0000000000000..73c019d1e22bc --- /dev/null +++ b/boards/firefly/roc_rk3588/roc_rk3588_smp_defconfig @@ -0,0 +1,30 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM_ARCH_TIMER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# ARMv8 NS world with cache management +CONFIG_ARMV8_A_NS=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE=y + +CONFIG_TICKLESS_KERNEL=y + +# SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_MAX_THREAD_BYTES=4 + +# PSCI support +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y diff --git a/dts/arm64/rockchip/rk3588.dtsi b/dts/arm64/rockchip/rk3588.dtsi new file mode 100644 index 0000000000000..5f2488d86cdac --- /dev/null +++ b/dts/arm64/rockchip/rk3588.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright 2020 NXP + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rk3588"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + clock-frequency = <24000000>; + reg = <0x000>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + }; + + gic: interrupt-controller@fe600000 { + #address-cells = <1>; + compatible = "arm,gic-v3","arm,gic"; + #interrupt-cells = <4>; + interrupt-controller; + + reg = <0xfe600000 0x10000>, /* GICD */ + <0xfe680000 0x100000>; /* GICR */ + status = "okay"; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "ns16550"; + reg = <0xfeb50000 0x100>; + interrupts = ; + clock-frequency = <12000000>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "ns16550"; + reg = <0xfeb60000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + status = "disabled"; + }; +}; diff --git a/soc/rockchip/rk35/CMakeLists.txt b/soc/rockchip/rk35/CMakeLists.txt index b45e8592a61da..7fe70086e818f 100644 --- a/soc/rockchip/rk35/CMakeLists.txt +++ b/soc/rockchip/rk35/CMakeLists.txt @@ -5,4 +5,6 @@ if(CONFIG_SOC_RK3568) add_subdirectory(rk3568) elseif(CONFIG_SOC_RK3588S) add_subdirectory(rk3588s) +elseif(CONFIG_SOC_RK3588) + add_subdirectory(rk3588) endif() diff --git a/soc/rockchip/rk35/rk3588/CMakeLists.txt b/soc/rockchip/rk35/rk3588/CMakeLists.txt new file mode 100644 index 0000000000000..22fc2aa11bee4 --- /dev/null +++ b/soc/rockchip/rk35/rk3588/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/rockchip/rk35/rk3588/Kconfig b/soc/rockchip/rk35/rk3588/Kconfig new file mode 100644 index 0000000000000..ec00c560f9083 --- /dev/null +++ b/soc/rockchip/rk35/rk3588/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RK3588 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER + +config SOC_PART_NUMBER + default "RK3588" if SOC_RK3588 diff --git a/soc/rockchip/rk35/rk3588/Kconfig.defconfig b/soc/rockchip/rk35/rk3588/Kconfig.defconfig new file mode 100644 index 0000000000000..27ecfa6a5b1c4 --- /dev/null +++ b/soc/rockchip/rk35/rk3588/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RK3588 + +rsource "Kconfig.defconfig.rk3588" + +endif # SOC_SERIES_RK3588 diff --git a/soc/rockchip/rk35/rk3588/Kconfig.defconfig.rk3588 b/soc/rockchip/rk35/rk3588/Kconfig.defconfig.rk3588 new file mode 100644 index 0000000000000..63035588e2595 --- /dev/null +++ b/soc/rockchip/rk35/rk3588/Kconfig.defconfig.rk3588 @@ -0,0 +1,19 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RK3588 + +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 + +config NUM_IRQS + default 370 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif diff --git a/soc/rockchip/rk35/rk3588/Kconfig.soc b/soc/rockchip/rk35/rk3588/Kconfig.soc new file mode 100644 index 0000000000000..86e122668618b --- /dev/null +++ b/soc/rockchip/rk35/rk3588/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RK3588 + bool + select SOC_SERIES_RK35 + +config SOC + default "rk3588" if SOC_RK3588 diff --git a/soc/rockchip/rk35/rk3588/mmu_regions.c b/soc/rockchip/rk35/rk3588/mmu_regions.c new file mode 100644 index 0000000000000..c183ad886e2fe --- /dev/null +++ b/soc/rockchip/rk35/rk3588/mmu_regions.c @@ -0,0 +1,27 @@ +/* + * Copyright 2020 NXP + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/rockchip/soc.yml b/soc/rockchip/soc.yml index 777bd05a9d3c0..371d79e8bf44c 100644 --- a/soc/rockchip/soc.yml +++ b/soc/rockchip/soc.yml @@ -8,3 +8,4 @@ family: socs: - name: rk3588s - name: rk3568 + - name: rk3588