diff --git a/dts/arm/st/wba/stm32wba55.dtsi b/dts/arm/st/wba/stm32wba55.dtsi
index ec0d1e585279b..913eda08c3e08 100644
--- a/dts/arm/st/wba/stm32wba55.dtsi
+++ b/dts/arm/st/wba/stm32wba55.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023 STMicroelectronics
+ * Copyright (c) 2025 Mario Paja
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +9,30 @@
 / {
 	soc {
 		compatible = "st,stm32wba55", "st,stm32wba", "simple-bus";
+
+		sai1_a: sai1@40015404 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015404 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21)>,
+				 <&rcc STM32_SRC_PLL1_P SAI1_SEL(0)>;
+			dmas = <&gpdma1 1 17 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+					      STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
+
+		sai1_b: sai1@40015424 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015424 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21)>,
+				 <&rcc STM32_SRC_PLL1_P SAI1_SEL(0)>;
+			dmas = <&gpdma1 0 18 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+					      STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/dts/bindings/clock/st,stm32wba-pll-clock.yaml b/dts/bindings/clock/st,stm32wba-pll-clock.yaml
index a47b61183f5a8..35ae43678514f 100644
--- a/dts/bindings/clock/st,stm32wba-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32wba-pll-clock.yaml
@@ -51,6 +51,13 @@ properties:
         PLLx multiplication factor for VCO
         Valid range: 4 - 512
 
+  div-p:
+    type: int
+    required: true
+    description: |
+        PLLx DIVP division factor
+        Valid range: 1 - 128
+
   div-q:
     type: int
     description: |
diff --git a/include/zephyr/dt-bindings/clock/stm32wba_clock.h b/include/zephyr/dt-bindings/clock/stm32wba_clock.h
index f1ae4be8fcc15..aedd8c52bcc53 100644
--- a/include/zephyr/dt-bindings/clock/stm32wba_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wba_clock.h
@@ -69,6 +69,7 @@
 #define SYSTICK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
 #define TIMIC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
 /** CCIPR2 devices */
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
 #define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
 /** CCIPR3 devices */
 #define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
diff --git a/samples/drivers/i2s/output/boards/nucleo_wba55cg.conf b/samples/drivers/i2s/output/boards/nucleo_wba55cg.conf
new file mode 100644
index 0000000000000..4f3f73a1e06a5
--- /dev/null
+++ b/samples/drivers/i2s/output/boards/nucleo_wba55cg.conf
@@ -0,0 +1 @@
+CONFIG_HEAP_MEM_POOL_SIZE=4192
diff --git a/samples/drivers/i2s/output/boards/nucleo_wba55cg.overlay b/samples/drivers/i2s/output/boards/nucleo_wba55cg.overlay
new file mode 100644
index 0000000000000..5df69a950571b
--- /dev/null
+++ b/samples/drivers/i2s/output/boards/nucleo_wba55cg.overlay
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2s-tx = &sai1_b;
+	};
+};
+
+&pll1 {
+	/* 43.526KHz (-1.3% Error) */
+	div-m = <4>;
+	mul-n = <19>;
+	div-r = <2>;
+	div-q = <2>;
+	div-p = <14>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&gpdma1 {
+	status = "okay";
+};
+
+/* SAI MCLK conflicts with SPI SCK */
+/* SAI FS conflicts with LPUART TX */
+&sai1_b {
+	pinctrl-0 = <&sai1_mclk_b_pb4 &sai1_sd_b_pb7 &sai1_fs_b_pb5 &sai1_sck_b_pb6>;
+	pinctrl-names = "default";
+	status = "okay";
+	mclk-enable;
+	mclk-divider = "div-256";
+	dma-names = "tx";
+};
+
+&spi1 {
+	status = "disabled";
+};
+
+&lpuart1 {
+	status = "disabled";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
index d8584b42f715b..172332286bdfc 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
@@ -21,6 +21,7 @@
 &pll1 {
 	/delete-property/ div-m;
 	/delete-property/ mul-n;
+	/delete-property/ div-p;
 	/delete-property/ div-q;
 	/delete-property/ div-r;
 	/delete-property/ clocks;
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay
index f5f2cff0d8e51..a50a6c97ea996 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay
@@ -17,6 +17,7 @@
 &pll1 {
 	div-m = <8>;
 	mul-n = <100>;
+	div-p = <2>;
 	div-q = <2>;
 	div-r = <4>;
 	clocks = <&clk_hse>;
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay
index 9c0d128b78aac..7aa2682f04749 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay
@@ -17,6 +17,7 @@
 &pll1 {
 	div-m = <8>;
 	mul-n = <100>;
+	div-p = <2>;
 	div-q = <2>;
 	div-r = <4>;
 	clocks = <&clk_hse>;