diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi
index f62df87dfe269..0e2ab313df9b9 100644
--- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi
+++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi
@@ -138,4 +138,15 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ tpiu_default: tpiu_default {
+		group1 {
+			psels = <NRF_PSEL(TPIU_CLOCK, 7, 3)>,
+				<NRF_PSEL(TPIU_DATA0, 7, 4)>,
+				<NRF_PSEL(TPIU_DATA1, 7, 5)>,
+				<NRF_PSEL(TPIU_DATA2, 7, 6)>,
+				<NRF_PSEL(TPIU_DATA3, 7, 7)>;
+			nordic,drive-mode = <NRF_DRIVE_H0H1>;
+		};
+	};
 };
diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript
index 9738ec77f4372..d79c934174556 100644
--- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript
+++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript
@@ -1,3 +1,9 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 __constant U32 _CPUCONF_ADDR = 0x52011000;
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
@@ -5,32 +11,17 @@ __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 __constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000;
 __constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000;
 __constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0;
+__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700;
 __constant U32 _HOLDTIME_4 = 0x300;
-__constant U32 _ENS0 = 0x1;
-__constant U32 _ENS1 = 0x2;
-__constant U32 _ENS2 = 0x4;
+__constant U32 _ENS0 = 0x1; // Application Core
+__constant U32 _ENS1 = 0x2; // Radio Core
 
 // ATBREPLICATOR
 __constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000;
 __constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000;
 __constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0;
 __constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4;
-__constant U32 _ID_NONE = 0xFFFFFFFF;
-__constant U32 _ID1x = 0xFFFFFFFD;
-
-// TSGEN
-__constant U32 _TSGEN_ADDR = 0xBF041000;
-__constant U32 _TSGEN_CNTCR_OFFSET = 0x0;
-__constant U32 _TSGEN_CNTFID0_OFFSET = 0x20;
-// Clock rate = TDD Freq. / 8
-__constant U32 _TS_CLOCKRATE = 40000000;
-
-// CTI
-__constant U32 _CTI210_ADDR = 0xBF046000;
-__constant U32 _CTICONTROL_OFFSET = 0x0;
-__constant U32 _CTIOUTEN_OFFSET = 0xA0;
-__constant U32 _CTIGATE_OFFSET = 0x140;
-__constant U32 _TPIU_FLUSH_TRIG = 0x2;
+__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID
 
 // TPIU
 __constant U32 _TPIU_ADDR = 0xBF043000;
@@ -43,30 +34,10 @@ __constant U32 _ENFTC = 0x1;
 __constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8;
 __constant U32 _CURRENTPORTSIZE_4 = 0x8;
 
-// TDDCONF
-__constant U32 _TDDCONF_ADDR = 0xBF001000;
-__constant U32 _TRACEPORTSPEED_OFFSET = 0x408;
-__constant U32 _SPEED80MHZ = 0x0;
-
 // CoreSight general
-__constant U32 _CORESIGHT_CLAIMSET_OFFSET = 0xFA0;
-__constant U32 _CORESIGHT_CLAIMCLR_OFFSET = 0xFA4;
 __constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0;
 __constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55;
 
-// GPIO P7
-__constant U32 _P7_ADDR = 0x5F938E00;
-__constant U32 _PIN_CNF3_OFFSET = 0x8C;
-__constant U32 _PIN_CNF4_OFFSET = 0x90;
-__constant U32 _PIN_CNF5_OFFSET = 0x94;
-__constant U32 _PIN_CNF6_OFFSET = 0x98;
-__constant U32 _PIN_CNF7_OFFSET = 0x9C;
-__constant U32 _PIN_CNF_TPIU_CLOCK_VALUE = 0x80000503;
-__constant U32 _PIN_CNF_TPIU_DATA_VALUE = 0x00000503;
-
-// Settings
-__constant U32 _DEBUGGER_CLAIM_MASK = 0x2;
-
 // Used to check if we have already set up tracing
 int _needCoresightSetup = 1;
 
@@ -82,68 +53,59 @@ void _CSLock(U32 addr)
 	JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0);
 }
 
-// Set claim bits in the CoreSight peripheral to indicate to the firmware that it
-// has been configured by the host debugger
-void _CSClaim(U32 addr)
-{
-	JLINK_MEM_WriteU32(addr + _CORESIGHT_CLAIMSET_OFFSET, _DEBUGGER_CLAIM_MASK);
-}
-
 // Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing.
 int _SetupETMTPIUTrace(void)
 {
+	U32 ctrlreg_old;
+	U32 ctrlreg_new;
+	U32 idfilter0_old;
+	U32 idfilter1_old;
+	U32 idfilter0_new;
+	U32 idfilter1_new;
+
 	// Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU
+
 	_CSUnlock(_ATBFUNNEL212_ADDR);
-	JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
-	_CSClaim(_ATBFUNNEL212_ADDR);
+	ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
+	ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0;
+	JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
 	_CSLock(_ATBFUNNEL212_ADDR);
 
 	_CSUnlock(_ATBREPLICATOR212_ADDR);
-	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID_NONE);
-	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID1x);
-	_CSLock(_ATBREPLICATOR212_ADDR);
-	_CSClaim(_ATBREPLICATOR212_ADDR);
+	idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
+	idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
+
+	idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM;  // SET for output 0
+	idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1
+
+	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
+	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
 	_CSLock(_ATBREPLICATOR212_ADDR);
 
 	_CSUnlock(_ATBFUNNEL211_ADDR);
-	JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
-	_CSClaim(_ATBFUNNEL211_ADDR);
+	ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
+	ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0;
+	JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
 	_CSLock(_ATBFUNNEL211_ADDR);
 
 	_CSUnlock(_ATBREPLICATOR213_ADDR);
-	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID1x);
-	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID_NONE);
-	_CSClaim(_ATBREPLICATOR213_ADDR);
-	_CSLock(_ATBREPLICATOR213_ADDR);
+	idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
+	idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
 
-	// Configure timestamp generator for the correct clock rate
-	JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTFID0_OFFSET, _TS_CLOCKRATE);
-	JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTCR_OFFSET, 1);
-	_CSClaim(_TSGEN_ADDR);
+	idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM;  // CLEAR for output 0
+	idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM;   // SET for output 1
 
-	// Configure CTI1 for TPIU formatter flushing
-	_CSUnlock(_CTI210_ADDR);
-	JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIOUTEN_OFFSET, _TPIU_FLUSH_TRIG);
-	JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIGATE_OFFSET, _TPIU_FLUSH_TRIG);
-	JLINK_MEM_WriteU32(_CTI210_ADDR + _CTICONTROL_OFFSET, 1);
-	_CSClaim(_CTI210_ADDR);
-	_CSLock(_CTI210_ADDR);
+	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
+	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
+	_CSLock(_ATBREPLICATOR213_ADDR);
 
 	// Configure TPIU for port size 4, continuous formatting
 	_CSUnlock(_TPIU_ADDR);
 	JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4);
 	JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC);
 	JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT);
-	_CSClaim(_TPIU_ADDR);
 	_CSLock(_TPIU_ADDR);
 
-	// Configure the trace pins
-	JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF3_OFFSET, _PIN_CNF_TPIU_CLOCK_VALUE);
-	JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF4_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
-	JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF5_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
-	JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF6_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
-	JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF7_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
-
 	return 0;
 }
 
@@ -155,6 +117,19 @@ int ConfigTargetSettings(void)
 	// Adjust trace sample delay to compensate for timing when using 320MHz
 	JLINK_ExecCommand("TraceSampleAdjust TD = 1000");
 
+	JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000");
+
+	return 0;
+}
+
+int StartTPIU(void)
+{
+	/* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */
+	return 0;
+}
+
+int StopTPIU(void)
+{
 	return 0;
 }
 
@@ -169,6 +144,11 @@ int OnTraceStart(void)
 	return 0;
 }
 
+int AfterResetTarget(void)
+{
+	_needCoresightSetup = 1;
+	return 0;
+}
 
 int SetupTarget(void)
 {
@@ -179,3 +159,8 @@ int SetupTarget(void)
 
 	return 0;
 }
+
+int InitEMU(void) {
+	JLINK_ExecCommand("EnableLowPowerHandlingMode");
+	return 0;
+}
diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript
index e1861ae8c972a..2ff7f6c160e3c 100644
--- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript
+++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript
@@ -1,11 +1,153 @@
-__constant U32 _CPUCONF_ADDR = 0x53011000;
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+__constant U32 _CPUCONF_ADDR = 0x52011000;
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
+// ATBFUNNEL
+__constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000;
+__constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000;
+__constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0;
+__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700;
+__constant U32 _HOLDTIME_4 = 0x300;
+__constant U32 _ENS0 = 0x1; // Application Core
+__constant U32 _ENS1 = 0x2; // Radio Core
+
+// ATBREPLICATOR
+__constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000;
+__constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000;
+__constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0;
+__constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4;
+__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID
+
+// TPIU
+__constant U32 _TPIU_ADDR = 0xBF043000;
+__constant U32 _CURRENTPORTSIZE_OFFSET = 0x4;
+__constant U32 _FFCR_OFFSET = 0x304;
+__constant U32 _FSCR_OFFSET = 0x308;
+__constant U32 _ENFCONT = 0x02;
+__constant U32 _FONFLIN = 0x10;
+__constant U32 _ENFTC = 0x1;
+__constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8;
+__constant U32 _CURRENTPORTSIZE_4 = 0x8;
+
+// CoreSight general
+__constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0;
+__constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55;
+
+// Used to check if we have already set up tracing
+int _needCoresightSetup = 1;
+
+// Unlock a CoreSight peripheral
+void _CSUnlock(U32 addr)
+{
+	JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, _CORESIGHT_UNLOCK_KEY);
+}
+
+// Lock a CoreSight peripheral
+void _CSLock(U32 addr)
+{
+	JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0);
+}
+
+// Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing.
+int _SetupETMTPIUTrace(void)
+{
+	U32 ctrlreg_old;
+	U32 ctrlreg_new;
+	U32 idfilter0_old;
+	U32 idfilter1_old;
+	U32 idfilter0_new;
+	U32 idfilter1_new;
+
+	// Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU
+
+	_CSUnlock(_ATBFUNNEL212_ADDR);
+	ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
+	ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1;
+	JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
+	_CSLock(_ATBFUNNEL212_ADDR);
+
+	_CSUnlock(_ATBREPLICATOR212_ADDR);
+	idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
+	idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
+
+	idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM;  // SET for output 0
+	idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1
+
+	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
+	JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
+	_CSLock(_ATBREPLICATOR212_ADDR);
+
+	_CSUnlock(_ATBFUNNEL211_ADDR);
+	ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
+	ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1;
+	JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
+	_CSLock(_ATBFUNNEL211_ADDR);
+
+	_CSUnlock(_ATBREPLICATOR213_ADDR);
+	idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
+	idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
+
+	idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM;  // CLEAR for output 0
+	idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM;   // SET for output 1
+
+	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
+	JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
+	_CSLock(_ATBREPLICATOR213_ADDR);
+
+	// Configure TPIU for port size 4, continuous formatting
+	_CSUnlock(_TPIU_ADDR);
+	JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4);
+	JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC);
+	JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT);
+	_CSLock(_TPIU_ADDR);
+
+	return 0;
+}
+
 int ConfigTargetSettings(void)
 {
 	JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP");
 	CORESIGHT_IndexAHBAPToUse = 1;
 
+	// Adjust trace sample delay to compensate for timing when using 320MHz
+	JLINK_ExecCommand("TraceSampleAdjust TD = 1000");
+
+	JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000");
+
+	return 0;
+}
+
+int StartTPIU(void)
+{
+	/* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */
+	return 0;
+}
+
+int StopTPIU(void)
+{
+	return 0;
+}
+
+
+int OnTraceStart(void)
+{
+	// Set up CoreSight if not already configured
+	if (_needCoresightSetup) {
+		_SetupETMTPIUTrace();
+		_needCoresightSetup = 0;
+	}
+
+	return 0;
+}
+
+int AfterResetTarget(void)
+{
+	_needCoresightSetup = 1;
 	return 0;
 }
 
@@ -18,3 +160,8 @@ int SetupTarget(void)
 
 	return 0;
 }
+
+int InitEMU(void) {
+	JLINK_ExecCommand("EnableLowPowerHandlingMode");
+	return 0;
+}
diff --git a/doc/releases/migration-guide-4.3.rst b/doc/releases/migration-guide-4.3.rst
index 10b0e3232a06d..0ad5c10c543f2 100644
--- a/doc/releases/migration-guide-4.3.rst
+++ b/doc/releases/migration-guide-4.3.rst
@@ -68,6 +68,14 @@ MFD
   kconfig symbol ``MFD_AXP192_AXP2101`` is removed. :kconfig:option:`MFD_AXP192` is now to be
   used for AXP192 device while :kconfig:option:`MFD_AXP2101` for the AXP2101 one.
 
+MISC
+====
+
+* The nrf_etr driver has been migrated to drivers/debug. As a consequence the related Kconfig
+  symbol was renamed from ``NRF_ETR`` to :kconfig:option:`DEBUG_NRF_ETR`, along with the rest of
+  the ``NRF_ETR`` symbols. Also the driver needs to be explicitly enabled via
+  :kconfig:option:`DEBUG_DRIVER` as it is no longer built by default.
+
 PWM
 ===
 
diff --git a/doc/services/logging/cs_stm.rst b/doc/services/logging/cs_stm.rst
index 75a371dfd24e0..77b097d651612 100644
--- a/doc/services/logging/cs_stm.rst
+++ b/doc/services/logging/cs_stm.rst
@@ -119,7 +119,7 @@ When using logs, this method has the following advantages:
 
 Proxy core is using Nordic specific peripheral (TBM) to get ETR buffer busyness and send data over
 UART. Nordic specific driver for ETR buffer is located in
-:zephyr_file:`drivers/misc/coresight/nrf_etr.c`.
+:zephyr_file:`drivers/debug/debug_nrf_etr.c`.
 
 Configuration
 -------------
@@ -175,7 +175,7 @@ in :zephyr_file:`subsys/logging/frontends/log_frontend_stmesp_demux.c`.
 
 ``Proxy`` is using Nordic specific peripheral (TBM) to get ETR buffer busyness and read and
 decode data and send human-readable data over UART. Nordic specific driver for ETR buffer is
-located in :zephyr_file:`drivers/misc/coresight/nrf_etr.c`. It is using :ref:`cs_trace_defmt` and
+located in :zephyr_file:`drivers/debug/debug_nrf_etr.c`. It is using :ref:`cs_trace_defmt` and
 :ref:`mipi_stp_decoder` and above-mentioned demultiplexer to decode messages.
 
 Logging messages contains read-only format string used in the logging macros thus they cannot be
diff --git a/drivers/debug/CMakeLists.txt b/drivers/debug/CMakeLists.txt
index 54ca9f71694e8..29763be07ec17 100644
--- a/drivers/debug/CMakeLists.txt
+++ b/drivers/debug/CMakeLists.txt
@@ -4,5 +4,7 @@
 zephyr_library()
 
 # zephyr-keep-sorted-start
+zephyr_library_sources_ifdef(CONFIG_DEBUG_CORESIGHT_NRF debug_coresight_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_DEBUG_NRF_ETR debug_nrf_etr.c)
 zephyr_library_sources_ifdef(CONFIG_DEBUG_SILABS_PTI debug_silabs_pti.c)
 # zephyr-keep-sorted-stop
diff --git a/drivers/debug/Kconfig b/drivers/debug/Kconfig
index 68c23fdf1243b..b38c5206f3cb6 100644
--- a/drivers/debug/Kconfig
+++ b/drivers/debug/Kconfig
@@ -15,6 +15,7 @@ config DEBUG_DRIVER_INIT_PRIORITY
 	  Debug drivers initialization priority.
 
 # zephyr-keep-sorted-start
+source "drivers/debug/Kconfig.nrf"
 source "drivers/debug/Kconfig.silabs"
 # zephyr-keep-sorted-stop
 
diff --git a/drivers/misc/coresight/Kconfig b/drivers/debug/Kconfig.nrf
similarity index 51%
rename from drivers/misc/coresight/Kconfig
rename to drivers/debug/Kconfig.nrf
index 997d0c23c0a54..030e9885a06df 100644
--- a/drivers/misc/coresight/Kconfig
+++ b/drivers/debug/Kconfig.nrf
@@ -3,7 +3,7 @@
 
 DT_COMPAT_NORDIC_NRF_TBM := nordic,nrf-tbm
 
-config NRF_ETR
+config DEBUG_NRF_ETR
 	bool "Coresight ETR handler (with Nordic TBM)"
 	depends on $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_TBM))
 	select NRFX_TBM
@@ -14,9 +14,9 @@ config NRF_ETR
 	  data). Busyness is tracked using TBM (Trace Buffer Monitor) peripheral
 	  which is specific to Nordic Semiconductor SoCs.
 
-if NRF_ETR
+if DEBUG_NRF_ETR
 
-config NRF_ETR_DECODE
+config DEBUG_NRF_ETR_DECODE
 	bool "Decode ETR content"
 	default y if LOG_FRONTEND_STMESP_FSC
 	select MIPI_STP_DECODER
@@ -29,14 +29,14 @@ config NRF_ETR_DECODE
 	  In this mode, log messages stored by Coresight STM logging frontends are
 	  decoded and printed in the human readable form.
 
-config NRF_ETR_DECODE_DROP_PERIOD
+config DEBUG_NRF_ETR_DECODE_DROP_PERIOD
 	int "Period of dropped messages notification"
 	default 5000
 	help
 	  Period (in milliseconds) how often it is checked if any dropped messages
 	  have occurred.
 
-config NRF_ETR_DEBUG
+config DEBUG_NRF_ETR_DEBUG
 	bool "Debug mode"
 	depends on !LOG_PRINTK
 	select MIPI_STP_DECODER
@@ -44,18 +44,18 @@ config NRF_ETR_DEBUG
 	help
 	  In debug mode STPv2 decoded data is printed.
 
-config NRF_ETR_STACK_SIZE
+config DEBUG_NRF_ETR_STACK_SIZE
 	int "ETR thread stack size"
-	default 2048 if NRF_ETR_DECODE || NRF_ETR_DEBUG
+	default 2048 if DEBUG_NRF_ETR_DECODE || DEBUG_NRF_ETR_DEBUG
 	default 1024
 
-config NRF_ETR_BACKOFF
+config DEBUG_NRF_ETR_BACKOFF
 	int "Thread backoff time (ms)"
 	default 10
 	help
 	  Determines how often attempt to dump the data is performed.
 
-config NRF_ETR_FLUSH_TIMEOUT
+config DEBUG_NRF_ETR_FLUSH_TIMEOUT
 	int "Backoff time during flushing (ms)"
 	default 100
 	help
@@ -63,10 +63,10 @@ config NRF_ETR_FLUSH_TIMEOUT
 	  there is still a pending ETR data. This option specifies how often
 	  thread is waking up to check. Given in milliseconds.
 
-config NRF_ETR_SYNC_PERIOD
+config DEBUG_NRF_ETR_SYNC_PERIOD
 	int "Period of custom synchronization frame"
-	default 0 if NRF_ETR_DECODE
-	default 0 if NRF_ETR_DEBUG
+	default 0 if DEBUG_NRF_ETR_DECODE
+	default 0 if DEBUG_NRF_ETR_DEBUG
 	default 16
 	help
 	  To help find the synchronization when decoding the ETR content
@@ -74,25 +74,25 @@ config NRF_ETR_SYNC_PERIOD
 	  sent on regular intervals. This frame is sent between Coresight formatter
 	  frames. Use 0 to disable.
 
-config NRF_ETR_SHELL
+config DEBUG_NRF_ETR_SHELL
 	bool "Use shell"
 	select UART_ASYNC_API
 	select UART_ASYNC_RX_HELPER
 	select SHELL_LOG_BACKEND_CUSTOM
-	depends on NRF_ETR_DECODE
+	depends on DEBUG_NRF_ETR_DECODE
 	default y if SHELL
 	help
 	  Enable shell with Coresight STM logging support.
 
-if NRF_ETR_SHELL
+if DEBUG_NRF_ETR_SHELL
 
-config NRF_ETR_SHELL_PROMPT
+config DEBUG_NRF_ETR_SHELL_PROMPT
 	string "Displayed prompt name"
 	default "uart:~$ "
 	help
 	  Displayed prompt name for UART shell with Coresight STM logging.
 
-config NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE
+config DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE
 	int "Size of the RX buffer"
 	default 16
 	help
@@ -101,13 +101,78 @@ config NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE
 	  slow and may need to be increased if long messages are pasted directly
 	  to the shell prompt.
 
-config NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT
+config DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT
 	int "Number of RX buffers"
 	default 4
 	range 2 64
 	help
 	  Number of RX buffers.
 
-endif # NRF_ETR_SHELL
+endif # DEBUG_NRF_ETR_SHELL
 
-endif # NRF_ETR
+endif # DEBUG_NRF_ETR
+
+menuconfig DEBUG_CORESIGHT_NRF
+	bool "Coresight Trace support"
+	default y
+	depends on DT_HAS_NORDIC_CORESIGHT_NRF_ENABLED
+	select PINCTRL
+	select NRF_IRONSIDE_TDD_SERVICE
+	help
+	  Support CoreSight peripherals in Test and Debug Domain for ARM
+	  CoreSight System Trace Macrocell (STM) trace support.
+
+if DEBUG_CORESIGHT_NRF
+
+config DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL
+	def_hex 0x40
+	help
+	  Global trace ID used by STM.
+
+config DEBUG_CORESIGHT_NRF_STM_SYNC_BYTE_COUNT
+	int "STM: Emit synhronization packet every N bytes"
+	range 0 4095
+	default 512
+
+config DEBUG_CORESIGHT_NRF_STM_HWEVENTS
+	bool "STM: Enable hardware events"
+	help
+	  Enable the output of hardware events in STM.
+
+config DEBUG_CORESIGHT_NRF_TPIU_FFCR_TRIG
+	bool "TPIU: Use flush request trigger"
+	default y
+	help
+	  Use CTI channel 1 for triggering flush request in TPIU.
+
+config DEBUG_CORESIGHT_NRF_TPIU_SYNC_FRAME_COUNT
+	int "TPIU: Emit synchronisation packet every N frames"
+	default 8
+
+config DEBUG_CORESIGHT_NRF_TPIU_PORTSIZE
+	int "TPIU: Size of the current TPIU port in bits"
+	range 1 32
+	default 4
+
+config DEBUG_CORESIGHT_NRF_ATBFUNNEL_HOLD_TIME
+	int "ATBFUNNEL: Hold time for the transaction"
+	range 1 15
+	default 4
+	help
+	  Number of transactions that are output on the funnel master port from the
+	  same slave.
+
+config DEBUG_CORESIGHT_NRF_TSGEN_CLK_DIV
+	int
+	default 8
+	help
+	  Clock division factor for generating trace timestamps. The timestamp
+	  counter should not be slower than 10% of the fastest processor clock
+	  frequency in the system, therefore its clock speed is divided by
+	  eight.
+
+module = DEBUG_CORESIGHT_NRF
+module-str = CoreSight Trace
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # DEBUG_CORESIGHT_NRF
diff --git a/drivers/debug/coresight_arm.h b/drivers/debug/coresight_arm.h
new file mode 100644
index 0000000000000..b0c5da3e92d02
--- /dev/null
+++ b/drivers/debug/coresight_arm.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CORESIGHT_ARM_H_
+#define CORESIGHT_ARM_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <zephyr/sys/sys_io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file
+ * @brief Generic ARM CoreSight Hardware Abstraction Layer
+ *
+ * This HAL provides generic register definitions and utility functions for ARM CoreSight
+ * peripherals. Platform-specific drivers should provide base addresses and use these
+ * generic definitions for register access.
+ */
+
+/* Common CoreSight unlock key as defined by ARM architecture */
+#define CORESIGHT_UNLOCK_KEY (0xC5ACCE55UL)
+
+/* CoreSight register offsets */
+
+/* Common CoreSight peripheral register offsets (found at the end of all CoreSight peripherals) */
+#define CORESIGHT_CLAIMSET_OFFSET (0xFA0UL) /* Claim Tag Set Register */
+#define CORESIGHT_CLAIMCLR_OFFSET (0xFA4UL) /* Claim Tag Clear Register */
+#define CORESIGHT_LAR_OFFSET      (0xFB0UL) /* Lock Access Register */
+#define CORESIGHT_LSR_OFFSET      (0xFB4UL) /* Lock Status Register */
+
+/* ATB Funnel register offsets */
+#define ATBFUNNEL_CTRLREG_OFFSET (0x000UL) /* Control Register */
+
+/* ATB Replicator register offsets */
+#define ATBREPLICATOR_IDFILTER0_OFFSET (0x000UL) /* ID Filter Register 0 */
+#define ATBREPLICATOR_IDFILTER1_OFFSET (0x004UL) /* ID Filter Register 1 */
+
+/* ETR (Embedded Trace Router/TMC-ETR) register offsets */
+#define ETR_RSZ_OFFSET   (0x004UL) /* RAM Size Register */
+#define ETR_RWP_OFFSET   (0x018UL) /* RAM Write Pointer Register */
+#define ETR_CTL_OFFSET   (0x020UL) /* Control Register */
+#define ETR_MODE_OFFSET  (0x028UL) /* Mode Register */
+#define ETR_DBALO_OFFSET (0x118UL) /* Data Buffer Address Low Register */
+#define ETR_DBAHI_OFFSET (0x11CUL) /* Data Buffer Address High Register */
+#define ETR_FFCR_OFFSET  (0x304UL) /* Formatter and Flush Control Register */
+
+/* STM (System Trace Macrocell) register offsets */
+#define STM_STMHEER_OFFSET    (0xD00UL) /* Hardware Event Enable Register */
+#define STM_STMHEMCR_OFFSET   (0xD64UL) /* Hardware Event Master Control Register */
+#define STM_STMSPER_OFFSET    (0xE00UL) /* Stimulus Port Enable Register */
+#define STM_STMTCSR_OFFSET    (0xE80UL) /* Trace Control and Status Register */
+#define STM_STMTSFREQR_OFFSET (0xE8CUL) /* Timestamp Frequency Register */
+#define STM_STMSYNCR_OFFSET   (0xE90UL) /* Synchronization Control Register */
+#define STM_STMAUXCR_OFFSET   (0xE94UL) /* Auxiliary Control Register */
+
+/* TPIU (Trace Port Interface Unit) register offsets */
+#define TPIU_CSPSR_OFFSET (0x004UL) /* Current Parallel Port Size Register */
+#define TPIU_FFCR_OFFSET  (0x304UL) /* Formatter and Flush Control Register */
+#define TPIU_FSCR_OFFSET  (0x308UL) /* Formatter Synchronization Counter Register */
+
+/* CTI (Cross Trigger Interface) register offsets */
+#define CTI_CTICONTROL_OFFSET (0x000UL) /* CTI Control Register */
+#define CTI_CTIOUTEN0_OFFSET  (0x0A0UL) /* CTI Trigger Output Enable Register 0 */
+#define CTI_CTIGATE_OFFSET    (0x140UL) /* CTI Channel Gate Enable Register */
+
+/* TSGEN (Timestamp Generator) register offsets */
+#define TSGEN_CNTCR_OFFSET   (0x000UL) /* Counter Control Register */
+#define TSGEN_CNTFID0_OFFSET (0x020UL) /* Counter Frequency ID Register 0 */
+
+/* Lock Status Register (LSR) bit fields */
+#define CORESIGHT_LSR_LOCKED_Pos  (1UL)
+#define CORESIGHT_LSR_LOCKED_Msk  (0x1UL << CORESIGHT_LSR_LOCKED_Pos)
+#define CORESIGHT_LSR_PRESENT_Pos (0UL)
+#define CORESIGHT_LSR_PRESENT_Msk (0x1UL << CORESIGHT_LSR_PRESENT_Pos)
+
+/* STM Trace Control and Status Register (STMTCSR) bit fields */
+#define STM_STMTCSR_EN_Pos      (0UL)
+#define STM_STMTCSR_EN_Msk      (0x1UL << STM_STMTCSR_EN_Pos)
+#define STM_STMTCSR_TSEN_Pos    (1UL)
+#define STM_STMTCSR_TSEN_Msk    (0x1UL << STM_STMTCSR_TSEN_Pos)
+#define STM_STMTCSR_TRACEID_Pos (16UL)
+#define STM_STMTCSR_TRACEID_Msk (0x7FUL << STM_STMTCSR_TRACEID_Pos)
+
+/* STM Hardware Event Master Control Register (STMHEMCR) bit fields */
+#define STM_STMHEMCR_EN_Pos (0UL)
+#define STM_STMHEMCR_EN_Msk (0x1UL << STM_STMHEMCR_EN_Pos)
+
+/* STM Auxiliary Control Register (STMAUXCR) bit fields */
+#define STM_STMAUXCR_FIFOAF_Pos (0UL)
+#define STM_STMAUXCR_FIFOAF_Msk (0x1UL << STM_STMAUXCR_FIFOAF_Pos)
+
+/* CTI Control Register (CTICONTROL) bit fields */
+#define CTI_CTICONTROL_GLBEN_Pos (0UL)
+#define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos)
+
+/* TPIU Formatter and Flush Control Register (FFCR) bit fields */
+#define TPIU_FFCR_ENFCONT_Pos (1UL)
+#define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos)
+#define TPIU_FFCR_FONFLIN_Pos (4UL)
+#define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos)
+#define TPIU_FFCR_ENFTC_Pos   (0UL)
+#define TPIU_FFCR_ENFTC_Msk   (0x1UL << TPIU_FFCR_ENFTC_Pos)
+
+/* ETR Mode Register bit fields */
+#define ETR_MODE_MODE_Pos         (0UL)
+#define ETR_MODE_MODE_Msk         (0x3UL << ETR_MODE_MODE_Pos)
+#define ETR_MODE_MODE_CIRCULARBUF (0UL) /* Circular Buffer mode */
+#define ETR_MODE_MODE_SWFIFO1     (1UL) /* Software FIFO mode */
+#define ETR_MODE_MODE_HWFIFO      (2UL) /* Hardware FIFO mode */
+#define ETR_MODE_MODE_SWFIFO2     (3UL) /* Software FIFO mode */
+
+/* ETR Control Register bit fields */
+#define ETR_CTL_TRACECAPTEN_Pos (0UL)
+#define ETR_CTL_TRACECAPTEN_Msk (0x1UL << ETR_CTL_TRACECAPTEN_Pos)
+
+/* ETR Formatter and Flush Control Register (FFCR) bit fields */
+#define ETR_FFCR_ENFT_Pos (0UL)
+#define ETR_FFCR_ENFT_Msk (0x1UL << ETR_FFCR_ENFT_Pos)
+#define ETR_FFCR_ENTI_Pos (1UL)
+#define ETR_FFCR_ENTI_Msk (0x1UL << ETR_FFCR_ENTI_Pos)
+
+/* ATB Funnel Control Register bit fields */
+#define ATBFUNNEL_CTRLREG_ENS0_Pos (0UL)
+#define ATBFUNNEL_CTRLREG_ENS0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS0_Pos)
+#define ATBFUNNEL_CTRLREG_ENS1_Pos (1UL)
+#define ATBFUNNEL_CTRLREG_ENS1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS1_Pos)
+#define ATBFUNNEL_CTRLREG_ENS2_Pos (2UL)
+#define ATBFUNNEL_CTRLREG_ENS2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS2_Pos)
+#define ATBFUNNEL_CTRLREG_ENS3_Pos (3UL)
+#define ATBFUNNEL_CTRLREG_ENS3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS3_Pos)
+#define ATBFUNNEL_CTRLREG_ENS4_Pos (4UL)
+#define ATBFUNNEL_CTRLREG_ENS4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS4_Pos)
+#define ATBFUNNEL_CTRLREG_ENS5_Pos (5UL)
+#define ATBFUNNEL_CTRLREG_ENS5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS5_Pos)
+#define ATBFUNNEL_CTRLREG_ENS6_Pos (6UL)
+#define ATBFUNNEL_CTRLREG_ENS6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS6_Pos)
+#define ATBFUNNEL_CTRLREG_ENS7_Pos (7UL)
+#define ATBFUNNEL_CTRLREG_ENS7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS7_Pos)
+#define ATBFUNNEL_CTRLREG_HT_Pos   (8UL)
+#define ATBFUNNEL_CTRLREG_HT_Msk   (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos)
+
+/* TSGEN Counter Control Register bit fields */
+#define TSGEN_CNTCR_EN_Pos (0UL)
+#define TSGEN_CNTCR_EN_Msk (0x1UL << TSGEN_CNTCR_EN_Pos)
+
+/**
+ * @brief Check if a CoreSight peripheral is locked
+ *
+ * @param base_addr Base address of CoreSight peripheral
+ * @return true if peripheral is locked, false otherwise
+ */
+static inline bool coresight_is_locked(mem_addr_t base_addr)
+{
+	uint32_t lsr = *(volatile uint32_t *)(base_addr + CORESIGHT_LSR_OFFSET);
+
+	return (lsr & CORESIGHT_LSR_LOCKED_Msk) != 0;
+}
+
+/**
+ * @brief Unlock a CoreSight peripheral
+ *
+ * @param base_addr Base address of CoreSight peripheral
+ * @retval 0 on success
+ * @retval -EIO if unlock operation failed
+ */
+static inline int coresight_unlock(mem_addr_t base_addr)
+{
+	*(volatile uint32_t *)(base_addr + CORESIGHT_LAR_OFFSET) = CORESIGHT_UNLOCK_KEY;
+
+	if (coresight_is_locked(base_addr)) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Lock a CoreSight peripheral
+ *
+ * @param base_addr Base address of CoreSight peripheral
+ * @retval 0 on success
+ * @retval -EIO if lock operation failed
+ */
+static inline int coresight_lock(mem_addr_t base_addr)
+{
+	/* Write any value other than unlock key to Lock Access Register to lock */
+	*(volatile uint32_t *)(base_addr + CORESIGHT_LAR_OFFSET) = 0x00000000;
+
+	if (!coresight_is_locked(base_addr)) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CORESIGHT_ARM_H_ */
diff --git a/drivers/debug/debug_coresight_nrf.c b/drivers/debug/debug_coresight_nrf.c
new file mode 100644
index 0000000000000..7bc9bab68ee0b
--- /dev/null
+++ b/drivers/debug/debug_coresight_nrf.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/sys_io.h>
+#include <nrf_ironside/tdd.h>
+#include <uicr/uicr.h>
+
+#undef ETR_MODE_MODE_CIRCULARBUF
+
+#include "coresight_arm.h"
+
+#define DT_DRV_COMPAT nordic_coresight_nrf
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(cs_trace, CONFIG_DEBUG_CORESIGHT_NRF_LOG_LEVEL);
+
+#define CTI_CH_TPIU_FLUSH_REQ_OFFSET (1)
+
+#define TS_CLOCKRATE                                                                               \
+	(DT_PROP(DT_NODELABEL(hsfll200), clock_frequency) /                                        \
+	 CONFIG_DEBUG_CORESIGHT_NRF_TSGEN_CLK_DIV)
+
+#define ATBREPLICATOR_IDFILTER_FORWARD_STM                                                         \
+	BIT(CONFIG_DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL >> 4)
+#define ATBFUNNEL211_STM_ENS_MASK BIT(2)
+
+enum coresight_nrf_mode {
+	CORESIGHT_NRF_MODE_UNCONFIGURED,
+	CORESIGHT_NRF_MODE_STM_TPIU,
+	CORESIGHT_NRF_MODE_STM_ETR,
+};
+
+struct coresight_nrf_config {
+	enum coresight_nrf_mode mode;
+	const struct pinctrl_dev_config *pcfg;
+};
+
+static void nrf_tsgen_init(void)
+{
+	mem_addr_t tsgen = DT_REG_ADDR(DT_NODELABEL(tsgen));
+
+	coresight_unlock(tsgen);
+
+	sys_write32(TS_CLOCKRATE, tsgen + TSGEN_CNTFID0_OFFSET);
+	sys_write32(TSGEN_CNTCR_EN_Msk, tsgen + TSGEN_CNTCR_OFFSET);
+
+	coresight_lock(tsgen);
+
+	LOG_INF("CoreSight Host TSGEN initialized with clockrate %u", TS_CLOCKRATE);
+}
+
+static void nrf_cti_for_tpiu_init(void)
+{
+	mem_addr_t cti210 = DT_REG_ADDR(DT_NODELABEL(cti210));
+
+	coresight_unlock(cti210);
+
+	/* Connect CTI channel to TPIU formatter flushin */
+	sys_write32(BIT(CTI_CH_TPIU_FLUSH_REQ_OFFSET), cti210 + CTI_CTIOUTEN0_OFFSET);
+	sys_write32(BIT(CTI_CH_TPIU_FLUSH_REQ_OFFSET), cti210 + CTI_CTIGATE_OFFSET);
+	sys_write32(CTI_CTICONTROL_GLBEN_Msk, cti210 + CTI_CTICONTROL_OFFSET);
+
+	coresight_lock(cti210);
+
+	LOG_INF("CoreSight Host CTI initialized");
+}
+
+static void nrf_tpiu_init(void)
+{
+	mem_addr_t tpiu = DT_REG_ADDR(DT_NODELABEL(tpiu));
+
+	coresight_unlock(tpiu);
+
+	sys_write32(BIT((CONFIG_DEBUG_CORESIGHT_NRF_TPIU_PORTSIZE - 1)), tpiu + TPIU_CSPSR_OFFSET);
+
+	/* Continuous formatting  */
+	if (IS_ENABLED(CONFIG_DEBUG_CORESIGHT_NRF_TPIU_FFCR_TRIG)) {
+		sys_write32((TPIU_FFCR_ENFCONT_Msk | TPIU_FFCR_FONFLIN_Msk | TPIU_FFCR_ENFTC_Msk),
+			    tpiu + TPIU_FFCR_OFFSET);
+	} else {
+		sys_write32((TPIU_FFCR_ENFCONT_Msk | TPIU_FFCR_ENFTC_Msk), tpiu + TPIU_FFCR_OFFSET);
+	}
+
+	sys_write32(CONFIG_DEBUG_CORESIGHT_NRF_TPIU_SYNC_FRAME_COUNT, tpiu + TPIU_FSCR_OFFSET);
+
+	coresight_lock(tpiu);
+
+	LOG_INF("CoreSight Host TPIU initialized");
+}
+
+static void nrf_etr_init(uintptr_t buf, size_t buf_word_len)
+{
+	mem_addr_t etr = DT_REG_ADDR(DT_NODELABEL(etr));
+
+	coresight_unlock(etr);
+
+	sys_write32(buf_word_len, etr + ETR_RSZ_OFFSET);
+	sys_write32(buf, etr + ETR_RWP_OFFSET);
+	sys_write32(buf, etr + ETR_DBALO_OFFSET);
+	sys_write32(0UL, etr + ETR_DBAHI_OFFSET);
+	sys_write32(ETR_FFCR_ENFT_Msk, etr + ETR_FFCR_OFFSET);
+	sys_write32(ETR_MODE_MODE_CIRCULARBUF, etr + ETR_MODE_OFFSET);
+	sys_write32(ETR_CTL_TRACECAPTEN_Msk, etr + ETR_CTL_OFFSET);
+
+	coresight_lock(etr);
+
+	LOG_INF("Coresight Host ETR initialized");
+}
+
+static void nrf_stm_init(void)
+{
+	mem_addr_t stm = DT_REG_ADDR(DT_NODELABEL(stm));
+
+	coresight_unlock(stm);
+
+	sys_write32(1, stm + STM_STMAUXCR_OFFSET);
+
+	sys_write32(TS_CLOCKRATE, stm + STM_STMTSFREQR_OFFSET);
+
+	sys_write32((CONFIG_DEBUG_CORESIGHT_NRF_STM_SYNC_BYTE_COUNT & 0xFFF),
+		    stm + STM_STMSYNCR_OFFSET);
+
+	sys_write32(0xFFFFFFFF, stm + STM_STMSPER_OFFSET);
+
+	if (IS_ENABLED(CONFIG_DEBUG_CORESIGHT_NRF_STM_HWEVENTS)) {
+		sys_write32(0xFFFFFFFF, stm + STM_STMHEER_OFFSET);
+		sys_write32((1 << STM_STMHEMCR_EN_Pos), stm + STM_STMHEMCR_OFFSET);
+	}
+
+	sys_write32(((CONFIG_DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL & STM_STMTCSR_TRACEID_Msk)
+		     << STM_STMTCSR_TRACEID_Pos) |
+			    (1 << STM_STMTCSR_EN_Pos) | (1 << STM_STMTCSR_TSEN_Pos),
+		    stm + STM_STMTCSR_OFFSET);
+
+	coresight_lock(stm);
+
+	LOG_INF("CoreSight STM initialized with clockrate %u", TS_CLOCKRATE);
+}
+
+static void nrf_atbfunnel_init(mem_addr_t funnel_addr, uint32_t enable_set_mask)
+{
+	coresight_unlock(funnel_addr);
+
+	uint32_t ctrlreg_old = sys_read32(funnel_addr + ATBFUNNEL_CTRLREG_OFFSET);
+
+	const uint32_t funnel_hold_time = (((CONFIG_DEBUG_CORESIGHT_NRF_ATBFUNNEL_HOLD_TIME - 1)
+					    << ATBFUNNEL_CTRLREG_HT_Pos) &
+					   ATBFUNNEL_CTRLREG_HT_Msk);
+
+	uint32_t ctrlreg_new = (ctrlreg_old & ~ATBFUNNEL_CTRLREG_HT_Msk) | funnel_hold_time |
+			       (enable_set_mask & 0xFF);
+
+	sys_write32(ctrlreg_new, funnel_addr + ATBFUNNEL_CTRLREG_OFFSET);
+
+	coresight_lock(funnel_addr);
+}
+
+static void nrf_atbreplicator_init(mem_addr_t replicator_addr, uint32_t filter, bool ch0_allow,
+				   bool ch1_allow)
+{
+	coresight_unlock(replicator_addr);
+
+	uint32_t ch0_current = sys_read32(replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET);
+	uint32_t ch1_current = sys_read32(replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET);
+
+	if (ch0_allow) {
+		sys_write32(ch0_current & ~filter,
+			    replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET);
+	} else {
+		sys_write32(ch0_current | filter, replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET);
+	}
+
+	if (ch1_allow) {
+		sys_write32(ch1_current & ~filter,
+			    replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET);
+	} else {
+		sys_write32(ch1_current | filter, replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET);
+	}
+
+	coresight_lock(replicator_addr);
+}
+
+static int coresight_nrf_init_stm_etr(uintptr_t buf, size_t buf_word_len)
+{
+	mem_addr_t atbfunnel211 = DT_REG_ADDR(DT_NODELABEL(atbfunnel211));
+	mem_addr_t atbreplicator210 = DT_REG_ADDR(DT_NODELABEL(atbreplicator210));
+	mem_addr_t atbreplicator213 = DT_REG_ADDR(DT_NODELABEL(atbreplicator213));
+
+	nrf_atbfunnel_init(atbfunnel211, ATBFUNNEL211_STM_ENS_MASK);
+	nrf_atbreplicator_init(atbreplicator210, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true);
+	nrf_atbreplicator_init(atbreplicator213, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true);
+
+	nrf_tsgen_init();
+	nrf_etr_init(buf, buf_word_len);
+	nrf_stm_init();
+
+	return 0;
+}
+
+static int coresight_nrf_init_stm_tpiu(void)
+{
+	mem_addr_t atbfunnel211 = DT_REG_ADDR(DT_NODELABEL(atbfunnel211));
+	mem_addr_t atbreplicator210 = DT_REG_ADDR(DT_NODELABEL(atbreplicator210));
+	mem_addr_t atbreplicator213 = DT_REG_ADDR(DT_NODELABEL(atbreplicator213));
+
+	nrf_atbfunnel_init(atbfunnel211, ATBFUNNEL211_STM_ENS_MASK);
+	nrf_atbreplicator_init(atbreplicator210, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true);
+	nrf_atbreplicator_init(atbreplicator213, ATBREPLICATOR_IDFILTER_FORWARD_STM, true, false);
+
+	nrf_tsgen_init();
+	nrf_cti_for_tpiu_init();
+	nrf_tpiu_init();
+	nrf_stm_init();
+
+	return 0;
+}
+
+static int coresight_nrf_init(const struct device *dev)
+{
+	int err;
+	struct coresight_nrf_config *cfg = (struct coresight_nrf_config *)dev->config;
+
+	if (cfg->pcfg) {
+		err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+		if (err) {
+			LOG_ERR("Failed to configure pins (%d)", err);
+			return err;
+		}
+	}
+
+	err = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT);
+	if (err) {
+		LOG_ERR("Failed to configure TDD (%d)", err);
+		return err;
+	}
+
+	switch (cfg->mode) {
+	case CORESIGHT_NRF_MODE_UNCONFIGURED: {
+		return 0;
+	}
+	case CORESIGHT_NRF_MODE_STM_TPIU: {
+		return coresight_nrf_init_stm_tpiu();
+	}
+	case CORESIGHT_NRF_MODE_STM_ETR: {
+		uintptr_t etr_buffer = DT_REG_ADDR(DT_NODELABEL(etr_buffer));
+		size_t buf_word_len = DT_REG_SIZE(DT_NODELABEL(etr_buffer)) / sizeof(uint32_t);
+
+		return coresight_nrf_init_stm_etr(etr_buffer, buf_word_len);
+	}
+	default: {
+		LOG_ERR("Unsupported Coresight mode");
+		return -ENOTSUP;
+	}
+	}
+	return 0;
+}
+
+#define DEBUG_CORESIGHT_NRF_INIT_PRIORITY UTIL_INC(CONFIG_NRF_IRONSIDE_CALL_INIT_PRIORITY)
+
+#define CORESIGHT_NRF_INST(inst)                                                                   \
+	COND_CODE_1(DT_INST_PINCTRL_HAS_IDX(inst, 0),                                      \
+		    (PINCTRL_DT_INST_DEFINE(inst);), ())       \
+                                                                                                   \
+	static struct coresight_nrf_config coresight_nrf_cfg_##inst = {                            \
+		.mode = _CONCAT(CORESIGHT_NRF_MODE_,                                               \
+				DT_STRING_UPPER_TOKEN(DT_DRV_INST(inst), mode)),                   \
+		.pcfg = COND_CODE_1(DT_INST_PINCTRL_HAS_IDX(inst, 0),                     \
+				    (PINCTRL_DT_INST_DEV_CONFIG_GET(inst)),               \
+				    (NULL)) };                  \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, coresight_nrf_init, NULL, NULL, &coresight_nrf_cfg_##inst,     \
+			      POST_KERNEL, DEBUG_CORESIGHT_NRF_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(CORESIGHT_NRF_INST)
diff --git a/drivers/misc/coresight/nrf_etr.c b/drivers/debug/debug_nrf_etr.c
similarity index 90%
rename from drivers/misc/coresight/nrf_etr.c
rename to drivers/debug/debug_nrf_etr.c
index bf1aecd6f5b47..d536cd4a9f40e 100644
--- a/drivers/misc/coresight/nrf_etr.c
+++ b/drivers/debug/debug_nrf_etr.c
@@ -16,7 +16,7 @@
 #include <zephyr/debug/coresight/cs_trace_defmt.h>
 #include <zephyr/debug/mipi_stp_decoder.h>
 #include <zephyr/linker/devicetree_regions.h>
-#include <zephyr/drivers/misc/coresight/nrf_etr.h>
+#include <zephyr/drivers/debug/debug_nrf_etr.h>
 #include <zephyr/drivers/serial/uart_async_rx.h>
 #include <zephyr/sys/printk.h>
 #include <dmm.h>
@@ -29,15 +29,15 @@ LOG_MODULE_REGISTER(cs_etr_tbm);
 #define ETR_BUFFER_NODE DT_NODELABEL(etr_buffer)
 
 #define DROP_CHECK_PERIOD                            \
-	COND_CODE_1(CONFIG_NRF_ETR_DECODE, \
-		    (CONFIG_NRF_ETR_DECODE_DROP_PERIOD), (0))
+	COND_CODE_1(CONFIG_DEBUG_NRF_ETR_DECODE, \
+		    (CONFIG_DEBUG_NRF_ETR_DECODE_DROP_PERIOD), (0))
 
 #define MIN_DATA (2 * CORESIGHT_TRACE_FRAME_SIZE32)
 
 /* Since ETR debug is a part of logging infrastructure, logging cannot be used
  * for debugging. Printk is used (assuming CONFIG_LOG_PRINTK=n)
  */
-#define DBG(...) IF_ENABLED(CONFIG_NRF_ETR_DEBUG, (printk(__VA_ARGS__)))
+#define DBG(...) IF_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG, (printk(__VA_ARGS__)))
 
 /** @brief Macro for dumping debug data.
  *
@@ -86,10 +86,10 @@ static const struct device *uart_dev = DEVICE_DT_GET(UART_NODE);
 static uint32_t frame_buf0[CORESIGHT_TRACE_FRAME_SIZE32] DMM_MEMORY_SECTION(UART_NODE);
 static uint32_t frame_buf1[CORESIGHT_TRACE_FRAME_SIZE32] DMM_MEMORY_SECTION(UART_NODE);
 static uint32_t frame_buf_decode[CORESIGHT_TRACE_FRAME_SIZE32];
-static uint32_t *frame_buf = IS_ENABLED(CONFIG_NRF_ETR_DECODE) ?
+static uint32_t *frame_buf = IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) ?
 				frame_buf_decode : frame_buf0;
 
-K_KERNEL_STACK_DEFINE(etr_stack, CONFIG_NRF_ETR_STACK_SIZE);
+K_KERNEL_STACK_DEFINE(etr_stack, CONFIG_DEBUG_NRF_ETR_STACK_SIZE);
 static struct k_thread etr_thread;
 
 BUILD_ASSERT((DT_REG_SIZE(ETR_BUFFER_NODE) % CONFIG_DCACHE_LINE_SIZE) == 0);
@@ -134,9 +134,10 @@ static const char *const hw_evts[] = {
 	"GD0 HS down", /* 31 Global domain high speed 0 down */
 };
 
-#ifdef CONFIG_NRF_ETR_SHELL
+#ifdef CONFIG_DEBUG_NRF_ETR_SHELL
 #define RX_BUF_SIZE \
-	(CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE * CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT)
+	(CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE * \
+	CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT)
 
 static void etr_timer_handler(struct k_timer *timer);
 K_TIMER_DEFINE(etr_timer, etr_timer_handler, NULL);
@@ -278,7 +279,7 @@ static void message_process(union log_frontend_stmesp_demux_packet packet)
  */
 static void sync_loss(void)
 {
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) {
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) {
 		mipi_stp_decoder_sync_loss();
 		log_frontend_stmesp_demux_reset();
 		oosync_cnt++;
@@ -292,7 +293,7 @@ static void sync_loss(void)
  */
 static void on_resync(void)
 {
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) {
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) {
 		in_sync = true;
 	}
 }
@@ -365,7 +366,7 @@ static void decoder_cb(enum mipi_stp_decoder_ctrl_type type,
 
 	decoder_cb_debug(type, data, ts, marked);
 
-	if (!IS_ENABLED(CONFIG_NRF_ETR_DECODE)) {
+	if (!IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) {
 		return;
 	}
 
@@ -549,7 +550,7 @@ static void dump_frame(uint8_t *buf)
 static void process(void)
 {
 	static const uint32_t *const etr_buf = (uint32_t *)(DT_REG_ADDR(ETR_BUFFER_NODE));
-	static uint32_t sync_cnt;
+	static uint32_t sync_cnt = CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD;
 	uint32_t pending;
 
 	/* If function is called in panic mode then it may interrupt ongoing
@@ -562,7 +563,7 @@ static void process(void)
 	 */
 	while ((pending = pending_data()) >= MIN_DATA) {
 		/* Do not read the data that has already been read but not yet processed. */
-		if (sync_cnt || (CONFIG_NRF_ETR_SYNC_PERIOD == 0)) {
+		if (sync_cnt || (CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD == 0)) {
 			sync_cnt--;
 			sys_cache_data_invd_range((void *)&etr_buf[etr_rd_idx & wsize_mask],
 						  CORESIGHT_TRACE_FRAME_SIZE);
@@ -572,11 +573,12 @@ static void process(void)
 			rd_idx_inc();
 			__sync_synchronize();
 		} else {
-			sync_cnt = CONFIG_NRF_ETR_SYNC_PERIOD;
+			sync_cnt = CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD;
 			memset(frame_buf, 0xff, CORESIGHT_TRACE_FRAME_SIZE);
 		}
 
-		if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) {
+		if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) ||
+		    IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) {
 			if ((pending >= (wsize_mask - MIN_DATA)) ||
 			    (pending_data() >= (wsize_mask - MIN_DATA))) {
 				/* If before or after reading the frame it is close to full
@@ -586,7 +588,7 @@ static void process(void)
 			}
 
 			process_frame((uint8_t *)frame_buf, pending);
-			if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) {
+			if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) {
 				process_messages();
 			}
 		} else {
@@ -612,7 +614,7 @@ static int decoder_init(void)
 	}
 
 	once = true;
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) {
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) {
 		static const struct log_frontend_stmesp_demux_config config = {
 			.m_ids = stm_m_id,
 			.m_ids_cnt = ARRAY_SIZE(stm_m_id),
@@ -635,12 +637,12 @@ static int decoder_init(void)
 	return 0;
 }
 
-void nrf_etr_flush(void)
+void debug_nrf_etr_flush(void)
 {
 	int cnt = 4;
 
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) ||
-	    IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) {
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) ||
+	    IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) {
 		(void)decoder_init();
 	}
 
@@ -658,13 +660,13 @@ void nrf_etr_flush(void)
 	irq_unlock(k);
 }
 
-#ifndef CONFIG_NRF_ETR_SHELL
+#ifndef CONFIG_DEBUG_NRF_ETR_SHELL
 static void etr_thread_func(void *dummy1, void *dummy2, void *dummy3)
 {
 	uint64_t checkpoint = 0;
 
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) ||
-	    IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) {
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) ||
+	    IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) {
 		int err;
 
 		err = decoder_init();
@@ -688,7 +690,7 @@ static void etr_thread_func(void *dummy1, void *dummy2, void *dummy3)
 			}
 		}
 
-		k_sleep(K_MSEC(CONFIG_NRF_ETR_BACKOFF));
+		k_sleep(K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF));
 	}
 }
 #endif
@@ -703,7 +705,7 @@ static void uart_event_handler(const struct device *dev, struct uart_event *evt,
 	case UART_TX_DONE:
 		k_sem_give(&uart_sem);
 		break;
-#ifdef CONFIG_NRF_ETR_SHELL
+#ifdef CONFIG_DEBUG_NRF_ETR_SHELL
 	case UART_RX_RDY:
 		uart_async_rx_on_rdy(&async_rx, evt->data.rx.buf, evt->data.rx.len);
 		shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, shell_context);
@@ -729,7 +731,7 @@ static void uart_event_handler(const struct device *dev, struct uart_event *evt,
 		break;
 	case UART_RX_DISABLED:
 		break;
-#endif /* CONFIG_NRF_ETR_SHELL */
+#endif /* CONFIG_DEBUG_NRF_ETR_SHELL */
 	default:
 		__ASSERT_NO_MSG(0);
 	}
@@ -743,7 +745,7 @@ static void tbm_event_handler(nrf_tbm_event_t event)
 		tbm_full = true;
 	}
 
-#ifdef CONFIG_NRF_ETR_SHELL
+#ifdef CONFIG_DEBUG_NRF_ETR_SHELL
 	k_poll_signal_raise(&etr_shell.ctx->signals[SHELL_SIGNAL_LOG_MSG], 0);
 #else
 	k_wakeup(&etr_thread);
@@ -766,15 +768,16 @@ int etr_process_init(void)
 	IRQ_CONNECT(DT_IRQN(DT_NODELABEL(tbm)), DT_IRQ(DT_NODELABEL(tbm), priority),
 			    nrfx_isr, nrfx_tbm_irq_handler, 0);
 	irq_enable(DT_IRQN(DT_NODELABEL(tbm)));
+	nrfx_tbm_start();
 
-#ifdef CONFIG_NRF_ETR_SHELL
+#ifdef CONFIG_DEBUG_NRF_ETR_SHELL
 	uint32_t level = CONFIG_LOG_MAX_LEVEL;
 	static const struct shell_backend_config_flags cfg_flags =
 		SHELL_DEFAULT_BACKEND_CONFIG_FLAGS;
 
 	shell_init(&etr_shell, NULL, cfg_flags, true, level);
-	k_timer_start(&etr_timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT);
-	if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) {
+	k_timer_start(&etr_timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT);
+	if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) {
 		err = decoder_init();
 		if (err < 0) {
 			return err;
@@ -789,16 +792,26 @@ int etr_process_init(void)
 	return 0;
 }
 
-SYS_INIT(etr_process_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#define NRF_ETR_INIT_PRIORITY UTIL_INC(UTIL_INC(CONFIG_NRF_IRONSIDE_CALL_INIT_PRIORITY))
 
-#ifdef CONFIG_NRF_ETR_SHELL
+SYS_INIT(etr_process_init, POST_KERNEL, NRF_ETR_INIT_PRIORITY);
+
+#if defined(CONFIG_NORDIC_VPR_LAUNCHER) && defined(CONFIG_LOG_FRONTEND_STMESP_FSC)
+/* TDD/ETR must be up and running before VPR cores are started as they write to
+ * ETR some vital initial data that cannot be lost.
+ */
+BUILD_ASSERT(CONFIG_NORDIC_VPR_LAUNCHER_INIT_PRIORITY > NRF_ETR_INIT_PRIORITY);
+#endif
+
+
+#ifdef CONFIG_DEBUG_NRF_ETR_SHELL
 
 static void etr_timer_handler(struct k_timer *timer)
 {
 	if (pending_data() >= MIN_DATA) {
 		k_poll_signal_raise(&etr_shell.ctx->signals[SHELL_SIGNAL_LOG_MSG], 0);
 	} else {
-		k_timer_start(timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT);
+		k_timer_start(timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT);
 	}
 }
 
@@ -807,7 +820,7 @@ bool z_shell_log_backend_process(const struct shell_log_backend *backend)
 	ARG_UNUSED(backend);
 
 	process();
-	k_timer_start(&etr_timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT);
+	k_timer_start(&etr_timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT);
 
 	return false;
 }
@@ -901,7 +914,7 @@ static int etr_shell_init(const struct shell_transport *transport, const void *c
 	static const struct uart_async_rx_config async_rx_config = {
 		.buffer = rx_buf,
 		.length = sizeof(rx_buf),
-		.buf_cnt = CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT,
+		.buf_cnt = CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT,
 	};
 
 	shell_context = context;
@@ -939,6 +952,6 @@ static struct shell_transport transport = {
 };
 
 static uint8_t shell_out_buffer[CONFIG_SHELL_PRINTF_BUFF_SIZE];
-Z_SHELL_DEFINE(etr_shell, CONFIG_NRF_ETR_SHELL_PROMPT, &transport, shell_out_buffer, NULL,
+Z_SHELL_DEFINE(etr_shell, CONFIG_DEBUG_NRF_ETR_SHELL_PROMPT, &transport, shell_out_buffer, NULL,
 	       SHELL_FLAG_OLF_CRLF);
-#endif /* CONFIG_NRF_ETR_SHELL */
+#endif /* CONFIG_DEBUG_NRF_ETR_SHELL */
diff --git a/drivers/misc/CMakeLists.txt b/drivers/misc/CMakeLists.txt
index 437bd124247a6..8426090ab14ec 100644
--- a/drivers/misc/CMakeLists.txt
+++ b/drivers/misc/CMakeLists.txt
@@ -15,5 +15,4 @@ add_subdirectory_ifdef(CONFIG_RENESAS_RX_EXTERNAL_INTERRUPT renesas_rx_external_
 add_subdirectory_ifdef(CONFIG_NXP_RTXXX_DSP_CTRL nxp_rtxxx_dsp_ctrl)
 add_subdirectory_ifdef(CONFIG_STM32N6_AXISRAM stm32n6_axisram)
 
-add_subdirectory(coresight)
 add_subdirectory(interconn)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6d4d5cfc16fe0..0a3af14dc2c08 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -15,7 +15,6 @@ source "drivers/misc/timeaware_gpio/Kconfig"
 source "drivers/misc/devmux/Kconfig"
 source "drivers/misc/nordic_vpr_launcher/Kconfig"
 source "drivers/misc/mcux_flexio/Kconfig"
-source "drivers/misc/coresight/Kconfig"
 source "drivers/misc/interconn/Kconfig"
 source "drivers/misc/renesas_ra_external_interrupt/Kconfig"
 source "drivers/misc/renesas_rx_external_interrupt/Kconfig"
diff --git a/drivers/misc/coresight/CMakeLists.txt b/drivers/misc/coresight/CMakeLists.txt
deleted file mode 100644
index 1ec34ca2f75a4..0000000000000
--- a/drivers/misc/coresight/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_NRF_ETR nrf_etr.c)
diff --git a/drivers/misc/nordic_vpr_launcher/Kconfig b/drivers/misc/nordic_vpr_launcher/Kconfig
index d00bcc583f96d..edd2a9ead753c 100644
--- a/drivers/misc/nordic_vpr_launcher/Kconfig
+++ b/drivers/misc/nordic_vpr_launcher/Kconfig
@@ -18,6 +18,7 @@ source "subsys/logging/Kconfig.template.log_config"
 
 config NORDIC_VPR_LAUNCHER_INIT_PRIORITY
 	int "Nordic VPR coprocessor launcher init priority"
+	default 44 if DT_HAS_NORDIC_CORESIGHT_NRF_ENABLED
 	default 0
 	help
 	  The init priority of the VPR coprocessor launcher.
diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c
index 429ed761e6145..ac9b17d27b394 100644
--- a/drivers/pinctrl/pinctrl_nrf.c
+++ b/drivers/pinctrl/pinctrl_nrf.c
@@ -557,6 +557,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_CONNECT;
 			break;
 #endif /* defined(NRF_PSEL_TWIS) */
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf)
+		/* Pin routing is controlled by secure domain, via UICR */
+		case NRF_FUN_TPIU_CLOCK:
+		case NRF_FUN_TPIU_DATA0:
+		case NRF_FUN_TPIU_DATA1:
+		case NRF_FUN_TPIU_DATA2:
+		case NRF_FUN_TPIU_DATA3:
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf) */
 		default:
 			return -ENOTSUP;
 		}
diff --git a/dts/bindings/arm/nordic,nrf-tddconf.yaml b/dts/bindings/arm/nordic,nrf-tddconf.yaml
deleted file mode 100644
index 2273082c12f94..0000000000000
--- a/dts/bindings/arm/nordic,nrf-tddconf.yaml
+++ /dev/null
@@ -1,44 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Nordic TRACE and Debug Domain
-
-  Configuration for the Trace and Debug subsystem
-
-compatible: "nordic,nrf-tddconf"
-
-include: base.yaml
-
-properties:
-  etbsources:
-    type: int
-    description: |
-      Bitmask of enabled sources for the ETB sink. Valid values can be found in
-      dt-bindings/misc/nordic-tddconf.h
-
-  tpiusources:
-    type: int
-    description: |
-      Bitmask of enabled sources for the TPIU sink. Valid values can be found in
-      dt-bindings/misc/nordic-tddconf.h
-
-  etrsources:
-    type: int
-    description: |
-      Bitmask of enabled sources for the ETR sink. Valid values can be found in
-      dt-bindings/misc/nordic-tddconf.h
-
-  portconfig:
-    type: int
-    default: 3
-    description: TPIU clock divider - TDD HSFLL / 2^(2 + portconfig)
-    enum:
-      - 0
-      - 1
-      - 2
-      - 3
-
-  etrbuffer:
-    description: phandle to the memory region used for the ETR buffer
-    type: phandle
diff --git a/dts/bindings/debug/nordic,coresight-nrf.yaml b/dts/bindings/debug/nordic,coresight-nrf.yaml
new file mode 100644
index 0000000000000..fec4f37ce5a97
--- /dev/null
+++ b/dts/bindings/debug/nordic,coresight-nrf.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Coresight Subsystem (Trace Port Interface Unit)
+
+compatible: "nordic,coresight-nrf"
+
+include: [base.yaml, pinctrl-device.yaml, nordic-clockpin.yaml]
+
+properties:
+  reg:
+    required: true
+
+  mode:
+    required: true
+    type: string
+    enum:
+      - "unconfigured"
+      - "stm-tpiu"
+      - "stm-etr"
+    description: >
+      Specifies which mode to configure the Coresight subsystem in.
diff --git a/dts/bindings/misc/nordic,nrf-tbm.yaml b/dts/bindings/debug/nordic,nrf-tbm.yaml
similarity index 100%
rename from dts/bindings/misc/nordic,nrf-tbm.yaml
rename to dts/bindings/debug/nordic,nrf-tbm.yaml
diff --git a/dts/vendor/nordic/nrf54h20.dtsi b/dts/vendor/nordic/nrf54h20.dtsi
index b6f93c5ce52dd..4564cdaebf15e 100644
--- a/dts/vendor/nordic/nrf54h20.dtsi
+++ b/dts/vendor/nordic/nrf54h20.dtsi
@@ -13,7 +13,6 @@
 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
-#include <zephyr/dt-bindings/misc/nordic-tddconf.h>
 
 /delete-node/ &sw_pwm;
 
@@ -543,10 +542,82 @@
 				interrupts = <127 NRF_DEFAULT_IRQ_PRIORITY>;
 			};
 
-			tddconf: tddconf@1000 {
-				compatible = "nordic,nrf-tddconf";
-				reg = <0x1000 0x10>;
+			hsfll200: clock@4000 {
+				compatible = "fixed-clock";
+				reg = <0x4000 0x1000>;
+				#clock-cells = <0>;
+				status = "disabled";
+				clock-frequency = <DT_FREQ_M(320)>;
+			};
+
+			coresight: coresight@40000 {
+				compatible = "nordic,coresight-nrf";
+				reg = <0x40000 0x11000>;
 				status = "disabled";
+				nordic,clockpin-enable = <NRF_FUN_TPIU_CLOCK>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x40000 0x11000>;
+
+				tsgen: tsgen@1000 {
+					reg = <0x1000 0x1000>;
+				};
+
+				stm: stm@2000 {
+					reg = <0x2000 0x1000>;
+				};
+
+				tpiu: tpiu@3000 {
+					reg = <0x3000 0x1000>;
+				};
+
+				etb: etb@4000 {
+					reg = <0x4000 0x1000>;
+				};
+
+				etr: etr@5000 {
+					reg = <0x5000 0x1000>;
+				};
+
+				cti210: cti@6000 {
+					reg = <0x6000 0x1000>;
+				};
+
+				cti211: cti@7000 {
+					reg = <0x7000 0x1000>;
+				};
+
+				atbreplicator210: atbreplicator@8000 {
+					reg = <0x8000 0x1000>;
+				};
+
+				atbreplicator211: atbreplicator@9000 {
+					reg = <0x9000 0x1000>;
+				};
+
+				atbreplicator212: atbreplicator@A000 {
+					reg = <0xA000 0x1000>;
+				};
+
+				atbreplicator213: atbreplicator@B000 {
+					reg = <0xB000 0x1000>;
+				};
+
+				atbfunnel210: atbfunnel@C000 {
+					reg = <0xC000 0x1000>;
+				};
+
+				atbfunnel211: atbfunnel@D000 {
+					reg = <0xD000 0x1000>;
+				};
+
+				atbfunnel212: atbfunnel@E000 {
+					reg = <0xE000 0x1000>;
+				};
+
+				atbfunnel213: atbfunnel@F000 {
+					reg = <0xF000 0x1000>;
+				};
 			};
 		};
 
diff --git a/include/zephyr/drivers/misc/coresight/nrf_etr.h b/include/zephyr/drivers/debug/debug_nrf_etr.h
similarity index 52%
rename from include/zephyr/drivers/misc/coresight/nrf_etr.h
rename to include/zephyr/drivers/debug/debug_nrf_etr.h
index 062afa3b61aae..04805a7e2d1d3 100644
--- a/include/zephyr/drivers/misc/coresight/nrf_etr.h
+++ b/include/zephyr/drivers/debug/debug_nrf_etr.h
@@ -3,18 +3,18 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_
-#define _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_
+#ifndef _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_
+#define _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /** @brief Flush data from the ETR buffer. */
-void nrf_etr_flush(void);
+void debug_nrf_etr_flush(void);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ */
+#endif /* _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_ */
diff --git a/include/zephyr/drivers/misc/coresight/stmesp.h b/include/zephyr/drivers/debug/stmesp.h
similarity index 96%
rename from include/zephyr/drivers/misc/coresight/stmesp.h
rename to include/zephyr/drivers/debug/stmesp.h
index ce0f64b52dded..d4b245857eb3e 100644
--- a/include/zephyr/drivers/misc/coresight/stmesp.h
+++ b/include/zephyr/drivers/debug/stmesp.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_
-#define ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_
+#ifndef ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_
+#define ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_
 
 #include <zephyr/devicetree.h>
 
@@ -190,4 +190,4 @@ static inline int stmesp_get_port(uint32_t idx, STMESP_Type **port)
  * @}
  */
 
-#endif /* ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ */
+#endif /* ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_ */
diff --git a/include/zephyr/dt-bindings/misc/nordic-tddconf.h b/include/zephyr/dt-bindings/misc/nordic-tddconf.h
deleted file mode 100644
index 44bc74e491c02..0000000000000
--- a/include/zephyr/dt-bindings/misc/nordic-tddconf.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_
-
-#define NRF_TDDCONF_SOURCE_STMMAINCORE BIT(0)
-#define NRF_TDDCONF_SOURCE_ETMMAINCORE BIT(1)
-#define NRF_TDDCONF_SOURCE_STMHWEVENTS BIT(2)
-#define NRF_TDDCONF_SOURCE_STMPPR      BIT(3)
-#define NRF_TDDCONF_SOURCE_STMFLPR     BIT(4)
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
index 42b302193ed0a..92e62a9a6bed3 100644
--- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
@@ -187,7 +187,17 @@
 /** TDM MCK */
 #define NRF_FUN_TDM_MCK          77U
 /** SPI master CSN */
-#define NRF_FUN_SPIM_CSN 78U
+#define NRF_FUN_SPIM_CSN         78U
+/** TPIU CLOCK */
+#define NRF_FUN_TPIU_CLOCK       79U
+/** TPIU DATA0 */
+#define NRF_FUN_TPIU_DATA0       80U
+/** TPIU DATA1 */
+#define NRF_FUN_TPIU_DATA1       81U
+/** TPIU DATA2 */
+#define NRF_FUN_TPIU_DATA2       82U
+/** TPIU DATA3 */
+#define NRF_FUN_TPIU_DATA3       83U
 
 /** @} */
 
diff --git a/include/zephyr/logging/log_frontend_stmesp.h b/include/zephyr/logging/log_frontend_stmesp.h
index 38f33bf62f102..c30972319fa74 100644
--- a/include/zephyr/logging/log_frontend_stmesp.h
+++ b/include/zephyr/logging/log_frontend_stmesp.h
@@ -9,7 +9,7 @@
 #include <errno.h>
 #include <zephyr/types.h>
 #ifdef CONFIG_LOG_FRONTEND_STMESP
-#include <zephyr/drivers/misc/coresight/stmesp.h>
+#include <zephyr/drivers/debug/stmesp.h>
 #endif
 
 #ifdef __cplusplus
diff --git a/samples/boards/nordic/coresight_stm/prj.conf b/samples/boards/nordic/coresight_stm/prj.conf
index 1e935e973c761..9ee7cf8cc03a8 100644
--- a/samples/boards/nordic/coresight_stm/prj.conf
+++ b/samples/boards/nordic/coresight_stm/prj.conf
@@ -1 +1,2 @@
 CONFIG_LOG=y
+CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y
diff --git a/samples/boards/nordic/coresight_stm/pytest/test_stm.py b/samples/boards/nordic/coresight_stm/pytest/test_stm.py
index 4af24fbfa3c94..6db0b56857592 100644
--- a/samples/boards/nordic/coresight_stm/pytest/test_stm.py
+++ b/samples/boards/nordic/coresight_stm/pytest/test_stm.py
@@ -20,7 +20,7 @@
 SB_CONFIG_APP_CPUFLPR_RUN = None
 
 # See definition of stm_m_id[] and stm_m_name[] in
-# https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/misc/coresight/nrf_etr.c
+# https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/debug/debug_nrf_etr.c
 STM_M_ID = {
     "sec": 33,
     "app": 34,
diff --git a/samples/boards/nordic/coresight_stm/sample.yaml b/samples/boards/nordic/coresight_stm/sample.yaml
index 000241d4d979e..9ff835d8ffadf 100644
--- a/samples/boards/nordic/coresight_stm/sample.yaml
+++ b/samples/boards/nordic/coresight_stm/sample.yaml
@@ -22,6 +22,13 @@ tests:
       - SB_CONFIG_APP_CPUPPR_RUN=y
       - SB_CONFIG_APP_CPUFLPR_RUN=y
 
+  sample.boards.nrf.coresight_stm.tpiu.dict:
+    required_snippets:
+      - nordic-log-stm-tpiu-dict
+    extra_args:
+      - SB_CONFIG_APP_CPUPPR_RUN=y
+      - SB_CONFIG_APP_CPUFLPR_RUN=y
+
   sample.boards.nrf.coresight_stm:
     harness: pytest
     harness_config:
diff --git a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay
index fec5481736486..962aa231b7a9f 100644
--- a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay
+++ b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay
@@ -7,10 +7,7 @@
 	status = "okay";
 };
 
-&tddconf {
+&coresight {
 	status = "okay";
-	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR |
-		NRF_TDDCONF_SOURCE_STMFLPR)>;
-	portconfig = <0>;
-	etrbuffer = <&etr_buffer>;
+	mode = "stm-etr";
 };
diff --git a/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf b/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf
index 7384e36b92a2f..0bd8b46d387e3 100644
--- a/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf
+++ b/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf
@@ -3,3 +3,4 @@ CONFIG_TEST_LOGGING_DEFAULTS=n
 CONFIG_LOG_FRONTEND=y
 CONFIG_LOG_FRONTEND_ONLY=y
 CONFIG_LOG_FRONTEND_STMESP=y
+CONFIG_DEBUG_DRIVER=y
diff --git a/snippets/nordic/nordic-log-stm-dict/snippet.yml b/snippets/nordic/nordic-log-stm-dict/snippet.yml
index 6e4f1c6d23e12..a717d39399b5a 100644
--- a/snippets/nordic/nordic-log-stm-dict/snippet.yml
+++ b/snippets/nordic/nordic-log-stm-dict/snippet.yml
@@ -5,6 +5,3 @@ boards:
   /.*/nrf54h20/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay
-  /.*/nrf54h20/cpurad/:
-    append:
-      EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpurad.overlay
diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst b/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst
new file mode 100644
index 0000000000000..9dbf067671bfc
--- /dev/null
+++ b/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst
@@ -0,0 +1,11 @@
+.. _nordic-log-stm-tpiu-dict:
+
+Nordic Dictionary-based STM to TPIU logging snippet (nordic-log-stm-tpiu-dict)
+##############################################################################
+
+Overview
+********
+
+This snippet allows users to build Zephyr with the dictionary-based logging to
+the Coresight STM stimulus ports. Data is written to the TPIU interface and can
+be captured with nrfutil trace to translate into a human-readable format.
diff --git a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay
similarity index 54%
rename from snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay
rename to snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay
index 5bdeddd3c07f2..e6f14f46a6a4f 100644
--- a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay
+++ b/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay
@@ -3,7 +3,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-&tddconf {
+&coresight {
 	status = "okay";
-	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>;
+	mode = "stm-tpiu";
+	pinctrl-0 = <&tpiu_default>;
+	pinctrl-names = "default";
 };
diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf b/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf
new file mode 100644
index 0000000000000..0bd8b46d387e3
--- /dev/null
+++ b/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf
@@ -0,0 +1,6 @@
+CONFIG_LOG=y
+CONFIG_TEST_LOGGING_DEFAULTS=n
+CONFIG_LOG_FRONTEND=y
+CONFIG_LOG_FRONTEND_ONLY=y
+CONFIG_LOG_FRONTEND_STMESP=y
+CONFIG_DEBUG_DRIVER=y
diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml b/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml
new file mode 100644
index 0000000000000..32cd36d377eaa
--- /dev/null
+++ b/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml
@@ -0,0 +1,7 @@
+name: nordic-log-stm-tpiu-dict
+append:
+  EXTRA_CONF_FILE: log_stm_dict.conf
+boards:
+  /.*/nrf54h20/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay
diff --git a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay
index fec5481736486..962aa231b7a9f 100644
--- a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay
+++ b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay
@@ -7,10 +7,7 @@
 	status = "okay";
 };
 
-&tddconf {
+&coresight {
 	status = "okay";
-	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR |
-		NRF_TDDCONF_SOURCE_STMFLPR)>;
-	portconfig = <0>;
-	etrbuffer = <&etr_buffer>;
+	mode = "stm-etr";
 };
diff --git a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay
deleted file mode 100644
index 5bdeddd3c07f2..0000000000000
--- a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&tddconf {
-	status = "okay";
-	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>;
-};
diff --git a/snippets/nordic/nordic-log-stm/log_stm.conf b/snippets/nordic/nordic-log-stm/log_stm.conf
index 1325c25b505fc..46550a258cd1e 100644
--- a/snippets/nordic/nordic-log-stm/log_stm.conf
+++ b/snippets/nordic/nordic-log-stm/log_stm.conf
@@ -4,3 +4,4 @@ CONFIG_LOG_FRONTEND=y
 CONFIG_LOG_FRONTEND_ONLY=y
 CONFIG_LOG_FRONTEND_STMESP=y
 CONFIG_LOG_FRONTEND_STMESP_FSC=y
+CONFIG_DEBUG_DRIVER=y
diff --git a/snippets/nordic/nordic-log-stm/snippet.yml b/snippets/nordic/nordic-log-stm/snippet.yml
index 0a984a8312cc0..918379360afca 100644
--- a/snippets/nordic/nordic-log-stm/snippet.yml
+++ b/snippets/nordic/nordic-log-stm/snippet.yml
@@ -5,6 +5,3 @@ boards:
   /.*/nrf54h20/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay
-  /.*/nrf54h20/cpurad/:
-    append:
-      EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpurad.overlay
diff --git a/soc/nordic/common/uicr/gen_periphconf_entries.py b/soc/nordic/common/uicr/gen_periphconf_entries.py
index 4308df31449fa..9a273dab7a598 100644
--- a/soc/nordic/common/uicr/gen_periphconf_entries.py
+++ b/soc/nordic/common/uicr/gen_periphconf_entries.py
@@ -121,6 +121,10 @@ def main() -> None:
     for node in dt.label2node["global_peripherals"].children.values():
         builder.add_global_peripheral_cfg(node, **get_additional_node_kwargs(node))
 
+    # TDD (Trace and Debug Domain) peripherals - contains coresight/TPIU
+    for node in dt.label2node["tdd_peripherals"].children.values():
+        builder.add_global_peripheral_cfg(node, **get_additional_node_kwargs(node))
+
     # Add pins referenced by 'gpios' properties on non-peripheral nodes, for example
     # buttons and leds. We only add SPU configurations for these and not CTRLSEL,
     # to avoid false CTRLSEL conflicts for things like PWM leds.
@@ -425,6 +429,14 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables:
                 NrfPsel(fun=NrfFun.IGNORE, port=2, pin=10): Ctrlsel.CAN,
                 NrfPsel(fun=NrfFun.IGNORE, port=2, pin=11): Ctrlsel.CAN,
             },
+            # Coresight (TPIU)
+            0xBF04_0000: {
+                NrfPsel(fun=NrfFun.TPIU_CLOCK, port=7, pin=3): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA0, port=7, pin=4): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA1, port=7, pin=5): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA2, port=7, pin=6): Ctrlsel.TND,
+                NrfPsel(fun=NrfFun.TPIU_DATA3, port=7, pin=7): Ctrlsel.TND,
+            },
         }
     elif soc == Soc.NRF9280:
         ctrlsel_lookup = {
diff --git a/soc/nordic/common/uicr/periphconf/builder.py b/soc/nordic/common/uicr/periphconf/builder.py
index 1a343dee44a06..b8387fd9a7567 100644
--- a/soc/nordic/common/uicr/periphconf/builder.py
+++ b/soc/nordic/common/uicr/periphconf/builder.py
@@ -41,6 +41,9 @@
     "nordic,nrf-temp",
     "nordic,nrf-vevif-task-tx",
     "nordic,nrf-vevif-task-rx",
+    # No retention in TDD so permissions can't be set outside of the TDD service
+    "nordic,coresight-nrf",
+    "nordic,nrf-tbm",
 }
 
 # Compatibles of global peripherals that should be assigned to the current core but do not have DMA
@@ -1018,6 +1021,11 @@ class NrfFun(int, enum.Enum):
     TDM_SDOUT = 76
     TDM_MCK = 77
     SPIM_CSN = 78
+    TPIU_CLOCK = 79
+    TPIU_DATA0 = 80
+    TPIU_DATA1 = 81
+    TPIU_DATA2 = 82
+    TPIU_DATA3 = 83
 
     # Value used to ignore the function field and only check (port, pin)
     IGNORE = -1
diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig
index 7e23aad4d2331..d5632943e19f7 100644
--- a/soc/nordic/nrf54h/Kconfig
+++ b/soc/nordic/nrf54h/Kconfig
@@ -68,17 +68,6 @@ config SOC_NRF54H20_CPURAD_COMMON
 	select HAS_PM_S2RAM_CUSTOM_MARKING
 	select HAS_POWEROFF
 
-config SOC_NRF54H20_TDD_ENABLE
-	bool "Power and configure the trace and debug domain (TDD)"
-	depends on SOC_NRF54H20_CPUAPP
-	select NRF_IRONSIDE_TDD_SERVICE
-	select SOC_LATE_INIT_HOOK
-	help
-	  This will at application boot time request that the trace and
-	  debug domain (TDD) is powered up and configured.
-	  This allows configuring the coresight peripherals from
-	  the application domain.
-
 config SOC_NRF54H20_CPURAD_ENABLE
 	bool "Boot the nRF54H20 Radio core"
 	default y if NRF_802154_SER_HOST || BT_HCI_HOST
diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp
index f2e0343d6350d..bc16629ae4367 100644
--- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp
+++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp
@@ -9,7 +9,7 @@ config NUM_IRQS
 	default 471
 
 config SHELL_BACKEND_SERIAL
-	default n if NRF_ETR_SHELL
+	default n if DEBUG_NRF_ETR_SHELL
 
 config POWER_DOMAIN
 	default y
diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c
index 1206e6767aa28..8493aa03bc345 100644
--- a/soc/nordic/nrf54h/soc.c
+++ b/soc/nordic/nrf54h/soc.c
@@ -22,14 +22,10 @@
 #include <soc/nrfx_coredep.h>
 #include <soc_lrcconf.h>
 #include <dmm.h>
-#include <uicr/uicr.h>
 
 #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
 #include <nrf_ironside/cpuconf.h>
 #endif
-#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE)
-#include <nrf_ironside/tdd.h>
-#endif
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -183,20 +179,6 @@ void soc_early_init_hook(void)
 
 void soc_late_init_hook(void)
 {
-#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE)
-	int err_tdd;
-
-	err_tdd = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT);
-	__ASSERT(err_tdd == 0, "err_tdd was %d", err_tdd);
-
-	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 3, GPIO_PIN_CNF_CTRLSEL_TND);
-	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 4, GPIO_PIN_CNF_CTRLSEL_TND);
-	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 5, GPIO_PIN_CNF_CTRLSEL_TND);
-	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 6, GPIO_PIN_CNF_CTRLSEL_TND);
-	UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 7, GPIO_PIN_CNF_CTRLSEL_TND);
-
-#endif
-
 #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
 	int err_cpuconf;
 
diff --git a/subsys/logging/frontends/Kconfig b/subsys/logging/frontends/Kconfig
index 6e56027635742..8bad85c69814b 100644
--- a/subsys/logging/frontends/Kconfig
+++ b/subsys/logging/frontends/Kconfig
@@ -46,7 +46,7 @@ config LOG_FRONTEND_STMESP_DICT
 
 config LOG_FRONTEND_STMESP_FSC
 	bool "Send fully self-contained messages"
-	select LOG_MSG_APPEND_RO_STRING_LOC if !(NRF_ETR || \
+	select LOG_MSG_APPEND_RO_STRING_LOC if !(DEBUG_NRF_ETR || \
 			SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR)
 
 config LOG_FRONTEND_STMESP_FLUSH_COUNT
@@ -70,7 +70,7 @@ config LOG_FRONTEND_STMESP_DICT_VER
 config LOG_FRONTEND_STMESP_TURBO_LOG
 	bool "Optimize short_logs"
 	select LOG_CUSTOM_HEADER
-	default y if (NRF_ETR || SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR) \
+	default y if (DEBUG_NRF_ETR || SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR) \
 		     && LOG_FRONTEND_STMESP_FSC
 	help
 	  When enabled, then logging messages with 0 and 1 numeric argument are
diff --git a/subsys/logging/frontends/log_frontend_stmesp.c b/subsys/logging/frontends/log_frontend_stmesp.c
index 0ede3cb48906d..7cdd16ffdd34d 100644
--- a/subsys/logging/frontends/log_frontend_stmesp.c
+++ b/subsys/logging/frontends/log_frontend_stmesp.c
@@ -11,8 +11,8 @@
 #include <zephyr/logging/log_ctrl.h>
 #include <zephyr/logging/log_msg.h>
 #include <zephyr/sys/cbprintf.h>
-#ifdef CONFIG_NRF_ETR
-#include <zephyr/drivers/misc/coresight/nrf_etr.h>
+#ifdef CONFIG_DEBUG_NRF_ETR
+#include <zephyr/drivers/debug/debug_nrf_etr.h>
 #endif
 
 /* Only 32 bit platforms supported. */
@@ -574,15 +574,16 @@ void log_frontend_simple_2(const void *source, uint32_t level, const char *fmt,
 void log_frontend_panic(void)
 {
 	in_panic = true;
-#ifdef CONFIG_NRF_ETR
-	nrf_etr_flush();
+#ifdef CONFIG_DEBUG_NRF_ETR
+	debug_nrf_etr_flush();
 #endif
 }
 
 void log_frontend_init(void)
 {
-#if	defined(CONFIG_LOG_FRONTEND_STPESP_TURBO_SOURCE_PORT_ID) && !defined(CONFIG_NRF_ETR) && \
-	!defined(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)
+#if defined(CONFIG_LOG_FRONTEND_STPESP_TURBO_SOURCE_PORT_ID) \
+	&& !defined(CONFIG_DEBUG_NRF_ETR) \
+	&& !defined(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)
 	/* Send location of section with constant source data. It is used by the
 	 * application core to retrieve source names of log messages coming from
 	 * coprocessors (FLPR and PPR).