diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts index 29f469463255a..755b120f8df41 100644 --- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts @@ -39,8 +39,9 @@ uart3: &scb3 { &peri0_group4_8bit_0 { status = "okay"; - scb-block = <3>; - div-value = <109>; + resource-type = ; + resource-instance = <3>; + clock-div = <109>; }; &path_mux0 { diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts index 49dd0814e0bd0..6a12db41f8fe2 100644 --- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts @@ -39,8 +39,9 @@ uart3: &scb3 { &peri0_group4_8bit_0 { status = "okay"; - scb-block = <3>; - div-value = <109>; + resource-type = ; + resource-instance = <3>; + clock-div = <109>; }; &path_mux0 { diff --git a/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval b/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval new file mode 100644 index 0000000000000..3122e41973bf9 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# PSOC E84 Configuration + +config BOARD_KIT_PSE84_EVAL + select SOC_PSE846GPS2DBZC4A_M33 if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M33 + select SOC_PSE846GPS2DBZC4A_M55 if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55 diff --git a/boards/infineon/kit_pse84_eval/board.cmake b/boards/infineon/kit_pse84_eval/board.cmake new file mode 100644 index 0000000000000..40792b08ad504 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_CPU_CORTEX_M55) + # Connect to the second port for CM55 (default port is 3333) + board_runner_args(openocd "--gdb-init=target extended-remote :3334") +endif() + +board_runner_args(openocd --no-load --no-targets --no-halt) +board_runner_args(openocd "--gdb-init=maint flush register-cache") +board_runner_args(openocd "--gdb-init=tb main") +board_runner_args(openocd "--gdb-init=continue") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +if(CONFIG_CPU_CORTEX_M33 AND CONFIG_TRUSTED_EXECUTION_SECURE) + set_property(TARGET runners_yaml_props_target + PROPERTY hex_file ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.signed.hex) +endif() diff --git a/boards/infineon/kit_pse84_eval/board.yml b/boards/infineon/kit_pse84_eval/board.yml new file mode 100644 index 0000000000000..821aeea313213 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/board.yml @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +board: + name: kit_pse84_eval + full_name: kit_pse84_eval + vendor: infineon + socs: + - name: pse846gps2dbzc4a diff --git a/boards/infineon/kit_pse84_eval/doc/index.rst b/boards/infineon/kit_pse84_eval/doc/index.rst new file mode 100644 index 0000000000000..ffd19ca8206ec --- /dev/null +++ b/boards/infineon/kit_pse84_eval/doc/index.rst @@ -0,0 +1,143 @@ +.. zephyr:board:: kit_pse84_eval + +Overview +******** +The PSOC™ Edge E84 Evaluation Kit enables applications to use the PSOC™ Edge E84 Series +Microcontroller (MCU) together with multiple on-board multimedia, Machine Learning (ML), +and connectivity features including custom MIPI-DSI displays, audio interfaces, +and AIROC™ Wi-Fi and Bluetooth® combo-based connectivity modules. + +The PSOC™ Edge E84 MCUs are based on high-performance Arm® Cortex®-M55 including Helium DSP support, +an Ethos™-U55 NPU, and a low-power Arm® Cortex®-M33 paired with Infineon's ultra-low power NNLite +hardware accelerator. They integrate 2.5D graphics accelerators and display interfaces, while +featuring always-on acoustic activity and wake-word detection, efficient HMI operations, and +extended battery life. + +The evaluation kit carries a PSOC™ Edge E84 MCU on a SODIMM-based detachable SOM board connected to +the baseboard. The MCU SOM also has 128 MB of QSP| Flash, 1GB of Octal Flash, 128MB of Octal RAM, +PSOC™ 4000T as CAPSENSE™ co-processor, and onboard AIROC™ Wi-Fi and Bluetooth® combo. + +Hardware +******** +For more information about the PSOC™ Edge E84 MCUs and the PSOC™ Edge E84 Evaluation Kit: + +- `PSOC™ Edge Arm® Cortex® Multicore SoC Website`_ +- `PSOC™ Edge E84 Evaluation Kit Website`_ + +Kit Features: +============= + +- Cortex®-M55 CPU with Helium™ DSP +- Advanced ML with Arm Ethos™-U55 NPU +- Low-Power Cortex®-M33 +- NNLite ultra-low power NPU +- Analog and Digital Microphones +- State-of-the-Art Secured Enclave +- Integrated Programmer/Debugger + +Kit Contents: +============= + +- PSOC™ Edge E84 base board +- PSOC™ Edge E84 SOM module +- 4.3in capacitive touch display and USB camera module +- USB Type C to Type-C cable +- Two proximity sensor wires +- Four stand-offs for Raspberry Pi compatible display +- Quick start guide + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +Please refer to `kit_pse84_eval User Manual Website`_ for more details. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The KIT-PSE84-EVAL includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, +flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and +require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Please refer to the `ModusToolbox™ software installation guide`_ to install the +Infineon OpenOCD and Edge Protect Security Suite (edgeprotecttools). + +Flashing +======== +Applications for the ``kit_pse84_eval/pse846gps2dbzc4a/m33`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Applications for the ``kit_pse84_eval/pse846gps2dbzc4a/m55`` +board target need to be built using sysbuild to include the required application for the other core. + +Enter the following command to compile ``hello_world`` for the FLPR core: + +.. code-block:: console + + west build -p -b kit_pse84_eval/pse846gps2dbzc4a/m55 --sysbuild + +Debugging +========= +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool +commands. There are multiple ways of doing this. The example below uses a permanent CMake argument +to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and +perform other standard GDB debugging on the PSOC E84 CM33 core. + +References +********** + +- `PSOC™ Edge Arm® Cortex® Multicore SoC Website`_ + +.. _PSOC™ Edge Arm® Cortex® Multicore SoC Website: + https://www.infineon.com/products/microcontroller/32-bit-psoc-arm-cortex/32-bit-psoc-edge-arm/psoc-edge-e84#Overview + +.. _PSOC™ Edge E84 Evaluation Kit Website: + https://www.infineon.com/evaluation-board/KIT-PSE84-EVAL + +.. _kit_pse84_eval User Manual Website: + https://www.infineon.com/assets/row/public/documents/30/44/infineon-kit-pse84-eval-qsg-usermanual-en.pdf + +.. _ModusToolbox™: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxsetup + +.. _ModusToolbox™ software installation guide: + https://www.Infineon.com/ModusToolboxInstallguide + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp b/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp new file mode 100644 index 0000000000000..4262d40983fa0 Binary files /dev/null and b/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp differ diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi new file mode 100644 index 0000000000000..c20aad634a6a0 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart2 pins */ +&p6_7_scb2_uart_tx{ + drive-push-pull; +}; + +&p6_5_scb2_uart_rx { + input-enable; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi new file mode 100644 index 0000000000000..e672305d810d3 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "kit_pse84_eval_common-pinctrl.dtsi" + +/ { + aliases { + sw0 = &user_bt; + watchdog0 = &watchdog0; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led_0 { + label = "LED_0"; + gpios = <&gpio_prt16 7 GPIO_ACTIVE_HIGH>; + }; + + led_green: led_1 { + label = "LED_1"; + gpios = <&gpio_prt16 6 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led_2 { + label = "LED_2"; + gpios = <&gpio_prt16 5 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt: button_0 { + label = "SW_1"; + gpios = <&gpio_prt8 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +uart2: &scb2 { + compatible = "infineon,cat1-uart-pdl"; + status = "okay"; + current-speed = <115200>; + + clocks = <&peri0_group1_16bit_0>; + + pinctrl-0 = <&p6_7_scb2_uart_tx &p6_5_scb2_uart_rx>; + pinctrl-names = "default"; +}; + +&peri0_group1_16bit_0 { + status = "okay"; + resource-type = ; + resource-instance = <2>; + clock-div = <1>; +}; + +&gpio_prt0 { + status = "okay"; +}; + +&gpio_prt16 { + status = "okay"; +}; + +&gpio_prt2 { + status = "okay"; +}; + +&gpio_prt8 { + status = "okay"; +}; + +&gpio_prt13 { + status = "okay"; +}; + +&gpio_prt14 { + status = "okay"; +}; + +&gpio_prt16 { + status = "okay"; +}; + +&clk_iho { + status = "okay"; + clock-frequency = <50000000>; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&path_mux4 { + status = "okay"; +}; + +&path_mux5 { + status = "okay"; +}; + +&clk_hf0 { + clocks = <&path_mux0>; + status = "okay"; +}; + +&clk_hf1 { + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf2 { + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf3 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf4 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf5 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf6 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf7 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf8 { + clocks = <&path_mux3>; + status = "okay"; +}; + +&clk_hf9 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf10 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&clk_hf11 { + clocks = <&path_mux0>; + status = "okay"; +}; + +&clk_hf12 { + clocks = <&path_mux1>; + status = "okay"; +}; + +&clk_hf13 { + clock-div = ; + clocks = <&path_mux2>; + status = "okay"; +}; + +&dpll_hp { + status = "okay"; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts new file mode 100644 index 0000000000000..c3f66a4b1522a --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +#include "kit_pse84_eval_common.dtsi" +#include "kit_pse84_eval_memory_map.dtsi" + +/ { + model = "kit_pse84_eval"; + compatible = "kit_pse84_eval"; + + aliases { + led0 = &led_red; + led1 = &led_green; + led2 = &led_blue; + }; + + chosen { + zephyr,flash = &m33s_xip; + zephyr,sram = &m33s_data; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml new file mode 100644 index 0000000000000..4ed08e4335b0f --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_pse84_eval/pse846gps2dbzc4a/m33 +name: PSOC Edge84 Evaluation Kit (M33_S) +type: mcu +arch: arm +sysbuild: true +toolchain: + - zephyr +supported: + - clock_control + - gpio + - pin_ctrl + - uart diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig new file mode 100644 index 0000000000000..cf7084e84d454 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Enable FPU +CONFIG_FPU=y +CONFIG_FPU_SHARING=y + +# General configuration +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable Clock Control driver +CONFIG_CLOCK_CONTROL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable assert +CONFIG_ASSERT=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts new file mode 100644 index 0000000000000..506c0a8e51a01 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +#include "kit_pse84_eval_common.dtsi" +#include "kit_pse84_eval_memory_map.dtsi" + +/ { + model = "kit_pse84_eval"; + compatible = "kit_pse84_eval"; + + aliases { + led0 = &led_red; + led1 = &led_green; + led2 = &led_blue; + }; + + chosen { + /* m55_xip is used in the pse84_boot.c file for m55 core startup + * If a different region is assigned here, it also needs to be updated at: + * soc/infineon/edge/pse84/security_config/pse84_boot.c + */ + zephyr,flash = &m55_xip; + zephyr,sram = &m55_data; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml new file mode 100644 index 0000000000000..af184f3bfb135 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_pse84_eval/pse846gps2dbzc4a/m55 +name: PSOC Edge84 Evaluation Kit (M55) +type: mcu +arch: arm +sysbuild: true +toolchain: + - zephyr +supported: + - clock_control + - gpio + - pin_ctrl + - uart diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig new file mode 100644 index 0000000000000..b8b94101f590b --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Enable FPU +CONFIG_FPU=y +CONFIG_FPU_SHARING=y + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable Clock Control driver +CONFIG_CLOCK_CONTROL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable assert +CONFIG_ASSERT=y + +CONFIG_CODE_DATA_RELOCATION=y diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi new file mode 100644 index 0000000000000..ab3a8b8a84f01 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Default SRAM(1MB) assignment + * - Lowest 4kb reserved for the Extended boot + * - 4kb shared between CM33 secure project and secure enclave + * - 212 kB allocated to CM33 Secure code + * - 132 kB allocated to CM33 Secure data + * - 404 kB allocated to CM33 Non-Secure code + * - 256 kB allocated to the CM33 Non-Secure data + * - 4 kB allocated to shared memory for each core (cm33_s, cm33 and cm55) + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + extended_boot_sram_reserved: memory@34000000 { + reg = <0x34000000 DT_SIZE_K(4)>; + }; + + m33s_shared: memory@34001000 { + reg = <0x34001000 DT_SIZE_K(4)>; + }; + + m33s_code: memory@34002000 { + reg = <0x34002000 DT_SIZE_K(212)>; + }; + + m33s_data: memory@34037000 { + reg = <0x34037000 DT_SIZE_K(132)>; + }; + + m33_code: memory@24058000 { + reg = <0x24058000 DT_SIZE_K(404)>; + }; + + m33_data: memory@240bd000 { + reg = <0x240bd000 DT_SIZE_K(256)>; + }; + + m33s_allocatable_shared: memory@340fd000 { + compatible = "zephyr,memory-region", "mmio-sram"; + zephyr,memory-region = "SHARED_MEMORY_SEC"; + reg = <0x340fd000 DT_SIZE_K(4)>; + }; + + m33_allocatable_shared: memory@240fe000 { + compatible = "zephyr,memory-region", "mmio-sram"; + zephyr,memory-region = "SHARED_MEMORY"; + reg = <0x240fe000 DT_SIZE_K(4)>; + }; + + m55_allocatable_shared: memory@240ff000 { + reg = <0x240ff000 DT_SIZE_K(4)>; + }; + + m55_data: memory@26100000 { + reg = <0x26100000 DT_SIZE_K(256)>; + }; + }; + + /* Default Flash memory(16MB) assignment + * - Lowest 1mb reserved for Storage + * - 2mb for each of the cores(cm33_s, cm33 and cm55) + + */ + flash_controller: flash_controller@40250000 { + compatible = "infineon,cat1-qspi-flash-mtb-hal"; + reg = <0x40250000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash0@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_M(16)>; + write-block-size = <256>; + erase-block-size = <65536>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + storage: storage@0 { + label = "storage"; + reg = <0 DT_SIZE_M(1)>; + }; + + m33s_header: m33s_header@60100000 { + reg = <0x60100000 0x400>; + }; + + m33s_xip: m33s_xip@70100400 { + reg = <0x70100400 DT_SIZE_M(2)>; + }; + + m33_xip: m33_xip@8300000 { + reg = <0x8300000 DT_SIZE_M(2)>; + }; + + m55_xip: m33_xip@60500000 { + reg = <0x60500000 DT_SIZE_M(2)>; + }; + }; + }; + }; +}; diff --git a/boards/infineon/kit_pse84_eval/support/openocd.cfg b/boards/infineon/kit_pse84_eval/support/openocd.cfg new file mode 100644 index 0000000000000..ada2b2e31864b --- /dev/null +++ b/boards/infineon/kit_pse84_eval/support/openocd.cfg @@ -0,0 +1,42 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +set ENABLE_CM55 1 +set ENABLE_CM33 1 + +source [find interface/kitprog3.cfg] +transport select swd + +if { [info exists _ZEPHYR_BOARD_SERIAL] } { + adapter serial $_ZEPHYR_BOARD_SERIAL +} + +if { [info exists WEST_ATTACH] } { + set ENABLE_ACQUIRE 0 +} + +source [find target/infineon/pse84xgxs2.cfg] +cat1d.cm55 configure -rtos auto -rtos-wipe-on-reset-halt 1 +cat1d.cm33 configure -rtos auto -rtos-wipe-on-reset-halt 1 +gdb_breakpoint_override hard + +if { [info exists WEST_ATTACH] } { + set _RESET 0 +} else { + set _RESET 1 +} + +if {$_RESET} { + cat1d.cm55 configure -event gdb-attach { + reset_halt cm55 + } + + cat1d.cm33 configure -event gdb-attach { + cat1d.cm33 cortex_m vector_catch reset + reset run + cat1d.cm33 arp_waitstate halted 8000 + cat1d.cm33 cortex_m vector_catch none + } +} diff --git a/boards/infineon/kit_pse84_eval/support/qspi_config.cfg b/boards/infineon/kit_pse84_eval/support/qspi_config.cfg new file mode 100644 index 0000000000000..4b5f461dc6ba0 --- /dev/null +++ b/boards/infineon/kit_pse84_eval/support/qspi_config.cfg @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +set SMIF_BANKS { + 1 {addr 0x60000000 size 0x1000000 psize 0x0000100 esize 0x0010000} +} diff --git a/boards/infineon/kit_pse84_eval/sysbuild.cmake b/boards/infineon/kit_pse84_eval/sysbuild.cmake new file mode 100644 index 0000000000000..01bde13daa33d --- /dev/null +++ b/boards/infineon/kit_pse84_eval/sysbuild.cmake @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if(SB_CONFIG_BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55) + ExternalZephyrProject_Add( + APPLICATION enable_cm55 + SOURCE_DIR ${ZEPHYR_BASE}/samples/basic/minimal + BOARD kit_pse84_eval/pse846gps2dbzc4a/m33 + ) + + set_config_bool(enable_cm55 CONFIG_SOC_PSE84_M55_ENABLE 1) +endif() diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 659c058ef61a0..c5e9c9e5bd09d 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -27,9 +27,9 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK clock_control_ifx_cat1_fixed_clock.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK clock_control_ifx_cat1_fixed_factor_clock.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK clock_control_ifx_cat1_peri_clock.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_CLOCK clock_control_ifx_fixed_clock.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK clock_control_ifx_fixed_factor_clock.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_PERI_CLOCK clock_control_ifx_peri_clock.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_pmc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_sckc.c) diff --git a/drivers/clock_control/Kconfig.ifx_cat1 b/drivers/clock_control/Kconfig.ifx_cat1 index 522c3cd9136c8..36aee1657c45a 100644 --- a/drivers/clock_control/Kconfig.ifx_cat1 +++ b/drivers/clock_control/Kconfig.ifx_cat1 @@ -12,26 +12,23 @@ config CLOCK_CONTROL_INFINEON_CAT1 help This option enables the clock control driver for Infineon CAT1 family. -config CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK +config CLOCK_CONTROL_IFX_FIXED_CLOCK bool "Infineon CAT1 Fixed clock driver" default y - depends on SOC_FAMILY_INFINEON_CAT1 depends on DT_HAS_INFINEON_FIXED_CLOCK_ENABLED help This option enables the Fixed clock driver for Infineon CAT1 family. -config CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK +config CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK bool "Infineon CAT1 Fixed factor clock driver" default y - depends on SOC_FAMILY_INFINEON_CAT1 depends on DT_HAS_INFINEON_FIXED_FACTOR_CLOCK_ENABLED help This option enables the Fixed clock driver for Infineon CAT1 family. -config CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK +config CLOCK_CONTROL_IFX_PERI_CLOCK bool "Infineon CAT1 Fixed clock driver" default y - depends on SOC_FAMILY_INFINEON_CAT1 - depends on DT_HAS_INFINEON_CAT1_PERI_DIV_ENABLED + depends on DT_HAS_INFINEON_PERI_DIV_ENABLED help This option enables the Peripheral clock driver for Infineon CAT1 family. diff --git a/drivers/clock_control/clock_control_ifx_cat1_fixed_clock.c b/drivers/clock_control/clock_control_ifx_cat1_fixed_clock.c deleted file mode 100644 index 06fa65fd64914..0000000000000 --- a/drivers/clock_control/clock_control_ifx_cat1_fixed_clock.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Clock control driver for Infineon CAT1 MCU family. - */ - -#include -#include -#include - -#include -#include -#include - -#define DT_DRV_COMPAT infineon_fixed_clock - -struct fixed_rate_clock_config { - uint32_t rate; - uint32_t id; /* ifx_cat1_clock_block */ -}; - -static int fixed_rate_clk_init(const struct device *dev) -{ - const struct fixed_rate_clock_config *const config = dev->config; - - switch (config->id) { - - case IFX_CAT1_CLOCK_BLOCK_IMO: - break; - - case IFX_CAT1_CLOCK_BLOCK_FLL: - break; - - case IFX_CAT1_CLOCK_BLOCK_IHO: - Cy_SysClk_IhoEnable(); - break; - - default: - break; - } - - return 0; -} - -#define FIXED_CLK_INIT(idx) \ - static const struct fixed_rate_clock_config fixed_rate_clock_config_##idx = { \ - .rate = DT_INST_PROP(idx, clock_frequency), \ - .id = DT_INST_PROP(idx, clock_block), \ - }; \ - DEVICE_DT_INST_DEFINE(idx, fixed_rate_clk_init, NULL, NULL, \ - &fixed_rate_clock_config_##idx, PRE_KERNEL_1, \ - CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL); - -DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT) diff --git a/drivers/clock_control/clock_control_ifx_fixed_clock.c b/drivers/clock_control/clock_control_ifx_fixed_clock.c new file mode 100644 index 0000000000000..6f97a4ce3fea2 --- /dev/null +++ b/drivers/clock_control/clock_control_ifx_fixed_clock.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Clock control driver for Infineon CAT1 MCU family. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define DT_DRV_COMPAT infineon_fixed_clock + +struct fixed_rate_clock_config { + uint32_t rate; + uint32_t system_clock; /* ifx_cat1_clock_block */ +}; + +__WEAK void ifx_clock_startup_error(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while (1) { + } +} + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) +void ifx_clk_dpll_hp0_init(void) +{ +#define CY_CFG_SYSCLK_PLL_ERROR 3 + + static cy_stc_dpll_hp_config_t dpll_hp_config = { + .pDiv = 0, + .nDiv = 15, + .kDiv = 1, + .nDivFract = 0, + .freqModeSel = CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL, + .ivrTrim = 0x8U, + .clkrSel = 0x1U, + .alphaCoarse = 0xCU, + .betaCoarse = 0x5U, + .flockThresh = 0x3U, + .flockWait = 0x6U, + .flockLkThres = 0x7U, + .flockLkWait = 0x4U, + .alphaExt = 0x14U, + .betaExt = 0x14U, + .lfEn = 0x1U, + .dcEn = 0x1U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; + static cy_stc_pll_manual_config_t dpll_config = { + .hpPllCfg = &dpll_hp_config, + }; + +#if !defined(CY_PDL_TZ_ENABLED) + if (Cy_SysClk_PllIsEnabled(SRSS_DPLL_HP_0_PATH_NUM)) { + return; + } +#endif + Cy_SysClk_PllDisable(SRSS_DPLL_HP_0_PATH_NUM); + if (CY_SYSCLK_SUCCESS != + Cy_SysClk_PllManualConfigure(SRSS_DPLL_HP_0_PATH_NUM, &dpll_config)) { + ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_DPLL_HP_0_PATH_NUM, 10000u)) { + ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR); + } +} +#endif + +static int fixed_rate_clk_init(const struct device *dev) +{ + const struct fixed_rate_clock_config *const config = dev->config; + + switch (config->system_clock) { + + case IFX_IMO: + break; + + case IFX_FLL: + break; + + case IFX_IHO: + Cy_SysClk_IhoEnable(); + break; + + case IFX_PILO: + Cy_SysClk_PiloEnable(); + break; + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) + case IFX_DPLL500: + ifx_clk_dpll_hp0_init(); + SystemCoreClockUpdate(); + break; +#endif + default: + break; + } + + return 0; +} + +#define FIXED_CLK_INIT(n) \ + static const struct fixed_rate_clock_config fixed_rate_clock_config_##n = { \ + .rate = DT_INST_PROP(n, clock_frequency), \ + .system_clock = DT_INST_PROP(n, system_clock), \ + }; \ + DEVICE_DT_INST_DEFINE(n, fixed_rate_clk_init, NULL, NULL, &fixed_rate_clock_config_##n, \ + PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT) diff --git a/drivers/clock_control/clock_control_ifx_cat1_fixed_factor_clock.c b/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c similarity index 55% rename from drivers/clock_control/clock_control_ifx_cat1_fixed_factor_clock.c rename to drivers/clock_control/clock_control_ifx_fixed_factor_clock.c index afc1fec8941ad..a939a7c6cc1c1 100644 --- a/drivers/clock_control/clock_control_ifx_cat1_fixed_factor_clock.c +++ b/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,11 @@ #include #include +#include #include -#include +#include +#include + #include #define DT_DRV_COMPAT infineon_fixed_factor_clock @@ -24,21 +27,33 @@ struct fixed_factor_clock_config { uint32_t block; /* ifx_cat1_clock_block */ uint32_t instance; uint32_t source_path; - uint32_t source_instance; + uint32_t source_block; }; static int fixed_factor_clk_init(const struct device *dev) { const struct fixed_factor_clock_config *const config = dev->config; + uint32_t source_instance; + + switch (config->source_block) { + + case IFX_DPLL250_1: + source_instance = 1; + break; + + default: + source_instance = 0; + break; + } switch (config->block) { - case IFX_CAT1_CLOCK_BLOCK_PATHMUX: + case IFX_PATHMUX: Cy_SysClk_ClkPathSetSource(config->instance, config->source_path); break; - case IFX_CAT1_CLOCK_BLOCK_HF: - Cy_SysClk_ClkHfSetSource(config->instance, config->source_instance); + case IFX_HF: + Cy_SysClk_ClkHfSetSource(config->instance, source_instance); Cy_SysClk_ClkHfSetDivider(config->instance, config->divider); Cy_SysClk_ClkHfEnable(config->instance); break; @@ -50,16 +65,16 @@ static int fixed_factor_clk_init(const struct device *dev) return 0; } -#define FIXED_CLK_INIT(idx) \ - static const struct fixed_factor_clock_config fixed_factor_clock_config_##idx = { \ - .divider = DT_INST_PROP_OR(idx, clock_divider, 1u), \ - .block = DT_INST_PROP(idx, clock_block), \ - .instance = DT_INST_PROP(idx, clock_instance), \ - .source_path = DT_INST_PROP_OR(idx, source_path, 1u), \ - .source_instance = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_instance), \ +#define FIXED_CLK_INIT(n) \ + static const struct fixed_factor_clock_config fixed_factor_clock_config_##n = { \ + .divider = DT_INST_PROP_OR(n, clock_div, 1u), \ + .block = DT_INST_PROP(n, system_clock), \ + .instance = DT_INST_PROP(n, instance), \ + .source_path = DT_INST_PROP_OR(n, source_path, 1u), \ + .source_block = DT_INST_PROP_BY_PHANDLE(n, clocks, system_clock), \ }; \ - DEVICE_DT_INST_DEFINE(idx, fixed_factor_clk_init, NULL, NULL, \ - &fixed_factor_clock_config_##idx, PRE_KERNEL_1, \ + DEVICE_DT_INST_DEFINE(n, fixed_factor_clk_init, NULL, NULL, \ + &fixed_factor_clock_config_##n, PRE_KERNEL_1, \ CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL); DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT) diff --git a/drivers/clock_control/clock_control_ifx_cat1_peri_clock.c b/drivers/clock_control/clock_control_ifx_peri_clock.c similarity index 54% rename from drivers/clock_control/clock_control_ifx_cat1_peri_clock.c rename to drivers/clock_control/clock_control_ifx_peri_clock.c index 4b7b904f73c92..bbd1b437483e8 100644 --- a/drivers/clock_control/clock_control_ifx_cat1_peri_clock.c +++ b/drivers/clock_control/clock_control_ifx_peri_clock.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,12 +9,16 @@ * @brief Peripheral Clock control driver for Infineon CAT1 MCU family. */ -#define DT_DRV_COMPAT infineon_cat1_peri_div +#define DT_DRV_COMPAT infineon_peri_div -#include #include #include #include + +#include +#include +#include + #include #include @@ -52,6 +56,14 @@ en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num) } else { clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num - 1); } +#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) + if (block_num == 0) { + clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK); + } else if (block_num == 1) { + clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB1_PCLK_CLOCK); + } else { + clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num - 1); + } #else clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num); #endif @@ -62,27 +74,41 @@ static int ifx_cat1_peri_clock_init(const struct device *dev) { struct ifx_cat1_peri_clock_data *const data = dev->data; - en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num); + if (data->hw_resource.type == IFX_RSC_SCB) { + en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num); - ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1); - ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock); - ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock); + ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1); + ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock); + ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock); + } else { + return -EINVAL; + } return 0; } +#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) +#define PERI_CLOCK_INIT(n) \ + .clock = { \ + .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST(DT_INST_PROP_BY_IDX(n, peri_group, 0), \ + DT_INST_PROP_BY_IDX(n, peri_group, 1), \ + DT_INST_PROP(n, div_type)), \ + .channel = DT_INST_PROP(n, channel), \ + }, +#else +#define PERI_CLOCK_INIT(n) \ + .clock = { \ + .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST(DT_INST_PROP_BY_IDX(n, peri_group, 1), \ + DT_INST_PROP(n, div_type)), \ + .channel = DT_INST_PROP(n, channel), \ + }, +#endif + #define INFINEON_CAT1_PERI_CLOCK_INIT(n) \ static struct ifx_cat1_peri_clock_data ifx_cat1_peri_clock##n##_data = { \ - .clock = \ - { \ - .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \ - DT_INST_PROP_BY_IDX(n, clk_dst, 1), \ - DT_INST_PROP(n, div_type)), \ - .channel = DT_INST_PROP(n, div_num), \ - }, \ - .divider = DT_INST_PROP(n, div_value), \ - .hw_resource = {.type = IFX_CAT1_RSC_SCB, \ - .block_num = DT_INST_PROP(n, scb_block)}, \ + PERI_CLOCK_INIT(n).divider = DT_INST_PROP(n, clock_div), \ + .hw_resource = {.type = DT_INST_PROP(n, resource_type), \ + .block_num = DT_INST_PROP(n, resource_instance)}, \ }; \ \ DEVICE_DT_INST_DEFINE(n, &ifx_cat1_peri_clock_init, NULL, &ifx_cat1_peri_clock##n##_data, \ diff --git a/drivers/gpio/gpio_ifx_cat1.c b/drivers/gpio/gpio_ifx_cat1.c index 29a3079ab4059..5cc8981fcefcb 100644 --- a/drivers/gpio/gpio_ifx_cat1.c +++ b/drivers/gpio/gpio_ifx_cat1.c @@ -19,6 +19,7 @@ #include #include +#include #include #include diff --git a/drivers/pinctrl/pinctrl_ifx_cat1.c b/drivers/pinctrl/pinctrl_ifx_cat1.c index 87370c14e67df..fe80dc5af37e0 100644 --- a/drivers/pinctrl/pinctrl_ifx_cat1.c +++ b/drivers/pinctrl/pinctrl_ifx_cat1.c @@ -10,9 +10,11 @@ */ #include + +#include #include -#define GPIO_PORT_OR_NULL(node_id) \ +#define GPIO_PORT_OR_NULL(node_id) \ COND_CODE_1(DT_NODE_EXISTS(node_id), ((GPIO_PRT_Type *)DT_REG_ADDR(node_id)), (NULL)) /* @brief Array containing pointers to each GPIO port. @@ -40,40 +42,40 @@ static GPIO_PRT_Type *const gpio_ports[] = { static uint32_t soc_gpio_get_drv_mode(uint32_t flags) { uint32_t drv_mode = CY_GPIO_DM_ANALOG; - uint32_t _flags; + uint32_t flags_masked; - _flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS); + flags_masked = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS); - if (_flags & SOC_GPIO_OPENDRAIN) { + if (flags_masked & SOC_GPIO_OPENDRAIN) { /* drive_open_drain */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW : CY_GPIO_DM_OD_DRIVESLOW_IN_OFF; - } else if (_flags & SOC_GPIO_OPENSOURCE) { + } else if (flags_masked & SOC_GPIO_OPENSOURCE) { /* drive_open_source */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH : CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF; - } else if (_flags & SOC_GPIO_PUSHPULL) { + } else if (flags_masked & SOC_GPIO_PUSHPULL) { /* drive_push_pull */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG : CY_GPIO_DM_STRONG_IN_OFF; - } else if ((_flags & SOC_GPIO_PULLUP) && (_flags & SOC_GPIO_PULLDOWN)) { + } else if ((flags_masked & SOC_GPIO_PULLUP) && (flags_masked & SOC_GPIO_PULLDOWN)) { /* bias_pull_up and bias_pull_down */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN : CY_GPIO_DM_PULLUP_DOWN_IN_OFF; - } else if (_flags & SOC_GPIO_PULLUP) { + } else if (flags_masked & SOC_GPIO_PULLUP) { /* bias_pull_up */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP : CY_GPIO_DM_PULLUP_IN_OFF; - } else if (_flags & SOC_GPIO_PULLDOWN) { + } else if (flags_masked & SOC_GPIO_PULLDOWN) { /* bias_pull_down */ - drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN + drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN : CY_GPIO_DM_PULLDOWN_IN_OFF; - } else if ((_flags & SOC_GPIO_HIGHZ) | (_flags & SOC_GPIO_INPUTENABLE)) { + } else if ((flags_masked & SOC_GPIO_HIGHZ) | (flags_masked & SOC_GPIO_INPUTENABLE)) { /* bias_pull_down */ drv_mode = CY_GPIO_DM_HIGHZ; } else { @@ -83,6 +85,39 @@ static uint32_t soc_gpio_get_drv_mode(uint32_t flags) return drv_mode; } +#if defined(CONFIG_SOC_SERIES_PSE84) +static uint32_t soc_gpio_get_drv_strength(uint32_t flags) +{ + uint32_t drv_strength_idx = 0; + uint32_t drv_strength = CY_GPIO_DRIVE_1_8; + uint32_t flags_masked; + + flags_masked = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS); + drv_strength_idx = (flags_masked & SOC_GPIO_DRIVESTRENGTH) >> SOC_GPIO_DRIVESTRENGTH_POS; + + switch (drv_strength_idx) { + case 0: + drv_strength = CY_GPIO_DRIVE_FULL; + break; + case 1: + drv_strength = CY_GPIO_DRIVE_1_2; + break; + case 2: + drv_strength = CY_GPIO_DRIVE_1_4; + break; + case 3: + drv_strength = CY_GPIO_DRIVE_1_8; + break; + + default: + drv_strength = CY_GPIO_DRIVE_1_8; + break; + } + + return drv_strength; +} +#endif + int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { ARG_UNUSED(reg); @@ -94,7 +129,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp uint32_t pin_num = CAT1_PINMUX_GET_PIN_NUM(pins[i].pinmux); /* Initialize pin */ -#if defined(COMPONENT_SECURE_DEVICE) || defined(CY_PDL_TZ_ENABLED) +#if defined(CY_PDL_TZ_ENABLED) Cy_GPIO_Pin_SecFastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom); #else Cy_GPIO_Pin_FastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom); @@ -109,9 +144,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp Cy_GPIO_Write(gpio_ports[port_num], pin_num, 0); break; default: - /* do nothing */ + /* Do nothing */ break; } + +#if defined(CONFIG_SOC_SERIES_PSE84) + Cy_GPIO_SetDriveSel(gpio_ports[port_num], pin_num, + soc_gpio_get_drv_strength(pins[i].pincfg)); +#endif } return 0; diff --git a/drivers/serial/uart_ifx_cat1_pdl.c b/drivers/serial/uart_ifx_cat1_pdl.c index 369e3c54b7f8e..677ba2282c12e 100644 --- a/drivers/serial/uart_ifx_cat1_pdl.c +++ b/drivers/serial/uart_ifx_cat1_pdl.c @@ -18,12 +18,14 @@ #include #include +#include #include #include #include #include #include +#include #include LOG_MODULE_REGISTER(uart_ifx_cat1, CONFIG_UART_LOG_LEVEL); @@ -37,7 +39,7 @@ struct ifx_cat1_uart_data { struct uart_config cfg; struct ifx_cat1_resource_inst hw_resource; struct ifx_cat1_clock clock; -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) uint8_t clock_peri_group; #endif @@ -133,10 +135,43 @@ static uint32_t convert_uart_data_bits_z_to_cy(const enum uart_config_data_bits return cy_data_bits; } +#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) +#define IFX_CAT1_INSTANCE_GROUP(instance, group) (((instance) << 4) | (group)) +#endif + static uint8_t ifx_cat1_get_hfclk_for_peri_group(uint8_t peri_group) { +#if defined(CONFIG_SOC_SERIES_PSE84) + switch (peri_group) { + case IFX_CAT1_INSTANCE_GROUP(0, 0): + case IFX_CAT1_INSTANCE_GROUP(1, 4): + return 0; + case IFX_CAT1_INSTANCE_GROUP(0, 7): + case IFX_CAT1_INSTANCE_GROUP(1, 0): + return 1; + case IFX_CAT1_INSTANCE_GROUP(0, 3): + case IFX_CAT1_INSTANCE_GROUP(1, 2): + return 5; + case IFX_CAT1_INSTANCE_GROUP(0, 4): + case IFX_CAT1_INSTANCE_GROUP(1, 3): + return 6; + case IFX_CAT1_INSTANCE_GROUP(1, 1): + return 7; + case IFX_CAT1_INSTANCE_GROUP(0, 2): + return 9; + case IFX_CAT1_INSTANCE_GROUP(0, 1): + case IFX_CAT1_INSTANCE_GROUP(0, 5): + return 10; + case IFX_CAT1_INSTANCE_GROUP(0, 8): + return 11; + case IFX_CAT1_INSTANCE_GROUP(0, 6): + case IFX_CAT1_INSTANCE_GROUP(0, 9): + return 13; + default: + break; + } +#elif defined(CONFIG_SOC_SERIES_PSC3) switch (peri_group) { - /* Peripheral groups are device specific. */ case 0: case 2: return 0; @@ -152,7 +187,8 @@ static uint8_t ifx_cat1_get_hfclk_for_peri_group(uint8_t peri_group) default: break; } - return -1; +#endif + return -EINVAL; } cy_rslt_t ifx_cat1_uart_set_baud(const struct device *dev, uint32_t baudrate) @@ -175,7 +211,8 @@ cy_rslt_t ifx_cat1_uart_set_baud(const struct device *dev, uint32_t baudrate) #if defined(COMPONENT_CAT1A) peri_frequency = Cy_SysClk_ClkPeriGetFrequency(); -#elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) +#elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || \ + defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) uint8_t hfclk = ifx_cat1_get_hfclk_for_peri_group(data->clock_peri_group); peri_frequency = Cy_SysClk_ClkHfGetFrequency(hfclk); @@ -571,11 +608,17 @@ static void ifx_cat1_uart_irq_handler(const struct device *dev) /* Default Counter configuration structure */ static const cy_stc_scb_uart_config_t _uart_default_config = { .uartMode = CY_SCB_UART_STANDARD, +#if defined(CONFIG_SOC_SERIES_PSE84) + .enableMultiProcessorMode = false, +#else .enableMutliProcessorMode = false, +#endif .smartCardRetryOnNack = false, .irdaInvertRx = false, .irdaEnableLowPowerReceiver = false, +#if ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4)) .halfDuplexMode = false, +#endif .oversample = 8, .enableMsbFirst = false, .dataWidth = 8UL, @@ -731,7 +774,7 @@ static int ifx_cat1_uart_init(const struct device *dev) int ret; /* Dedicate SCB HW resource */ - data->hw_resource.type = IFX_CAT1_RSC_SCB; + data->hw_resource.type = IFX_RSC_SCB; data->hw_resource.block_num = ifx_cat1_uart_get_hw_block_num(config->reg_addr); /* Configure dt provided device signals when available */ @@ -802,8 +845,8 @@ static DEVICE_API(uart, ifx_cat1_uart_driver_api) = { #define IRQ_INFO(n) .irq_num = DT_INST_IRQN(n), .irq_priority = DT_INST_IRQ(n, priority) #endif -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) -#define PERI_INFO(n) .clock_peri_group = DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), clk_dst, 1), +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) +#define PERI_INFO(n) .clock_peri_group = DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 1), #else #define PERI_INFO(n) #endif @@ -825,15 +868,28 @@ static DEVICE_API(uart, ifx_cat1_uart_driver_api) = { #define CALL_UART_IRQ_CONFIG(n) #endif +#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) #define UART_PERI_CLOCK_INIT(n) \ .clock = \ { \ .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \ - DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), clk_dst, 1), \ + DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 0), \ + DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 1), \ DT_INST_PROP_BY_PHANDLE(n, clocks, div_type)), \ - .channel = DT_INST_PROP_BY_PHANDLE(n, clocks, div_num), \ + .channel = DT_INST_PROP_BY_PHANDLE(n, clocks, channel), \ }, \ PERI_INFO(n) +#else +#define UART_PERI_CLOCK_INIT(n) \ + .clock = \ + { \ + .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \ + DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 1), \ + DT_INST_PROP_BY_PHANDLE(n, clocks, div_type)), \ + .channel = DT_INST_PROP_BY_PHANDLE(n, clocks, channel), \ + }, \ + PERI_INFO(n) +#endif #define INFINEON_CAT1_UART_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ diff --git a/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi b/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi index 89b02d55f17c2..10338b5be76cc 100644 --- a/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi +++ b/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi @@ -10,7 +10,8 @@ #define DIV_16_5_BIT 02 #define DIV_24_5_BIT 03 -#include +#include +#include / { srss_power: srss_power { @@ -26,8 +27,7 @@ #clock-cells = <0>; compatible = "infineon,fixed-clock"; clock-frequency = <48000000>; - clock-block = ; - clock-instance = <0>; + system-clock = ; status = "okay"; }; @@ -36,8 +36,7 @@ #clock-cells = <0>; compatible = "infineon,fixed-clock"; clock-frequency = <8000000>; - clock-block = ; - clock-instance = <0>; + system-clock = ; status = "okay"; }; @@ -46,8 +45,7 @@ #clock-cells = <0>; compatible = "infineon,fixed-clock"; clock-frequency = <96000000>; - clock-block = ; - clock-instance = <0>; + system-clock = ; status = "okay"; }; @@ -56,8 +54,8 @@ #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; clocks = <&clk_iho>; - clock-block = ; - clock-instance = <0>; + system-clock = ; + instance = <0>; source-path = ; status = "disabled"; }; @@ -67,8 +65,8 @@ #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; clocks = <&clk_iho>; - clock-block = ; - clock-instance = <1>; + system-clock = ; + instance = <1>; source-path = ; status = "disabled"; }; @@ -78,8 +76,8 @@ #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; clocks = <&clk_iho>; - clock-block = ; - clock-instance = <2>; + system-clock = ; + instance = <2>; source-path = ; status = "disabled"; }; @@ -89,8 +87,8 @@ #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; clocks = <&clk_iho>; - clock-block = ; - clock-instance = <3>; + system-clock = ; + instance = <3>; source-path = ; status = "disabled"; }; @@ -99,10 +97,10 @@ clk_hf0: clk_hf0 { #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; - clock-divider = ; + clock-div = ; clocks = <&path_mux1>; - clock-block = ; - clock-instance = <0>; + system-clock = ; + instance = <0>; status = "disabled"; }; @@ -110,10 +108,10 @@ clk_hf1: clk_hf1 { #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; - clock-divider = ; + clock-div = ; clocks = <&path_mux1>; - clock-block = ; - clock-instance = <1>; + system-clock = ; + instance = <1>; status = "disabled"; }; @@ -121,10 +119,10 @@ clk_hf2: clk_hf2 { #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; - clock-divider = ; + clock-div = ; clocks = <&path_mux0>; - clock-block = ; - clock-instance = <2>; + system-clock = ; + instance = <2>; status = "disabled"; }; @@ -132,10 +130,10 @@ clk_hf3: clk_hf3 { #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; - clock-divider = ; + clock-div = ; clocks = <&path_mux2>; - clock-block = ; - clock-instance = <3>; + system-clock = ; + instance = <3>; status = "disabled"; }; @@ -143,10 +141,10 @@ clk_hf4: clk_hf4 { #clock-cells = <0>; compatible = "infineon,fixed-factor-clock"; - clock-divider = ; + clock-div = ; clocks = <&path_mux0>; - clock-block = ; - clock-instance = <4>; + system-clock = ; + instance = <4>; status = "disabled"; }; }; @@ -156,11 +154,11 @@ /* 24.5-bit */ peri0_group0_24_5bit_0: peri0_group0_24_5bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 00]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 00]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; @@ -168,11 +166,11 @@ /* 8-bit */ peri0_group1_8bit_0: peri0_group1_8bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 01]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; @@ -180,74 +178,74 @@ /* 8-bit */ peri0_group4_8bit_0: peri0_group4_8bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; peri0_group4_8bit_1: peri0_group4_8bit_1 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <1>; - div-value = <1>; + channel = <1>; + clock-div = <1>; status = "disabled"; }; /* 16-bit */ peri0_group4_16bit_0: peri0_group4_16bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; /* 16.5-bit */ peri0_group4_16_5bit_0: peri0_group4_16_5bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; peri0_group4_16_5bit_1: peri0_group4_16_5bit_1 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <1>; - div-value = <1>; + channel = <1>; + clock-div = <1>; status = "disabled"; }; peri0_group4_16_5bit_2: peri0_group4_16_5bit_2 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <2>; - div-value = <1>; + channel = <2>; + clock-div = <1>; status = "disabled"; }; /* 24.5-bit */ peri0_group4_24_5bit_0: peri0_group4_24_5bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 04]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 04]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; @@ -255,142 +253,142 @@ /* 8-bit */ peri0_group5_8bit_0: peri0_group5_8bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_1: peri0_group5_8bit_1 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <1>; - div-value = <1>; + channel = <1>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_2: peri0_group5_8bit_2 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <2>; - div-value = <1>; + channel = <2>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_3: peri0_group5_8bit_3 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <3>; - div-value = <1>; + channel = <3>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_4: peri0_group5_8bit_4 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <4>; - div-value = <1>; + channel = <4>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_5: peri0_group5_8bit_5 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <5>; - div-value = <1>; + channel = <5>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_6: peri0_group5_8bit_6 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <6>; - div-value = <1>; + channel = <6>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_7: peri0_group5_8bit_7 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <7>; - div-value = <1>; + channel = <7>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_8: peri0_group5_8bit_8 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <8>; - div-value = <1>; + channel = <8>; + clock-div = <1>; status = "disabled"; }; peri0_group5_8bit_9: peri0_group5_8bit_9 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <9>; - div-value = <1>; + channel = <9>; + clock-div = <1>; status = "disabled"; }; /* 16-bit */ peri0_group5_16bit_0: peri0_group5_16bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; peri0_group5_16bit_1: peri0_group5_16bit_1 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <1>; - div-value = <1>; + channel = <1>; + clock-div = <1>; status = "disabled"; }; peri0_group5_16bit_2: peri0_group5_16bit_2 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <2>; - div-value = <1>; + channel = <2>; + clock-div = <1>; status = "disabled"; }; peri0_group5_16bit_3: peri0_group5_16bit_3 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 05]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 05]; /* inst#, group# */ div-type = ; - div-num = <3>; - div-value = <1>; + channel = <3>; + clock-div = <1>; status = "disabled"; }; @@ -398,11 +396,11 @@ /* 16.5-bit */ peri0_group6_16_5bit_0: peri0_group6_16_5bit_0 { #clock-cells = <0>; - compatible = "infineon,cat1-peri-div"; - clk-dst = [00 06]; /* inst#, group# */ + compatible = "infineon,peri-div"; + peri-group = [00 06]; /* inst#, group# */ div-type = ; - div-num = <0>; - div-value = <1>; + channel = <0>; + clock-div = <1>; status = "disabled"; }; }; diff --git a/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gms2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gms4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gos2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse812gos4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gms4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse813gos4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gms2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gms4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gos2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse822gos4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gms4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse823gos4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gms2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gms4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gos2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse832gos4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gms4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse833gos4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b.dtsi new file mode 100644 index 0000000000000..a5e5ee75fe1c9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b_s.dtsi new file mode 100644 index 0000000000000..fa66bba146797 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos2dfmc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b.dtsi new file mode 100644 index 0000000000000..a5e5ee75fe1c9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b_s.dtsi new file mode 100644 index 0000000000000..fa66bba146797 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos4dfmc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gos4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a.dtsi new file mode 100644 index 0000000000000..a5e5ee75fe1c9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a_s.dtsi new file mode 100644 index 0000000000000..fa66bba146797 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b.dtsi new file mode 100644 index 0000000000000..a5e5ee75fe1c9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b_s.dtsi new file mode 100644 index 0000000000000..fa66bba146797 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfmc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps2dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b.dtsi new file mode 100644 index 0000000000000..a5e5ee75fe1c9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b_s.dtsi new file mode 100644 index 0000000000000..fa66bba146797 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps4dfmc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.ewlb-235_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b.dtsi b/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b.dtsi new file mode 100644 index 0000000000000..4174f68edbd9f --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b_s.dtsi new file mode 100644 index 0000000000000..cabfe972ef6d5 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse845gps4dfnc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.wlb-154_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gos4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3a_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps2dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4a_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b.dtsi new file mode 100644 index 0000000000000..364b43c30a02c --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b_s.dtsi new file mode 100644 index 0000000000000..1d4dbfb66c102 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzc4b_s.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b.dtsi new file mode 100644 index 0000000000000..a7b4f86b29eb9 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b_s.dtsi b/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b_s.dtsi new file mode 100644 index 0000000000000..5dfe547800926 --- /dev/null +++ b/dts/arm/infineon/edge/mpns/pse846gps4dbzq3b_s.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../pse84/pse84.bga-220_s.dtsi" + +/ { + cpu@0 { + clock-frequency = <320000000>; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/clock_source_def.h b/dts/arm/infineon/edge/pse84/clock_source_def.h new file mode 100644 index 0000000000000..13cf1c42851c6 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/clock_source_def.h @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define CLK_SOURCE_IHO 0U +#define CLK_SOURCE_PILO 0x113U diff --git a/dts/arm/infineon/edge/pse84/pse84.bga-220.dtsi b/dts/arm/infineon/edge/pse84/pse84.bga-220.dtsi new file mode 100644 index 0000000000000..20c7dd1c10030 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.bga-220.dtsi @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84.dtsi" + +/ { + soc { + pinctrl: pinctrl@42800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_i2c_scl: p10_0_scb4_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_i2c_scl: p11_0_scb6_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_i2c_scl: p21_6_scb3_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_i2c_sda: p10_1_scb4_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_i2c_sda: p11_1_scb6_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_i2c_sda: p21_5_scb3_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_m_clk: p10_1_scb4_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_m_clk: p11_0_scb6_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_m_clk: p21_6_scb3_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_m_miso: p10_3_scb4_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_m_miso: p11_2_scb6_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_m_miso: p13_7_scb8_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_m_miso: p21_4_scb3_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_m_mosi: p10_2_scb4_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_m_mosi: p11_1_scb6_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_m_mosi: p21_5_scb3_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_m_select0: p0_0_scb3_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_m_select0: p10_4_scb4_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_m_select0: p11_3_scb6_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_m_select0: p14_7_scb8_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_m_select1: p10_5_scb4_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_m_select1: p11_4_scb6_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_m_select1: p13_6_scb7_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_m_select1: p14_6_scb8_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_m_select1: p15_4_scb9_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_m_select1: p17_7_scb11_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_m_select1: p20_0_scb1_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_s_clk: p10_1_scb4_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_s_clk: p11_0_scb6_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_s_clk: p21_6_scb3_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_s_miso: p10_3_scb4_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_s_miso: p11_2_scb6_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_s_miso: p13_7_scb8_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_s_miso: p21_4_scb3_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_s_mosi: p10_2_scb4_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_s_mosi: p11_1_scb6_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_s_mosi: p21_5_scb3_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_s_select0: p0_0_scb3_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_s_select0: p10_4_scb4_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_s_select0: p11_3_scb6_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_s_select0: p14_7_scb8_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_s_select1: p10_5_scb4_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_s_select1: p11_4_scb6_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_s_select1: p13_6_scb7_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_s_select1: p14_6_scb8_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_s_select1: p15_4_scb9_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_s_select1: p17_7_scb11_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_s_select1: p20_0_scb1_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_uart_cts: p10_2_scb4_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_uart_cts: p11_2_scb6_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_uart_cts: p13_7_scb8_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_uart_cts: p21_4_scb3_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_uart_rts: p10_3_scb4_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_uart_rts: p11_3_scb6_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_uart_rts: p14_7_scb8_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_uart_rx: p10_0_scb4_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_uart_rx: p11_0_scb6_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_uart_rx: p21_6_scb3_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_uart_tx: p10_1_scb4_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_uart_tx: p11_1_scb6_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_uart_tx: p21_5_scb3_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_sdhc0_card_if_pwr_en: p21_4_sdhc0_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p0_0_pwm0_0: p0_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm0_6: p8_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm0_1: p10_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm0_2: p10_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm0_3: p10_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm0_4: p10_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm0_5: p11_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm0_6: p11_2_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm0_7: p11_4_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm0_0: p11_6_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm0_6: p13_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm0_7: p14_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm0_1: p14_6_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm0_4: p15_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm0_5: p15_6_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm0_7: p20_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm0_1: p20_2_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm0_2: p20_3_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm0_5: p21_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm0_6: p21_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p0_0_pwm1_0: p0_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm1_22: p8_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm1_1: p10_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm1_2: p10_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm1_3: p10_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm1_4: p10_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm1_5: p11_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm1_6: p11_2_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm1_7: p11_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm1_8: p11_6_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm1_14: p13_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm1_15: p14_1_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm1_17: p14_6_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm1_20: p15_4_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm1_21: p15_6_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm1_7: p20_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm1_8: p20_5_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm1_9: p20_6_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm1_10: p20_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm1_13: p21_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm1_14: p21_6_pwm1_14 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p0_1_pwm0_0: p0_1_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm0_5: p8_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm0_6: p8_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm0_1: p10_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm0_2: p10_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm0_3: p10_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm0_4: p10_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm0_5: p11_1_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm0_6: p11_3_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm0_7: p11_5_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm0_0: p11_7_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm0_6: p13_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm0_7: p14_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm0_1: p14_7_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm0_4: p15_5_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm0_5: p15_7_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm0_7: p17_7_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm0_7: p20_4_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm0_0: p20_5_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm0_1: p20_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm0_2: p20_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm0_5: p21_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm1_21: p8_5_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm1_22: p8_7_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm1_1: p10_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm1_2: p10_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm1_3: p10_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm1_4: p10_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm1_5: p11_1_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm1_6: p11_3_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm1_7: p11_5_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm1_8: p11_7_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm1_14: p13_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm1_15: p14_2_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm1_17: p14_7_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm1_20: p15_5_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm1_21: p15_7_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm1_23: p17_7_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm1_7: p20_0_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm1_9: p20_2_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm1_10: p20_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm1_13: p21_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.bga-220_s.dtsi b/dts/arm/infineon/edge/pse84/pse84.bga-220_s.dtsi new file mode 100644 index 0000000000000..7022a837a8bbc --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.bga-220_s.dtsi @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84_s.dtsi" + +/ { + soc { + pinctrl: pinctrl@52800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_i2c_scl: p10_0_scb4_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_i2c_scl: p11_0_scb6_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_i2c_scl: p21_6_scb3_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_i2c_sda: p10_1_scb4_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_i2c_sda: p11_1_scb6_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_i2c_sda: p21_5_scb3_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_m_clk: p10_1_scb4_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_m_clk: p11_0_scb6_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_m_clk: p21_6_scb3_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_m_miso: p10_3_scb4_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_m_miso: p11_2_scb6_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_m_miso: p13_7_scb8_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_m_miso: p21_4_scb3_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_m_mosi: p10_2_scb4_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_m_mosi: p11_1_scb6_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_m_mosi: p21_5_scb3_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_m_select0: p0_0_scb3_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_m_select0: p10_4_scb4_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_m_select0: p11_3_scb6_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_m_select0: p14_7_scb8_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_m_select1: p10_5_scb4_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_m_select1: p11_4_scb6_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_m_select1: p13_6_scb7_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_m_select1: p14_6_scb8_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_m_select1: p15_4_scb9_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_m_select1: p17_7_scb11_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_m_select1: p20_0_scb1_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_s_clk: p10_1_scb4_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_s_clk: p11_0_scb6_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_s_clk: p21_6_scb3_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_s_miso: p10_3_scb4_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_s_miso: p11_2_scb6_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_s_miso: p13_7_scb8_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_s_miso: p21_4_scb3_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_s_mosi: p10_2_scb4_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_s_mosi: p11_1_scb6_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_s_mosi: p21_5_scb3_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_s_select0: p0_0_scb3_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_s_select0: p10_4_scb4_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_s_select0: p11_3_scb6_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_s_select0: p14_7_scb8_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_s_select1: p10_5_scb4_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_s_select1: p11_4_scb6_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_s_select1: p13_6_scb7_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_s_select1: p14_6_scb8_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_s_select1: p15_4_scb9_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_s_select1: p17_7_scb11_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_s_select1: p20_0_scb1_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_uart_cts: p10_2_scb4_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_uart_cts: p11_2_scb6_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_uart_cts: p13_7_scb8_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_uart_cts: p21_4_scb3_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_uart_rts: p10_3_scb4_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_uart_rts: p11_3_scb6_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_uart_rts: p14_7_scb8_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_uart_rx: p10_0_scb4_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_uart_rx: p11_0_scb6_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_uart_rx: p21_6_scb3_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_uart_tx: p10_1_scb4_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_uart_tx: p11_1_scb6_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_uart_tx: p21_5_scb3_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_sdhc0_card_if_pwr_en: p21_4_sdhc0_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p0_0_pwm0_0: p0_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm0_6: p8_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm0_1: p10_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm0_2: p10_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm0_3: p10_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm0_4: p10_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm0_5: p11_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm0_6: p11_2_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm0_7: p11_4_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm0_0: p11_6_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm0_6: p13_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm0_7: p14_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm0_1: p14_6_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm0_4: p15_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm0_5: p15_6_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm0_7: p20_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm0_1: p20_2_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm0_2: p20_3_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm0_5: p21_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm0_6: p21_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p0_0_pwm1_0: p0_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm1_22: p8_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm1_1: p10_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm1_2: p10_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm1_3: p10_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm1_4: p10_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm1_5: p11_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm1_6: p11_2_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm1_7: p11_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm1_8: p11_6_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm1_14: p13_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm1_15: p14_1_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm1_17: p14_6_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm1_20: p15_4_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm1_21: p15_6_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm1_7: p20_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm1_8: p20_5_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm1_9: p20_6_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm1_10: p20_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm1_13: p21_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm1_14: p21_6_pwm1_14 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p0_1_pwm0_0: p0_1_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm0_5: p8_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm0_6: p8_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm0_1: p10_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm0_2: p10_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm0_3: p10_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm0_4: p10_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm0_5: p11_1_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm0_6: p11_3_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm0_7: p11_5_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm0_0: p11_7_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm0_6: p13_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm0_7: p14_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm0_1: p14_7_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm0_4: p15_5_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm0_5: p15_7_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm0_7: p17_7_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm0_7: p20_4_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm0_0: p20_5_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm0_1: p20_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm0_2: p20_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm0_5: p21_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm1_21: p8_5_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm1_22: p8_7_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm1_1: p10_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm1_2: p10_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm1_3: p10_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm1_4: p10_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm1_5: p11_1_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm1_6: p11_3_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm1_7: p11_5_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm1_8: p11_7_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm1_14: p13_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm1_15: p14_2_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm1_17: p14_7_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm1_20: p15_5_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm1_21: p15_7_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm1_23: p17_7_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm1_7: p20_0_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm1_9: p20_2_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm1_10: p20_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm1_13: p21_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.cm33.dtsi b/dts/arm/infineon/edge/pse84/pse84.cm33.dtsi new file mode 100644 index 0000000000000..bc2540af7c099 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.cm33.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + clock-frequency = <200000000>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.cm55.dtsi b/dts/arm/infineon/edge/pse84/pse84.cm55.dtsi new file mode 100644 index 0000000000000..43a27313cb5c9 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.cm55.dtsi @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <1>; + clock-frequency = <400000000>; + }; + }; +}; + +&gpio_prt0 { + interrupts = <0 4>; +}; + +&gpio_prt1 { + interrupts = <39 4>; +}; + +&gpio_prt2 { + interrupts = <1 4>; +}; + +&gpio_prt3 { + interrupts = <2 4>; +}; + +&gpio_prt4 { + interrupts = <40 4>; +}; + +&gpio_prt5 { + interrupts = <3 4>; +}; + +&gpio_prt6 { + interrupts = <4 4>; +}; + +&gpio_prt7 { + interrupts = <5 4>; +}; + +&gpio_prt8 { + interrupts = <6 4>; +}; + +&gpio_prt9 { + interrupts = <7 4>; +}; + +&gpio_prt10 { + interrupts = <8 4>; +}; + +&gpio_prt11 { + interrupts = <9 4>; +}; + +&gpio_prt12 { + interrupts = <10 4>; +}; + +&gpio_prt13 { + interrupts = <11 4>; +}; + +&gpio_prt14 { + interrupts = <12 4>; +}; + +&gpio_prt15 { + interrupts = <13 4>; +}; + +&gpio_prt16 { + interrupts = <14 4>; +}; + +&gpio_prt17 { + interrupts = <15 4>; +}; + +&gpio_prt18 { + interrupts = <16 4>; +}; + +&gpio_prt19 { + interrupts = <17 4>; +}; + +&gpio_prt20 { + interrupts = <18 4>; +}; + +&gpio_prt21 { + interrupts = <19 4>; +}; + +&adc0 { + interrupts = <36 4>; +}; + +&scb0 { + interrupts = <22 4>; +}; + +&scb2 { + interrupts = <121 4>; +}; + +&scb3 { + interrupts = <122 4>; +}; + +&scb4 { + interrupts = <123 4>; +}; + +&scb5 { + interrupts = <124 4>; +}; + +&scb6 { + interrupts = <125 4>; +}; + +&scb7 { + interrupts = <126 4>; +}; + +&scb8 { + interrupts = <127 4>; +}; + +&scb9 { + interrupts = <128 4>; +}; + +&scb10 { + interrupts = <129 4>; +}; + +&scb11 { + interrupts = <130 4>; +}; + +&scb1 { + interrupts = <120 4>; +}; + +&i3c0 { + interrupts = <153 4>; +}; + +&watchdog0 { + interrupts = <33 4>; +}; + +&mcwdt0 { + interrupts = <0 4>; +}; + +&mcwdt1 { + interrupts = <34 4>; +}; + +&tcpwm0_0 { + interrupts = <88 4>; +}; + +&tcpwm0_1 { + interrupts = <89 4>; +}; + +&tcpwm0_2 { + interrupts = <90 4>; +}; + +&tcpwm0_3 { + interrupts = <91 4>; +}; + +&tcpwm0_4 { + interrupts = <92 4>; +}; + +&tcpwm0_5 { + interrupts = <93 4>; +}; + +&tcpwm0_6 { + interrupts = <94 4>; +}; + +&tcpwm0_7 { + interrupts = <95 4>; +}; + +&tcpwm1_0 { + interrupts = <96 4>; +}; + +&tcpwm1_1 { + interrupts = <97 4>; +}; + +&tcpwm1_2 { + interrupts = <98 4>; +}; + +&tcpwm1_3 { + interrupts = <99 4>; +}; + +&tcpwm1_4 { + interrupts = <100 4>; +}; + +&tcpwm1_5 { + interrupts = <101 4>; +}; + +&tcpwm1_6 { + interrupts = <102 4>; +}; + +&tcpwm1_7 { + interrupts = <103 4>; +}; + +&tcpwm1_8 { + interrupts = <104 4>; +}; + +&tcpwm1_9 { + interrupts = <105 4>; +}; + +&tcpwm1_10 { + interrupts = <106 4>; +}; + +&tcpwm1_11 { + interrupts = <107 4>; +}; + +&tcpwm1_12 { + interrupts = <108 4>; +}; + +&tcpwm1_13 { + interrupts = <109 4>; +}; + +&tcpwm1_14 { + interrupts = <110 4>; +}; + +&tcpwm1_15 { + interrupts = <111 4>; +}; + +&tcpwm1_16 { + interrupts = <112 4>; +}; + +&tcpwm1_17 { + interrupts = <113 4>; +}; + +&tcpwm1_18 { + interrupts = <114 4>; +}; + +&tcpwm1_19 { + interrupts = <115 4>; +}; + +&tcpwm1_20 { + interrupts = <116 4>; +}; + +&tcpwm1_21 { + interrupts = <117 4>; +}; + +&tcpwm1_22 { + interrupts = <118 4>; +}; + +&tcpwm1_23 { + interrupts = <119 4>; +}; + +&dma0 { +interrupts = <60 4>, /* CH0 */ + <61 4>, /* CH1 */ + <62 4>, /* CH2 */ + <63 4>, /* CH3 */ + <64 4>, /* CH4 */ + <65 4>, /* CH5 */ + <66 4>, /* CH6 */ + <67 4>, /* CH7 */ + <68 4>, /* CH8 */ + <69 4>, /* CH9 */ + <70 4>, /* CH10 */ + <71 4>, /* CH11 */ + <72 4>, /* CH12 */ + <73 4>, /* CH13 */ + <74 4>, /* CH14 */ + <75 4>; /* CH15 */ +}; + +&dma1 { +interrupts = <158 4>, /* CH0 */ + <159 4>, /* CH1 */ + <160 4>, /* CH2 */ + <161 4>, /* CH3 */ + <162 4>, /* CH4 */ + <163 4>, /* CH5 */ + <164 4>, /* CH6 */ + <165 4>, /* CH7 */ + <166 4>, /* CH8 */ + <167 4>, /* CH9 */ + <168 4>, /* CH10 */ + <169 4>, /* CH11 */ + <170 4>, /* CH12 */ + <171 4>, /* CH13 */ + <172 4>, /* CH14 */ + <173 4>; /* CH15 */ +}; + +&sdhc0 { + interrupts = <132 4>, /* SDIO wakeup interrupt for mxsdhc */ + <131 6>; /* Consolidated interrupt for mxsdhc */ +}; + +&sdhc1 { + interrupts = <134 4>, /* SDIO wakeup interrupt for mxsdhc */ + <133 6>; /* Consolidated interrupt for mxsdhc */ +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.dtsi b/dts/arm/infineon/edge/pse84/pse84.dtsi new file mode 100644 index 0000000000000..8576f0601c2f9 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.dtsi @@ -0,0 +1,1120 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + sram0: sram0@24000000 { + compatible = "mmio-sram"; + reg = <0x24000000 0x100000>; + }; + + dtcm { + #address-cells = <1>; + #size-cells = <1>; + + dtcm_m33: dtcm_m33@48040000 { + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x48040000 DT_SIZE_K(256)>; + zephyr,memory-region = "DTCM_M33"; + }; + + dtcm_m55: dtcm_m55@20000000 { + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x20000000 DT_SIZE_K(256)>; + zephyr,memory-region = "DTCM_M55"; + }; + }; + + itcm { + #address-cells = <1>; + #size-cells = <1>; + + itcm_m33: itcm_m33@48000000 { + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x48000000 DT_SIZE_K(256)>; + zephyr,memory-region = "ITCM_M33"; + }; + + itcm_m55: itcm_m55@0 { + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x00000000 DT_SIZE_K(256)>; + zephyr,memory-region = "ITCM_M55"; + }; + }; + + rram { + #address-cells = <1>; + #size-cells = <1>; + + rram: rram@22000000 { + compatible = "soc-nv-flash"; + reg = <0x22000000 DT_SIZE_K(512)>; + }; + }; + + socmem { + #address-cells = <1>; + #size-cells = <1>; + + socmem: socmem@26000000 { + reg = <0x26000000 DT_SIZE_M(5)>; + }; + }; + + soc { + pinctrl: pinctrl@42800000 { + compatible = "infineon,cat1-pinctrl"; + reg = <0x42800000 0x20000>; + }; + + hsiom: hsiom@42800000 { + compatible = "infineon,cat1-hsiom"; + reg = <0x42800000 0x4000>; + interrupts = <41 4>, <40 4>; + status = "disabled"; + }; + + gpio_prt0: gpio@42810000 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810000 0x80>; + interrupts = <0 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt1: gpio@42810080 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810080 0x80>; + interrupts = <59 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt2: gpio@42810100 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810100 0x80>; + interrupts = <1 4>; + gpio-controller; + ngpios = <1>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt3: gpio@42810180 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810180 0x80>; + interrupts = <2 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt4: gpio@42810200 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810200 0x80>; + interrupts = <60 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt5: gpio@42810280 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810280 0x80>; + interrupts = <3 4>; + gpio-controller; + ngpios = <1>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt6: gpio@42810300 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810300 0x80>; + interrupts = <4 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt7: gpio@42810380 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810380 0x80>; + interrupts = <5 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt8: gpio@42810400 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810400 0x80>; + interrupts = <6 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt9: gpio@42810480 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810480 0x80>; + interrupts = <7 4>; + gpio-controller; + ngpios = <4>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt10: gpio@42810500 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810500 0x80>; + interrupts = <8 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt11: gpio@42810580 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810580 0x80>; + interrupts = <9 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt12: gpio@42810600 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810600 0x80>; + interrupts = <10 4>; + gpio-controller; + ngpios = <6>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt13: gpio@42810680 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810680 0x80>; + interrupts = <11 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt14: gpio@42810700 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810700 0x80>; + interrupts = <12 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt15: gpio@42810780 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810780 0x80>; + interrupts = <13 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt16: gpio@42810800 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810800 0x80>; + interrupts = <14 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt17: gpio@42810880 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810880 0x80>; + interrupts = <15 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt18: gpio@42810900 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810900 0x80>; + interrupts = <16 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt19: gpio@42810980 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810980 0x80>; + interrupts = <17 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt20: gpio@42810a00 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810a00 0x80>; + interrupts = <18 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt21: gpio@42810a80 { + compatible = "infineon,cat1-gpio"; + reg = <0x42810a80 0x80>; + interrupts = <19 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + adc0: adc@42e80000 { + compatible = "infineon,autanalog-sar-adc"; + reg = <0x42e80000 0xf20>; + interrupts = <57 4>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + ipc0: ipc@422a0000 { + compatible = "infineon,cat1-ipc"; + reg = <0x422a0000 0x1200>; + status = "disabled"; + #ipc-config-cells = <3>; + }; + + ipc1: ipc@441d0000 { + compatible = "infineon,cat1-ipc"; + reg = <0x441d0000 0x1200>; + status = "disabled"; + #ipc-config-cells = <3>; + }; + + scb0: scb@42990000 { + compatible = "infineon,cat1-scb"; + reg = <0x42990000 0xfd0>; + interrupts = <43 4>; + status = "disabled"; + }; + + scb2: scb@429a0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429a0000 0xfd0>; + interrupts = <143 4>; + status = "disabled"; + }; + + scb3: scb@429b0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429b0000 0xfd0>; + interrupts = <144 4>; + status = "disabled"; + }; + + scb4: scb@429c0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429c0000 0xfd0>; + interrupts = <145 4>; + status = "disabled"; + }; + + scb5: scb@429d0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429d0000 0xfd0>; + interrupts = <146 4>; + status = "disabled"; + }; + + scb6: scb@429e0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429e0000 0xfd0>; + interrupts = <147 4>; + status = "disabled"; + }; + + scb7: scb@429f0000 { + compatible = "infineon,cat1-scb"; + reg = <0x429f0000 0xfd0>; + interrupts = <148 4>; + status = "disabled"; + }; + + scb8: scb@42a00000 { + compatible = "infineon,cat1-scb"; + reg = <0x42a00000 0xfd0>; + interrupts = <149 4>; + status = "disabled"; + }; + + scb9: scb@42a10000 { + compatible = "infineon,cat1-scb"; + reg = <0x42a10000 0xfd0>; + interrupts = <150 4>; + status = "disabled"; + }; + + scb10: scb@42a20000 { + compatible = "infineon,cat1-scb"; + reg = <0x42a20000 0xfd0>; + interrupts = <151 4>; + status = "disabled"; + }; + + scb11: scb@42a30000 { + compatible = "infineon,cat1-scb"; + reg = <0x42a30000 0xfd0>; + interrupts = <152 4>; + status = "disabled"; + }; + + scb1: scb@42d00000 { + compatible = "infineon,cat1-scb"; + reg = <0x42d00000 0xfd0>; + interrupts = <142 4>; + status = "disabled"; + }; + + i3c0: i3c@42a50000 { + compatible = "infineon,cat1-i3c"; + reg = <0x42a50000 0x438>; + interrupts = <176 4>; + status = "disabled"; + }; + + watchdog0: watchdog@4240c000 { + compatible = "infineon,cat1-watchdog"; + reg = <0x4240c000 0x180>; + interrupts = <54 4>; + status = "disabled"; + }; + + mcwdt0: mcwdt@4240d000 { + compatible = "infineon,cat1-lp-timer-pdl"; + reg = <0x4240d000 0x40>; + interrupts = <55 4>; + status = "disabled"; + }; + + mcwdt1: mcwdt@4240d040 { + compatible = "infineon,cat1-lp-timer-pdl"; + reg = <0x4240d040 0x40>; + interrupts = <0 4>; + status = "disabled"; + }; + + tcpwm0: tcpwm0@42860000 { + reg = <0x42860000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + tcpwm0_0: tcpwm0_0@42860000 { + compatible = "infineon,tcpwm"; + reg = <0x42860000 0x80>; + interrupts = <110 4>; + resolution = <32>; + status = "disabled"; + + pwm0_0: pwm0_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_0: counter0_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_1: tcpwm0_1@42860080 { + compatible = "infineon,tcpwm"; + reg = <0x42860080 0x80>; + interrupts = <111 4>; + resolution = <32>; + status = "disabled"; + + pwm0_1: pwm0_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_1: counter0_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_2: tcpwm0_2@42860100 { + compatible = "infineon,tcpwm"; + reg = <0x42860100 0x80>; + interrupts = <112 4>; + resolution = <32>; + status = "disabled"; + + pwm0_2: pwm0_2 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_2: counter0_2 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_3: tcpwm0_3@42860180 { + compatible = "infineon,tcpwm"; + reg = <0x42860180 0x80>; + interrupts = <113 4>; + resolution = <32>; + status = "disabled"; + + pwm0_3: pwm0_3 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_3: counter0_3 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_4: tcpwm0_4@42860200 { + compatible = "infineon,tcpwm"; + reg = <0x42860200 0x80>; + interrupts = <114 4>; + resolution = <32>; + status = "disabled"; + + pwm0_4: pwm0_4 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_4: counter0_4 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_5: tcpwm0_5@42860280 { + compatible = "infineon,tcpwm"; + reg = <0x42860280 0x80>; + interrupts = <115 4>; + resolution = <32>; + status = "disabled"; + + pwm0_5: pwm0_5 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_5: counter0_5 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_6: tcpwm0_6@42860300 { + compatible = "infineon,tcpwm"; + reg = <0x42860300 0x80>; + interrupts = <116 4>; + resolution = <32>; + status = "disabled"; + + pwm0_6: pwm0_6 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_6: counter0_6 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_7: tcpwm0_7@42860380 { + compatible = "infineon,tcpwm"; + reg = <0x42860380 0x80>; + interrupts = <117 4>; + resolution = <32>; + status = "disabled"; + + pwm0_7: pwm0_7 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_7: counter0_7 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + }; + + tcpwm1: tcpwm1@42868000 { + reg = <0x42868000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + tcpwm1_0: tcpwm1_0@42868000 { + compatible = "infineon,tcpwm"; + reg = <0x42868000 0x80>; + interrupts = <118 4>; + resolution = <16>; + status = "disabled"; + + pwm1_0: pwm1_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_0: counter1_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_1: tcpwm1_1@42868080 { + compatible = "infineon,tcpwm"; + reg = <0x42868080 0x80>; + interrupts = <119 4>; + resolution = <16>; + status = "disabled"; + + pwm1_1: pwm1_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_1: counter1_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_2: tcpwm1_2@42868100 { + compatible = "infineon,tcpwm"; + reg = <0x42868100 0x80>; + interrupts = <120 4>; + resolution = <16>; + status = "disabled"; + + pwm1_2: pwm1_2 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_2: counter1_2 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_3: tcpwm1_3@42868180 { + compatible = "infineon,tcpwm"; + reg = <0x42868180 0x80>; + interrupts = <121 4>; + resolution = <16>; + status = "disabled"; + + pwm1_3: pwm1_3 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_3: counter1_3 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_4: tcpwm1_4@42868200 { + compatible = "infineon,tcpwm"; + reg = <0x42868200 0x80>; + interrupts = <122 4>; + resolution = <16>; + status = "disabled"; + + pwm1_4: pwm1_4 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_4: counter1_4 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_5: tcpwm1_5@42868280 { + compatible = "infineon,tcpwm"; + reg = <0x42868280 0x80>; + interrupts = <123 4>; + resolution = <16>; + status = "disabled"; + + pwm1_5: pwm1_5 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_5: counter1_5 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_6: tcpwm1_6@42868300 { + compatible = "infineon,tcpwm"; + reg = <0x42868300 0x80>; + interrupts = <124 4>; + resolution = <16>; + status = "disabled"; + + pwm1_6: pwm1_6 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_6: counter1_6 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_7: tcpwm1_7@42868380 { + compatible = "infineon,tcpwm"; + reg = <0x42868380 0x80>; + interrupts = <125 4>; + resolution = <16>; + status = "disabled"; + + pwm1_7: pwm1_7 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_7: counter1_7 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_8: tcpwm1_8@42868400 { + compatible = "infineon,tcpwm"; + reg = <0x42868400 0x80>; + interrupts = <126 4>; + resolution = <16>; + status = "disabled"; + + pwm1_8: pwm1_8 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_8: counter1_8 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_9: tcpwm1_9@42868480 { + compatible = "infineon,tcpwm"; + reg = <0x42868480 0x80>; + interrupts = <127 4>; + resolution = <16>; + status = "disabled"; + + pwm1_9: pwm1_9 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_9: counter1_9 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_10: tcpwm1_10@42868500 { + compatible = "infineon,tcpwm"; + reg = <0x42868500 0x80>; + interrupts = <128 4>; + resolution = <16>; + status = "disabled"; + + pwm1_10: pwm1_10 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_10: counter1_10 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_11: tcpwm1_11@42868580 { + compatible = "infineon,tcpwm"; + reg = <0x42868580 0x80>; + interrupts = <129 4>; + resolution = <16>; + status = "disabled"; + + pwm1_11: pwm1_11 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_11: counter1_11 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_12: tcpwm1_12@42868600 { + compatible = "infineon,tcpwm"; + reg = <0x42868600 0x80>; + interrupts = <130 4>; + resolution = <16>; + status = "disabled"; + + pwm1_12: pwm1_12 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_12: counter1_12 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_13: tcpwm1_13@42868680 { + compatible = "infineon,tcpwm"; + reg = <0x42868680 0x80>; + interrupts = <131 4>; + resolution = <16>; + status = "disabled"; + + pwm1_13: pwm1_13 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_13: counter1_13 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_14: tcpwm1_14@42868700 { + compatible = "infineon,tcpwm"; + reg = <0x42868700 0x80>; + interrupts = <132 4>; + resolution = <16>; + status = "disabled"; + + pwm1_14: pwm1_14 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_14: counter1_14 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_15: tcpwm1_15@42868780 { + compatible = "infineon,tcpwm"; + reg = <0x42868780 0x80>; + interrupts = <133 4>; + resolution = <16>; + status = "disabled"; + + pwm1_15: pwm1_15 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_15: counter1_15 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_16: tcpwm1_16@42868800 { + compatible = "infineon,tcpwm"; + reg = <0x42868800 0x80>; + interrupts = <134 4>; + resolution = <16>; + status = "disabled"; + + pwm1_16: pwm1_16 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_16: counter1_16 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_17: tcpwm1_17@42868880 { + compatible = "infineon,tcpwm"; + reg = <0x42868880 0x80>; + interrupts = <135 4>; + resolution = <16>; + status = "disabled"; + + pwm1_17: pwm1_17 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_17: counter1_17 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_18: tcpwm1_18@42868900 { + compatible = "infineon,tcpwm"; + reg = <0x42868900 0x80>; + interrupts = <136 4>; + resolution = <16>; + status = "disabled"; + + pwm1_18: pwm1_18 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_18: counter1_18 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_19: tcpwm1_19@42868980 { + compatible = "infineon,tcpwm"; + reg = <0x42868980 0x80>; + interrupts = <137 4>; + resolution = <16>; + status = "disabled"; + + pwm1_19: pwm1_19 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_19: counter1_19 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_20: tcpwm1_20@42868a00 { + compatible = "infineon,tcpwm"; + reg = <0x42868a00 0x80>; + interrupts = <138 4>; + resolution = <16>; + status = "disabled"; + + pwm1_20: pwm1_20 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_20: counter1_20 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_21: tcpwm1_21@42868a80 { + compatible = "infineon,tcpwm"; + reg = <0x42868a80 0x80>; + interrupts = <139 4>; + resolution = <16>; + status = "disabled"; + + pwm1_21: pwm1_21 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_21: counter1_21 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_22: tcpwm1_22@42868b00 { + compatible = "infineon,tcpwm"; + reg = <0x42868b00 0x80>; + interrupts = <140 4>; + resolution = <16>; + status = "disabled"; + + pwm1_22: pwm1_22 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_22: counter1_22 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_23: tcpwm1_23@42868b80 { + compatible = "infineon,tcpwm"; + reg = <0x42868b80 0x80>; + interrupts = <141 4>; + resolution = <16>; + status = "disabled"; + + pwm1_23: pwm1_23 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_23: counter1_23 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + }; + + dma0: dw@42270000 { + #dma-cells = <1>; + compatible = "infineon,cat1-dma-pdl"; + reg = <0x42270000 0x10000>; + dma-channels = <16>; + interrupts = <82 4>, /* CH0 */ + <83 4>, /* CH1 */ + <84 4>, /* CH2 */ + <85 4>, /* CH3 */ + <86 4>, /* CH4 */ + <87 4>, /* CH5 */ + <88 4>, /* CH6 */ + <89 4>, /* CH7 */ + <90 4>, /* CH8 */ + <91 4>, /* CH9 */ + <92 4>, /* CH10 */ + <93 4>, /* CH11 */ + <94 4>, /* CH12 */ + <95 4>, /* CH13 */ + <96 4>, /* CH14 */ + <97 4>; /* CH15 */ + status = "disabled"; + }; + + dma1: dw@42280000 { + #dma-cells = <1>; + compatible = "infineon,cat1-dma-pdl"; + reg = <0x42280000 0x10000>; + dma-channels = <16>; + interrupts = <181 4>, /* CH0 */ + <182 4>, /* CH1 */ + <183 4>, /* CH2 */ + <184 4>, /* CH3 */ + <185 4>, /* CH4 */ + <186 4>, /* CH5 */ + <187 4>, /* CH6 */ + <188 4>, /* CH7 */ + <189 4>, /* CH8 */ + <190 4>, /* CH9 */ + <191 4>, /* CH10 */ + <192 4>, /* CH11 */ + <193 4>, /* CH12 */ + <194 4>, /* CH13 */ + <195 4>, /* CH14 */ + <196 4>; /* CH15 */ + status = "disabled"; + }; + + sdhc0: sdhc@44810000 { + compatible = "infineon,cat1-sdhc-sdio"; + reg = <0x44810000 0x2000>; + interrupts = <155 4>, /* SDIO wakeup interrupt for mxsdhc */ + <154 6>; /* Consolidated interrupt for mxsdhc */ + status = "disabled"; + }; + + sdhc1: sdhc@44820000 { + compatible = "infineon,cat1-sdhc-sdio"; + reg = <0x44820000 0x2000>; + interrupts = <157 4>, /* SDIO wakeup interrupt for mxsdhc */ + <156 6>; /* Consolidated interrupt for mxsdhc */ + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.ewlb-235.dtsi b/dts/arm/infineon/edge/pse84/pse84.ewlb-235.dtsi new file mode 100644 index 0000000000000..20c7dd1c10030 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.ewlb-235.dtsi @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84.dtsi" + +/ { + soc { + pinctrl: pinctrl@42800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_i2c_scl: p10_0_scb4_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_i2c_scl: p11_0_scb6_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_i2c_scl: p21_6_scb3_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_i2c_sda: p10_1_scb4_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_i2c_sda: p11_1_scb6_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_i2c_sda: p21_5_scb3_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_m_clk: p10_1_scb4_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_m_clk: p11_0_scb6_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_m_clk: p21_6_scb3_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_m_miso: p10_3_scb4_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_m_miso: p11_2_scb6_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_m_miso: p13_7_scb8_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_m_miso: p21_4_scb3_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_m_mosi: p10_2_scb4_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_m_mosi: p11_1_scb6_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_m_mosi: p21_5_scb3_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_m_select0: p0_0_scb3_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_m_select0: p10_4_scb4_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_m_select0: p11_3_scb6_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_m_select0: p14_7_scb8_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_m_select1: p10_5_scb4_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_m_select1: p11_4_scb6_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_m_select1: p13_6_scb7_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_m_select1: p14_6_scb8_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_m_select1: p15_4_scb9_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_m_select1: p17_7_scb11_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_m_select1: p20_0_scb1_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_s_clk: p10_1_scb4_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_s_clk: p11_0_scb6_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_s_clk: p21_6_scb3_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_s_miso: p10_3_scb4_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_s_miso: p11_2_scb6_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_s_miso: p13_7_scb8_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_s_miso: p21_4_scb3_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_s_mosi: p10_2_scb4_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_s_mosi: p11_1_scb6_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_s_mosi: p21_5_scb3_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_s_select0: p0_0_scb3_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_s_select0: p10_4_scb4_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_s_select0: p11_3_scb6_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_s_select0: p14_7_scb8_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_s_select1: p10_5_scb4_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_s_select1: p11_4_scb6_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_s_select1: p13_6_scb7_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_s_select1: p14_6_scb8_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_s_select1: p15_4_scb9_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_s_select1: p17_7_scb11_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_s_select1: p20_0_scb1_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_uart_cts: p10_2_scb4_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_uart_cts: p11_2_scb6_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_uart_cts: p13_7_scb8_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_uart_cts: p21_4_scb3_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_uart_rts: p10_3_scb4_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_uart_rts: p11_3_scb6_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_uart_rts: p14_7_scb8_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_uart_rx: p10_0_scb4_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_uart_rx: p11_0_scb6_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_uart_rx: p21_6_scb3_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_uart_tx: p10_1_scb4_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_uart_tx: p11_1_scb6_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_uart_tx: p21_5_scb3_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_sdhc0_card_if_pwr_en: p21_4_sdhc0_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p0_0_pwm0_0: p0_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm0_6: p8_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm0_1: p10_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm0_2: p10_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm0_3: p10_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm0_4: p10_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm0_5: p11_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm0_6: p11_2_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm0_7: p11_4_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm0_0: p11_6_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm0_6: p13_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm0_7: p14_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm0_1: p14_6_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm0_4: p15_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm0_5: p15_6_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm0_7: p20_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm0_1: p20_2_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm0_2: p20_3_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm0_5: p21_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm0_6: p21_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p0_0_pwm1_0: p0_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm1_22: p8_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm1_1: p10_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm1_2: p10_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm1_3: p10_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm1_4: p10_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm1_5: p11_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm1_6: p11_2_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm1_7: p11_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm1_8: p11_6_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm1_14: p13_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm1_15: p14_1_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm1_17: p14_6_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm1_20: p15_4_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm1_21: p15_6_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm1_7: p20_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm1_8: p20_5_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm1_9: p20_6_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm1_10: p20_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm1_13: p21_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm1_14: p21_6_pwm1_14 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p0_1_pwm0_0: p0_1_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm0_5: p8_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm0_6: p8_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm0_1: p10_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm0_2: p10_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm0_3: p10_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm0_4: p10_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm0_5: p11_1_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm0_6: p11_3_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm0_7: p11_5_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm0_0: p11_7_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm0_6: p13_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm0_7: p14_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm0_1: p14_7_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm0_4: p15_5_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm0_5: p15_7_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm0_7: p17_7_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm0_7: p20_4_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm0_0: p20_5_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm0_1: p20_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm0_2: p20_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm0_5: p21_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm1_21: p8_5_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm1_22: p8_7_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm1_1: p10_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm1_2: p10_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm1_3: p10_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm1_4: p10_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm1_5: p11_1_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm1_6: p11_3_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm1_7: p11_5_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm1_8: p11_7_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm1_14: p13_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm1_15: p14_2_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm1_17: p14_7_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm1_20: p15_5_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm1_21: p15_7_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm1_23: p17_7_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm1_7: p20_0_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm1_9: p20_2_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm1_10: p20_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm1_13: p21_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.ewlb-235_s.dtsi b/dts/arm/infineon/edge/pse84/pse84.ewlb-235_s.dtsi new file mode 100644 index 0000000000000..7022a837a8bbc --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.ewlb-235_s.dtsi @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84_s.dtsi" + +/ { + soc { + pinctrl: pinctrl@52800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_i2c_scl: p10_0_scb4_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_i2c_scl: p11_0_scb6_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_i2c_scl: p21_6_scb3_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_i2c_sda: p10_1_scb4_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_i2c_sda: p11_1_scb6_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_i2c_sda: p21_5_scb3_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_m_clk: p10_1_scb4_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_m_clk: p11_0_scb6_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_m_clk: p21_6_scb3_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_m_miso: p10_3_scb4_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_m_miso: p11_2_scb6_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_m_miso: p13_7_scb8_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_m_miso: p21_4_scb3_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_m_mosi: p10_2_scb4_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_m_mosi: p11_1_scb6_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_m_mosi: p21_5_scb3_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_m_select0: p0_0_scb3_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_m_select0: p10_4_scb4_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_m_select0: p11_3_scb6_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_m_select0: p14_7_scb8_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_m_select1: p10_5_scb4_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_m_select1: p11_4_scb6_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_m_select1: p13_6_scb7_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_m_select1: p14_6_scb8_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_m_select1: p15_4_scb9_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_m_select1: p17_7_scb11_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_m_select1: p20_0_scb1_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_spi_s_clk: p10_1_scb4_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_spi_s_clk: p11_0_scb6_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_spi_s_clk: p21_6_scb3_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_spi_s_miso: p10_3_scb4_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_spi_s_miso: p11_2_scb6_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_spi_s_miso: p13_7_scb8_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_spi_s_miso: p21_4_scb3_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_spi_s_mosi: p10_2_scb4_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_spi_s_mosi: p11_1_scb6_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_spi_s_mosi: p21_5_scb3_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p0_0_scb3_spi_s_select0: p0_0_scb3_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_scb4_spi_s_select0: p10_4_scb4_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_spi_s_select0: p11_3_scb6_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_spi_s_select0: p14_7_scb8_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_scb4_spi_s_select1: p10_5_scb4_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_scb6_spi_s_select1: p11_4_scb6_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_scb7_spi_s_select1: p13_6_scb7_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_scb8_spi_s_select1: p14_6_scb8_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_scb9_spi_s_select1: p15_4_scb9_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_scb11_spi_s_select1: p17_7_scb11_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_scb1_spi_s_select1: p20_0_scb1_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_scb4_uart_cts: p10_2_scb4_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_scb6_uart_cts: p11_2_scb6_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_scb8_uart_cts: p13_7_scb8_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_scb3_uart_cts: p21_4_scb3_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_scb4_uart_rts: p10_3_scb4_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_scb6_uart_rts: p11_3_scb6_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_scb8_uart_rts: p14_7_scb8_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_scb4_uart_rx: p10_0_scb4_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_scb6_uart_rx: p11_0_scb6_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_scb3_uart_rx: p21_6_scb3_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_scb4_uart_tx: p10_1_scb4_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_scb6_uart_tx: p11_1_scb6_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_scb3_uart_tx: p21_5_scb3_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_sdhc0_card_if_pwr_en: p21_4_sdhc0_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p0_0_pwm0_0: p0_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm0_6: p8_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm0_1: p10_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm0_2: p10_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm0_3: p10_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm0_4: p10_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm0_5: p11_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm0_6: p11_2_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm0_7: p11_4_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm0_0: p11_6_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm0_6: p13_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm0_7: p14_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm0_1: p14_6_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm0_4: p15_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm0_5: p15_6_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm0_7: p20_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm0_1: p20_2_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm0_2: p20_3_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm0_5: p21_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm0_6: p21_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p0_0_pwm1_0: p0_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_6_pwm1_22: p8_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_0_pwm1_1: p10_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_2_pwm1_2: p10_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_4_pwm1_3: p10_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p10_6_pwm1_4: p10_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_0_pwm1_5: p11_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_2_pwm1_6: p11_2_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_4_pwm1_7: p11_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p11_6_pwm1_8: p11_6_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_6_pwm1_14: p13_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_1_pwm1_15: p14_1_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_6_pwm1_17: p14_6_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_4_pwm1_20: p15_4_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_6_pwm1_21: p15_6_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm1_7: p20_4_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm1_8: p20_5_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm1_9: p20_6_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm1_10: p20_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_4_pwm1_13: p21_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_6_pwm1_14: p21_6_pwm1_14 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p0_1_pwm0_0: p0_1_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm0_5: p8_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm0_6: p8_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm0_1: p10_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm0_2: p10_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm0_3: p10_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm0_4: p10_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm0_5: p11_1_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm0_6: p11_3_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm0_7: p11_5_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm0_0: p11_7_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm0_6: p13_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm0_7: p14_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm0_1: p14_7_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm0_4: p15_5_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm0_5: p15_7_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm0_7: p17_7_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_4_pwm0_7: p20_4_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_5_pwm0_0: p20_5_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_6_pwm0_1: p20_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_7_pwm0_2: p20_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm0_5: p21_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_5_pwm1_21: p8_5_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_7_pwm1_22: p8_7_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_1_pwm1_1: p10_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_3_pwm1_2: p10_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_5_pwm1_3: p10_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p10_7_pwm1_4: p10_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_1_pwm1_5: p11_1_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_3_pwm1_6: p11_3_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_5_pwm1_7: p11_5_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p11_7_pwm1_8: p11_7_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_7_pwm1_14: p13_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_2_pwm1_15: p14_2_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_7_pwm1_17: p14_7_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_5_pwm1_20: p15_5_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_7_pwm1_21: p15_7_pwm1_21_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_7_pwm1_23: p17_7_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_0_pwm1_7: p20_0_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_2_pwm1_9: p20_2_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_3_pwm1_10: p20_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_5_pwm1_13: p21_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.wlb-154.dtsi b/dts/arm/infineon/edge/pse84/pse84.wlb-154.dtsi new file mode 100644 index 0000000000000..f9f1dc9959d8a --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.wlb-154.dtsi @@ -0,0 +1,1358 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84.dtsi" + +/ { + soc { + /delete-node/ gpio@42810000; // gpio_prt0 + /delete-node/ gpio@42810500; // gpio_prt10 + /delete-node/ gpio@42810580; // gpio_prt11 + + pinctrl: pinctrl@42800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; + +&gpio_prt8 { + ngpios = <5>; +}; + +&gpio_prt13 { + ngpios = <6>; +}; + +&gpio_prt14 { + ngpios = <2>; +}; + +&gpio_prt15 { + ngpios = <4>; +}; + +&gpio_prt17 { + ngpios = <7>; +}; + +&gpio_prt20 { + ngpios = <1>; +}; + +&gpio_prt21 { + ngpios = <5>; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84.wlb-154_s.dtsi b/dts/arm/infineon/edge/pse84/pse84.wlb-154_s.dtsi new file mode 100644 index 0000000000000..e9d4eb96c2a26 --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84.wlb-154_s.dtsi @@ -0,0 +1,1358 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "pse84_s.dtsi" + +/ { + soc { + /delete-node/ gpio@52810000; // gpio_prt0 + /delete-node/ gpio@52810500; // gpio_prt10 + /delete-node/ gpio@52810580; // gpio_prt11 + + pinctrl: pinctrl@52800000 { + /* i3c_i3c_scl */ + /omit-if-no-ref/ p3_0_i3c0_i3c_scl: p3_0_i3c0_i3c_scl { + pinmux = ; + }; + + /* i3c_i3c_sda */ + /omit-if-no-ref/ p3_1_i3c0_i3c_sda: p3_1_i3c0_i3c_sda { + pinmux = ; + }; + + /* scb_i2c_scl */ + /omit-if-no-ref/ p6_5_scb2_i2c_scl: p6_5_scb2_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_i2c_scl: p8_0_scb0_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_i2c_scl: p9_3_scb1_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_i2c_scl: p13_1_scb7_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_i2c_scl: p14_4_scb8_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_i2c_scl: p15_0_scb9_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_i2c_scl: p16_0_scb10_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_i2c_scl: p17_0_scb5_i2c_scl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_i2c_scl: p17_2_scb11_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p6_7_scb2_i2c_sda: p6_7_scb2_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_i2c_sda: p8_1_scb0_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_i2c_sda: p9_2_scb1_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_i2c_sda: p13_2_scb7_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_i2c_sda: p14_3_scb8_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_i2c_sda: p15_1_scb9_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_i2c_sda: p16_1_scb10_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_i2c_sda: p17_1_scb5_i2c_sda { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_i2c_sda: p17_3_scb11_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_m_clk: p6_5_scb2_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_m_clk: p8_0_scb0_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_m_clk: p9_3_scb1_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_m_clk: p13_1_scb7_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_m_clk: p14_4_scb8_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_m_clk: p15_0_scb9_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_m_clk: p16_0_scb10_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_m_clk: p17_0_scb5_spi_m_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_m_clk: p17_2_scb11_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_m_miso: p6_4_scb2_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_m_miso: p8_4_scb0_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_m_miso: p9_1_scb1_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_m_miso: p13_3_scb7_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_m_miso: p15_2_scb9_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_m_miso: p16_2_scb10_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_m_miso: p16_5_scb5_spi_m_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_m_miso: p17_5_scb11_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_m_mosi: p6_7_scb2_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_m_mosi: p8_1_scb0_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_m_mosi: p9_2_scb1_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_m_mosi: p13_2_scb7_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_m_mosi: p14_3_scb8_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_m_mosi: p15_1_scb9_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_m_mosi: p16_1_scb10_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_m_mosi: p17_1_scb5_spi_m_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_m_mosi: p17_3_scb11_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p6_6_scb2_spi_m_select0: p6_6_scb2_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_m_select0: p8_2_scb0_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_m_select0: p9_0_scb1_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_m_select0: p13_4_scb7_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_m_select0: p15_3_scb9_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_m_select0: p16_3_scb10_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_m_select0: p16_6_scb5_spi_m_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_m_select0: p17_6_scb11_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_m_select1: p6_3_scb2_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_m_select1: p8_3_scb0_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_m_select1: p16_4_scb10_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_m_select1: p16_7_scb5_spi_m_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_m_select1: p21_7_scb3_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p6_5_scb2_spi_s_clk: p6_5_scb2_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_scb0_spi_s_clk: p8_0_scb0_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_spi_s_clk: p9_3_scb1_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_spi_s_clk: p13_1_scb7_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_spi_s_clk: p14_4_scb8_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_spi_s_clk: p15_0_scb9_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_spi_s_clk: p16_0_scb10_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_spi_s_clk: p17_0_scb5_spi_s_clk { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_spi_s_clk: p17_2_scb11_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p6_4_scb2_spi_s_miso: p6_4_scb2_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_scb0_spi_s_miso: p8_4_scb0_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_spi_s_miso: p9_1_scb1_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_spi_s_miso: p13_3_scb7_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_spi_s_miso: p15_2_scb9_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_spi_s_miso: p16_2_scb10_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_spi_s_miso: p16_5_scb5_spi_s_miso { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_spi_s_miso: p17_5_scb11_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p6_7_scb2_spi_s_mosi: p6_7_scb2_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_scb0_spi_s_mosi: p8_1_scb0_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_spi_s_mosi: p9_2_scb1_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_spi_s_mosi: p13_2_scb7_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_spi_s_mosi: p14_3_scb8_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_spi_s_mosi: p15_1_scb9_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_spi_s_mosi: p16_1_scb10_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_spi_s_mosi: p17_1_scb5_spi_s_mosi { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_spi_s_mosi: p17_3_scb11_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p6_6_scb2_spi_s_select0: p6_6_scb2_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_scb0_spi_s_select0: p8_2_scb0_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_spi_s_select0: p9_0_scb1_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_spi_s_select0: p13_4_scb7_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_spi_s_select0: p15_3_scb9_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_spi_s_select0: p16_3_scb10_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_spi_s_select0: p16_6_scb5_spi_s_select0 { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_spi_s_select0: p17_6_scb11_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p6_3_scb2_spi_s_select1: p6_3_scb2_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_scb0_spi_s_select1: p8_3_scb0_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_scb10_spi_s_select1: p16_4_scb10_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_scb5_spi_s_select1: p16_7_scb5_spi_s_select1 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_spi_s_select1: p21_7_scb3_spi_s_select1 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p6_4_scb2_uart_cts: p6_4_scb2_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_scb1_uart_cts: p9_1_scb1_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_scb7_uart_cts: p13_3_scb7_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_scb9_uart_cts: p15_2_scb9_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_scb10_uart_cts: p16_2_scb10_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_scb5_uart_cts: p16_5_scb5_uart_cts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_scb11_uart_cts: p17_5_scb11_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p6_6_scb2_uart_rts: p6_6_scb2_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_scb1_uart_rts: p9_0_scb1_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_scb7_uart_rts: p13_4_scb7_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_scb9_uart_rts: p15_3_scb9_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_scb10_uart_rts: p16_3_scb10_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_scb5_uart_rts: p16_6_scb5_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_scb11_uart_rts: p17_6_scb11_uart_rts { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_scb3_uart_rts: p21_7_scb3_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p6_5_scb2_uart_rx: p6_5_scb2_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_scb1_uart_rx: p9_3_scb1_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_scb7_uart_rx: p13_1_scb7_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_scb8_uart_rx: p14_4_scb8_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_scb9_uart_rx: p15_0_scb9_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_scb10_uart_rx: p16_0_scb10_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_scb5_uart_rx: p17_0_scb5_uart_rx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_scb11_uart_rx: p17_2_scb11_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p6_7_scb2_uart_tx: p6_7_scb2_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_scb1_uart_tx: p9_2_scb1_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_scb7_uart_tx: p13_2_scb7_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_scb8_uart_tx: p14_3_scb8_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_scb9_uart_tx: p15_1_scb9_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_scb10_uart_tx: p16_1_scb10_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_scb5_uart_tx: p17_1_scb5_uart_tx { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_scb11_uart_tx: p17_3_scb11_uart_tx { + pinmux = ; + }; + + /* sdhc_card_cmd */ + /omit-if-no-ref/ p7_0_sdhc1_card_cmd: p7_0_sdhc1_card_cmd { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_sdhc0_card_cmd: p21_0_sdhc0_card_cmd { + pinmux = ; + }; + + /* sdhc_card_dat_3to0 */ + /omit-if-no-ref/ p7_3_sdhc1_card_dat_3to0: p7_3_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_sdhc1_card_dat_3to0: p7_5_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_sdhc1_card_dat_3to0: p7_6_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_sdhc1_card_dat_3to0: p7_7_sdhc1_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_sdhc0_card_dat_3to0: p12_1_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_sdhc0_card_dat_3to0: p12_2_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_sdhc0_card_dat_3to0: p12_4_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_sdhc0_card_dat_3to0: p12_5_sdhc0_card_dat_3to0 { + pinmux = ; + }; + + /* sdhc_card_dat_7to4 */ + /omit-if-no-ref/ p6_4_sdhc1_card_dat_7to4: p6_4_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_sdhc1_card_dat_7to4: p6_5_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_sdhc1_card_dat_7to4: p6_6_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_sdhc1_card_dat_7to4: p6_7_sdhc1_card_dat_7to4 { + pinmux = ; + }; + + /* sdhc_card_detect_n */ + /omit-if-no-ref/ p7_4_sdhc1_card_detect_n: p7_4_sdhc1_card_detect_n { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_sdhc0_card_detect_n: p21_1_sdhc0_card_detect_n { + pinmux = ; + }; + + /* sdhc_card_emmc_reset_n */ + /omit-if-no-ref/ + p7_2_sdhc1_card_emmc_reset_n: p7_2_sdhc1_card_emmc_reset_n { + pinmux = ; + }; + + /* sdhc_card_if_pwr_en */ + /omit-if-no-ref/ p6_2_sdhc1_card_if_pwr_en: p6_2_sdhc1_card_if_pwr_en { + pinmux = ; + }; + + /* sdhc_card_mech_write_prot */ + /omit-if-no-ref/ + p3_0_sdhc1_card_mech_write_prot: p3_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p6_0_sdhc1_card_mech_write_prot: p6_0_sdhc1_card_mech_write_prot { + pinmux = ; + }; + + /omit-if-no-ref/ + p21_2_sdhc0_card_mech_write_prot: p21_2_sdhc0_card_mech_write_prot { + pinmux = ; + }; + + /* sdhc_clk_card */ + /omit-if-no-ref/ p7_1_sdhc1_clk_card: p7_1_sdhc1_clk_card { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_sdhc0_clk_card: p12_0_sdhc0_clk_card { + pinmux = ; + }; + + /* sdhc_io_volt_sel */ + /omit-if-no-ref/ p6_3_sdhc1_io_volt_sel: p6_3_sdhc1_io_volt_sel { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_sdhc0_io_volt_sel: p21_3_sdhc0_io_volt_sel { + pinmux = ; + }; + + /* sdhc_led_ctrl */ + /omit-if-no-ref/ p6_1_sdhc1_led_ctrl: p6_1_sdhc1_led_ctrl { + pinmux = ; + }; + + /* PWM tcpwm_line*/ + /omit-if-no-ref/ p1_0_pwm0_1: p1_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm0_2: p1_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm0_3: p1_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm0_4: p1_6_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm0_5: p2_0_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm0_6: p3_1_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm0_7: p4_1_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm0_0: p4_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm0_1: p4_5_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm0_2: p4_7_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm0_3: p6_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm0_4: p6_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm0_5: p6_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm0_6: p6_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm0_7: p7_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm0_0: p7_2_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm0_1: p7_4_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm0_2: p7_6_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm0_3: p8_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm0_4: p8_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm0_5: p8_4_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm0_7: p9_0_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm0_0: p9_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm0_1: p12_0_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm0_2: p12_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm0_3: p12_4_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm0_4: p13_1_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm0_5: p13_3_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm0_0: p14_3_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm0_2: p15_0_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm0_3: p15_2_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm0_0: p16_0_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm0_1: p16_1_pwm0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm0_2: p16_2_pwm0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm0_3: p16_3_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm0_4: p16_4_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm0_5: p16_5_pwm0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm0_6: p16_6_pwm0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm0_7: p16_7_pwm0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm0_0: p20_1_pwm0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm0_3: p21_0_pwm0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm0_4: p21_2_pwm0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_0_pwm1_1: p1_0_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_2_pwm1_2: p1_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_4_pwm1_3: p1_4_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p1_6_pwm1_4: p1_6_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p2_0_pwm1_5: p2_0_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p3_1_pwm1_6: p3_1_pwm1_6 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_1_pwm1_7: p4_1_pwm1_7 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_3_pwm1_8: p4_3_pwm1_8 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_5_pwm1_9: p4_5_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p4_7_pwm1_10: p4_7_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_0_pwm1_11: p6_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_2_pwm1_12: p6_2_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_4_pwm1_13: p6_4_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p6_6_pwm1_14: p6_6_pwm1_14 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_0_pwm1_15: p7_0_pwm1_15 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_2_pwm1_16: p7_2_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_4_pwm1_17: p7_4_pwm1_17 { + pinmux = ; + }; + + /omit-if-no-ref/ p7_6_pwm1_18: p7_6_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_0_pwm1_19: p8_0_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_2_pwm1_20: p8_2_pwm1_20 { + pinmux = ; + }; + + /omit-if-no-ref/ p8_4_pwm1_21: p8_4_pwm1_21 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm1_23: p9_2_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm1_0: p9_3_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_0_pwm1_9: p12_0_pwm1_9 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_2_pwm1_10: p12_2_pwm1_10 { + pinmux = ; + }; + + /omit-if-no-ref/ p12_4_pwm1_11: p12_4_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_1_pwm1_12: p13_1_pwm1_12 { + pinmux = ; + }; + + /omit-if-no-ref/ p13_3_pwm1_13: p13_3_pwm1_13 { + pinmux = ; + }; + + /omit-if-no-ref/ p14_3_pwm1_16: p14_3_pwm1_16 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_0_pwm1_18: p15_0_pwm1_18 { + pinmux = ; + }; + + /omit-if-no-ref/ p15_2_pwm1_19: p15_2_pwm1_19 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_0_pwm1_0: p16_0_pwm1_0 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_1_pwm1_1: p16_1_pwm1_1 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_2_pwm1_2: p16_2_pwm1_2 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_3_pwm1_3: p16_3_pwm1_3 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_4_pwm1_4: p16_4_pwm1_4 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_5_pwm1_5: p16_5_pwm1_5 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_6_pwm1_22: p16_6_pwm1_22 { + pinmux = ; + }; + + /omit-if-no-ref/ p16_7_pwm1_23: p16_7_pwm1_23 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_0_pwm1_11: p21_0_pwm1_11 { + pinmux = ; + }; + + /omit-if-no-ref/ p21_2_pwm1_12: p21_2_pwm1_12 { + pinmux = ; + }; + + /* PWM tcpwm_line_compl*/ + /omit-if-no-ref/ p1_1_pwm0_1: p1_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm0_2: p1_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm0_3: p1_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm0_4: p1_7_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm0_5: p3_0_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm0_6: p4_0_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm0_7: p4_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm0_0: p4_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm0_1: p4_6_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm0_2: p5_0_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm0_3: p6_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm0_4: p6_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm0_5: p6_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm0_6: p6_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm0_7: p7_1_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm0_0: p7_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm0_1: p7_5_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm0_2: p7_7_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm0_3: p8_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm0_4: p8_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_2_pwm0_7: p9_2_pwm0_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_3_pwm0_0: p9_3_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm0_1: p12_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm0_2: p12_3_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm0_3: p12_5_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm0_4: p13_2_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm0_5: p13_4_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm0_0: p14_4_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm0_2: p15_1_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm0_3: p15_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm0_0: p17_0_pwm0_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm0_1: p17_1_pwm0_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm0_2: p17_2_pwm0_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm0_3: p17_3_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm0_4: p17_4_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm0_5: p17_5_pwm0_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm0_6: p17_6_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm0_3: p21_1_pwm0_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm0_4: p21_3_pwm0_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm0_6: p21_7_pwm0_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_1_pwm1_1: p1_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_3_pwm1_2: p1_3_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_5_pwm1_3: p1_5_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p1_7_pwm1_4: p1_7_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p3_0_pwm1_5: p3_0_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_0_pwm1_6: p4_0_pwm1_6_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_2_pwm1_7: p4_2_pwm1_7_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_4_pwm1_8: p4_4_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p4_6_pwm1_9: p4_6_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p5_0_pwm1_10: p5_0_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_1_pwm1_11: p6_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_3_pwm1_12: p6_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_5_pwm1_13: p6_5_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p6_7_pwm1_14: p6_7_pwm1_14_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_1_pwm1_15: p7_1_pwm1_15_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_3_pwm1_16: p7_3_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_5_pwm1_17: p7_5_pwm1_17_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p7_7_pwm1_18: p7_7_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_1_pwm1_19: p8_1_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p8_3_pwm1_20: p8_3_pwm1_20_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_0_pwm1_23: p9_0_pwm1_23_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p9_1_pwm1_0: p9_1_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_1_pwm1_9: p12_1_pwm1_9_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_3_pwm1_10: p12_3_pwm1_10_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p12_5_pwm1_11: p12_5_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_2_pwm1_12: p13_2_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p13_4_pwm1_13: p13_4_pwm1_13_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p14_4_pwm1_16: p14_4_pwm1_16_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_1_pwm1_18: p15_1_pwm1_18_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p15_3_pwm1_19: p15_3_pwm1_19_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_0_pwm1_0: p17_0_pwm1_0_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_1_pwm1_1: p17_1_pwm1_1_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_2_pwm1_2: p17_2_pwm1_2_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_3_pwm1_3: p17_3_pwm1_3_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_4_pwm1_4: p17_4_pwm1_4_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_5_pwm1_5: p17_5_pwm1_5_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p17_6_pwm1_22: p17_6_pwm1_22_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p20_1_pwm1_8: p20_1_pwm1_8_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_1_pwm1_11: p21_1_pwm1_11_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_3_pwm1_12: p21_3_pwm1_12_compl { + pinmux = ; + }; + + /omit-if-no-ref/ p21_7_pwm1_14: p21_7_pwm1_14_compl { + pinmux = ; + }; + }; + }; +}; + +&gpio_prt8 { + ngpios = <5>; +}; + +&gpio_prt13 { + ngpios = <6>; +}; + +&gpio_prt14 { + ngpios = <2>; +}; + +&gpio_prt15 { + ngpios = <4>; +}; + +&gpio_prt17 { + ngpios = <7>; +}; + +&gpio_prt20 { + ngpios = <1>; +}; + +&gpio_prt21 { + ngpios = <5>; +}; diff --git a/dts/arm/infineon/edge/pse84/pse84_s.dtsi b/dts/arm/infineon/edge/pse84/pse84_s.dtsi new file mode 100644 index 0000000000000..2d1553d2a8ece --- /dev/null +++ b/dts/arm/infineon/edge/pse84/pse84_s.dtsi @@ -0,0 +1,1106 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + sram0: sram0@34000000 { + compatible = "mmio-sram"; + reg = <0x34000000 0x100000>; + }; + + dtcm { + #address-cells = <1>; + #size-cells = <1>; + + dtcm_m33s: dtcm_m33s@58040000 { + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x58040000 DT_SIZE_K(256)>; + zephyr,memory-region = "DTCM"; + }; + }; + + itcm { + #address-cells = <1>; + #size-cells = <1>; + + itcm_m33s: itcm_m33s@58000000 { + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x58000000 DT_SIZE_K(256)>; + zephyr,memory-region = "ITCM"; + }; + }; + + rram { + #address-cells = <1>; + #size-cells = <1>; + + rram: rram@32000000 { + compatible = "soc-nv-flash"; + reg = <0x32000000 DT_SIZE_K(512)>; + }; + }; + + socmem { + #address-cells = <1>; + #size-cells = <1>; + + socmem: socmem@36000000 { + reg = <0x36000000 DT_SIZE_M(5)>; + }; + }; + + soc { + pinctrl: pinctrl@52800000 { + compatible = "infineon,cat1-pinctrl"; + reg = <0x52800000 0x20000>; + }; + + hsiom: hsiom@52800000 { + compatible = "infineon,cat1-hsiom"; + reg = <0x52800000 0x4000>; + interrupts = <42 4>, <40 4>; + status = "disabled"; + }; + + gpio_prt0: gpio@52810000 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810000 0x80>; + interrupts = <20 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt1: gpio@52810080 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810080 0x80>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt2: gpio@52810100 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810100 0x80>; + interrupts = <21 4>; + gpio-controller; + ngpios = <1>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt3: gpio@52810180 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810180 0x80>; + interrupts = <22 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt4: gpio@52810200 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810200 0x80>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt5: gpio@52810280 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810280 0x80>; + interrupts = <23 4>; + gpio-controller; + ngpios = <1>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt6: gpio@52810300 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810300 0x80>; + interrupts = <24 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt7: gpio@52810380 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810380 0x80>; + interrupts = <25 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt8: gpio@52810400 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810400 0x80>; + interrupts = <26 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt9: gpio@52810480 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810480 0x80>; + interrupts = <27 4>; + gpio-controller; + ngpios = <4>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt10: gpio@52810500 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810500 0x80>; + interrupts = <28 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt11: gpio@52810580 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810580 0x80>; + interrupts = <29 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt12: gpio@52810600 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810600 0x80>; + interrupts = <30 4>; + gpio-controller; + ngpios = <6>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt13: gpio@52810680 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810680 0x80>; + interrupts = <31 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt14: gpio@52810700 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810700 0x80>; + interrupts = <32 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt15: gpio@52810780 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810780 0x80>; + interrupts = <33 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt16: gpio@52810800 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810800 0x80>; + interrupts = <34 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt17: gpio@52810880 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810880 0x80>; + interrupts = <35 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt18: gpio@52810900 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810900 0x80>; + interrupts = <36 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt19: gpio@52810980 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810980 0x80>; + interrupts = <37 4>; + gpio-controller; + ngpios = <2>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt20: gpio@52810a00 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810a00 0x80>; + interrupts = <38 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + gpio_prt21: gpio@52810a80 { + compatible = "infineon,cat1-gpio"; + reg = <0x52810a80 0x80>; + interrupts = <39 4>; + gpio-controller; + ngpios = <8>; + status = "disabled"; + #gpio-cells = <2>; + }; + + adc0: adc@52e80000 { + compatible = "infineon,autanalog-sar-adc"; + reg = <0x52e80000 0xf20>; + interrupts = <57 4>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + ipc0: ipc@522a0000 { + compatible = "infineon,cat1-ipc"; + reg = <0x522a0000 0x1200>; + status = "disabled"; + #ipc-config-cells = <3>; + }; + + ipc1: ipc@541d0000 { + compatible = "infineon,cat1-ipc"; + reg = <0x541d0000 0x1200>; + status = "disabled"; + #ipc-config-cells = <3>; + }; + + scb0: scb@52990000 { + compatible = "infineon,cat1-scb"; + reg = <0x52990000 0xfd0>; + interrupts = <43 4>; + status = "disabled"; + }; + + scb2: scb@529a0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529a0000 0xfd0>; + interrupts = <143 4>; + status = "disabled"; + }; + + scb3: scb@529b0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529b0000 0xfd0>; + interrupts = <144 4>; + status = "disabled"; + }; + + scb4: scb@529c0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529c0000 0xfd0>; + interrupts = <145 4>; + status = "disabled"; + }; + + scb5: scb@529d0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529d0000 0xfd0>; + interrupts = <146 4>; + status = "disabled"; + }; + + scb6: scb@529e0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529e0000 0xfd0>; + interrupts = <147 4>; + status = "disabled"; + }; + + scb7: scb@529f0000 { + compatible = "infineon,cat1-scb"; + reg = <0x529f0000 0xfd0>; + interrupts = <148 4>; + status = "disabled"; + }; + + scb8: scb@52a00000 { + compatible = "infineon,cat1-scb"; + reg = <0x52a00000 0xfd0>; + interrupts = <149 4>; + status = "disabled"; + }; + + scb9: scb@52a10000 { + compatible = "infineon,cat1-scb"; + reg = <0x52a10000 0xfd0>; + interrupts = <150 4>; + status = "disabled"; + }; + + scb10: scb@52a20000 { + compatible = "infineon,cat1-scb"; + reg = <0x52a20000 0xfd0>; + interrupts = <151 4>; + status = "disabled"; + }; + + scb11: scb@52a30000 { + compatible = "infineon,cat1-scb"; + reg = <0x52a30000 0xfd0>; + interrupts = <152 4>; + status = "disabled"; + }; + + scb1: scb@52d00000 { + compatible = "infineon,cat1-scb"; + reg = <0x52d00000 0xfd0>; + interrupts = <142 4>; + status = "disabled"; + }; + + i3c0: i3c@52a50000 { + compatible = "infineon,cat1-i3c"; + reg = <0x52a50000 0x438>; + interrupts = <176 4>; + status = "disabled"; + }; + + watchdog0: watchdog@5240c000 { + compatible = "infineon,cat1-watchdog"; + reg = <0x5240c000 0x180>; + interrupts = <54 4>; + status = "disabled"; + }; + + mcwdt0: mcwdt@5240d000 { + compatible = "infineon,cat1-lp-timer-pdl"; + reg = <0x5240d000 0x40>; + interrupts = <55 4>; + status = "disabled"; + }; + + mcwdt1: mcwdt@5240d040 { + compatible = "infineon,cat1-lp-timer-pdl"; + reg = <0x5240d040 0x40>; + interrupts = <0 4>; + status = "disabled"; + }; + + tcpwm0: tcpwm0@52860000 { + reg = <0x52860000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + tcpwm0_0: tcpwm0_0@52860000 { + compatible = "infineon,tcpwm"; + reg = <0x52860000 0x80>; + interrupts = <110 4>; + resolution = <32>; + status = "disabled"; + + pwm0_0: pwm0_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_0: counter0_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_1: tcpwm0_1@52860080 { + compatible = "infineon,tcpwm"; + reg = <0x52860080 0x80>; + interrupts = <111 4>; + resolution = <32>; + status = "disabled"; + + pwm0_1: pwm0_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_1: counter0_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_2: tcpwm0_2@52860100 { + compatible = "infineon,tcpwm"; + reg = <0x52860100 0x80>; + interrupts = <112 4>; + resolution = <32>; + status = "disabled"; + + pwm0_2: pwm0_2 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_2: counter0_2 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_3: tcpwm0_3@52860180 { + compatible = "infineon,tcpwm"; + reg = <0x52860180 0x80>; + interrupts = <113 4>; + resolution = <32>; + status = "disabled"; + + pwm0_3: pwm0_3 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_3: counter0_3 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_4: tcpwm0_4@52860200 { + compatible = "infineon,tcpwm"; + reg = <0x52860200 0x80>; + interrupts = <114 4>; + resolution = <32>; + status = "disabled"; + + pwm0_4: pwm0_4 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_4: counter0_4 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_5: tcpwm0_5@52860280 { + compatible = "infineon,tcpwm"; + reg = <0x52860280 0x80>; + interrupts = <115 4>; + resolution = <32>; + status = "disabled"; + + pwm0_5: pwm0_5 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_5: counter0_5 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_6: tcpwm0_6@52860300 { + compatible = "infineon,tcpwm"; + reg = <0x52860300 0x80>; + interrupts = <116 4>; + resolution = <32>; + status = "disabled"; + + pwm0_6: pwm0_6 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_6: counter0_6 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm0_7: tcpwm0_7@52860380 { + compatible = "infineon,tcpwm"; + reg = <0x52860380 0x80>; + interrupts = <117 4>; + resolution = <32>; + status = "disabled"; + + pwm0_7: pwm0_7 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_7: counter0_7 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + }; + + tcpwm1: tcpwm1@52868000 { + reg = <0x52868000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + tcpwm1_0: tcpwm1_0@52868000 { + compatible = "infineon,tcpwm"; + reg = <0x52868000 0x80>; + interrupts = <118 4>; + resolution = <16>; + status = "disabled"; + + pwm1_0: pwm1_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_0: counter1_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_1: tcpwm1_1@52868080 { + compatible = "infineon,tcpwm"; + reg = <0x52868080 0x80>; + interrupts = <119 4>; + resolution = <16>; + status = "disabled"; + + pwm1_1: pwm1_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_1: counter1_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_2: tcpwm1_2@52868100 { + compatible = "infineon,tcpwm"; + reg = <0x52868100 0x80>; + interrupts = <120 4>; + resolution = <16>; + status = "disabled"; + + pwm1_2: pwm1_2 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_2: counter1_2 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_3: tcpwm1_3@52868180 { + compatible = "infineon,tcpwm"; + reg = <0x52868180 0x80>; + interrupts = <121 4>; + resolution = <16>; + status = "disabled"; + + pwm1_3: pwm1_3 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_3: counter1_3 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_4: tcpwm1_4@52868200 { + compatible = "infineon,tcpwm"; + reg = <0x52868200 0x80>; + interrupts = <122 4>; + resolution = <16>; + status = "disabled"; + + pwm1_4: pwm1_4 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_4: counter1_4 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_5: tcpwm1_5@52868280 { + compatible = "infineon,tcpwm"; + reg = <0x52868280 0x80>; + interrupts = <123 4>; + resolution = <16>; + status = "disabled"; + + pwm1_5: pwm1_5 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_5: counter1_5 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_6: tcpwm1_6@52868300 { + compatible = "infineon,tcpwm"; + reg = <0x52868300 0x80>; + interrupts = <124 4>; + resolution = <16>; + status = "disabled"; + + pwm1_6: pwm1_6 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_6: counter1_6 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_7: tcpwm1_7@52868380 { + compatible = "infineon,tcpwm"; + reg = <0x52868380 0x80>; + interrupts = <125 4>; + resolution = <16>; + status = "disabled"; + + pwm1_7: pwm1_7 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_7: counter1_7 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_8: tcpwm1_8@52868400 { + compatible = "infineon,tcpwm"; + reg = <0x52868400 0x80>; + interrupts = <126 4>; + resolution = <16>; + status = "disabled"; + + pwm1_8: pwm1_8 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_8: counter1_8 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_9: tcpwm1_9@52868480 { + compatible = "infineon,tcpwm"; + reg = <0x52868480 0x80>; + interrupts = <127 4>; + resolution = <16>; + status = "disabled"; + + pwm1_9: pwm1_9 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_9: counter1_9 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_10: tcpwm1_10@52868500 { + compatible = "infineon,tcpwm"; + reg = <0x52868500 0x80>; + interrupts = <128 4>; + resolution = <16>; + status = "disabled"; + + pwm1_10: pwm1_10 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_10: counter1_10 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_11: tcpwm1_11@52868580 { + compatible = "infineon,tcpwm"; + reg = <0x52868580 0x80>; + interrupts = <129 4>; + resolution = <16>; + status = "disabled"; + + pwm1_11: pwm1_11 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_11: counter1_11 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_12: tcpwm1_12@52868600 { + compatible = "infineon,tcpwm"; + reg = <0x52868600 0x80>; + interrupts = <130 4>; + resolution = <16>; + status = "disabled"; + + pwm1_12: pwm1_12 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_12: counter1_12 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_13: tcpwm1_13@52868680 { + compatible = "infineon,tcpwm"; + reg = <0x52868680 0x80>; + interrupts = <131 4>; + resolution = <16>; + status = "disabled"; + + pwm1_13: pwm1_13 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_13: counter1_13 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_14: tcpwm1_14@52868700 { + compatible = "infineon,tcpwm"; + reg = <0x52868700 0x80>; + interrupts = <132 4>; + resolution = <16>; + status = "disabled"; + + pwm1_14: pwm1_14 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_14: counter1_14 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_15: tcpwm1_15@52868780 { + compatible = "infineon,tcpwm"; + reg = <0x52868780 0x80>; + interrupts = <133 4>; + resolution = <16>; + status = "disabled"; + + pwm1_15: pwm1_15 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_15: counter1_15 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_16: tcpwm1_16@52868800 { + compatible = "infineon,tcpwm"; + reg = <0x52868800 0x80>; + interrupts = <134 4>; + resolution = <16>; + status = "disabled"; + + pwm1_16: pwm1_16 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_16: counter1_16 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_17: tcpwm1_17@52868880 { + compatible = "infineon,tcpwm"; + reg = <0x52868880 0x80>; + interrupts = <135 4>; + resolution = <16>; + status = "disabled"; + + pwm1_17: pwm1_17 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_17: counter1_17 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_18: tcpwm1_18@52868900 { + compatible = "infineon,tcpwm"; + reg = <0x52868900 0x80>; + interrupts = <136 4>; + resolution = <16>; + status = "disabled"; + + pwm1_18: pwm1_18 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_18: counter1_18 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_19: tcpwm1_19@52868980 { + compatible = "infineon,tcpwm"; + reg = <0x52868980 0x80>; + interrupts = <137 4>; + resolution = <16>; + status = "disabled"; + + pwm1_19: pwm1_19 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_19: counter1_19 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_20: tcpwm1_20@52868a00 { + compatible = "infineon,tcpwm"; + reg = <0x52868a00 0x80>; + interrupts = <138 4>; + resolution = <16>; + status = "disabled"; + + pwm1_20: pwm1_20 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_20: counter1_20 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_21: tcpwm1_21@52868a80 { + compatible = "infineon,tcpwm"; + reg = <0x52868a80 0x80>; + interrupts = <139 4>; + resolution = <16>; + status = "disabled"; + + pwm1_21: pwm1_21 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_21: counter1_21 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_22: tcpwm1_22@52868b00 { + compatible = "infineon,tcpwm"; + reg = <0x52868b00 0x80>; + interrupts = <140 4>; + resolution = <16>; + status = "disabled"; + + pwm1_22: pwm1_22 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_22: counter1_22 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + + tcpwm1_23: tcpwm1_23@52868b80 { + compatible = "infineon,tcpwm"; + reg = <0x52868b80 0x80>; + interrupts = <141 4>; + resolution = <16>; + status = "disabled"; + + pwm1_23: pwm1_23 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_23: counter1_23 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + }; + }; + + dma0: dw@52270000 { + #dma-cells = <1>; + compatible = "infineon,cat1-dma-pdl"; + reg = <0x52270000 0x10000>; + dma-channels = <16>; + interrupts = <82 4>, /* CH0 */ + <83 4>, /* CH1 */ + <84 4>, /* CH2 */ + <85 4>, /* CH3 */ + <86 4>, /* CH4 */ + <87 4>, /* CH5 */ + <88 4>, /* CH6 */ + <89 4>, /* CH7 */ + <90 4>, /* CH8 */ + <91 4>, /* CH9 */ + <92 4>, /* CH10 */ + <93 4>, /* CH11 */ + <94 4>, /* CH12 */ + <95 4>, /* CH13 */ + <96 4>, /* CH14 */ + <97 4>; /* CH15 */ + status = "disabled"; + }; + + dma1: dw@52280000 { + #dma-cells = <1>; + compatible = "infineon,cat1-dma-pdl"; + reg = <0x52280000 0x10000>; + dma-channels = <16>; + interrupts = <181 4>, /* CH0 */ + <182 4>, /* CH1 */ + <183 4>, /* CH2 */ + <184 4>, /* CH3 */ + <185 4>, /* CH4 */ + <186 4>, /* CH5 */ + <187 4>, /* CH6 */ + <188 4>, /* CH7 */ + <189 4>, /* CH8 */ + <190 4>, /* CH9 */ + <191 4>, /* CH10 */ + <192 4>, /* CH11 */ + <193 4>, /* CH12 */ + <194 4>, /* CH13 */ + <195 4>, /* CH14 */ + <196 4>; /* CH15 */ + status = "disabled"; + }; + + sdhc0: sdhc@54810000 { + compatible = "infineon,cat1-sdhc-sdio"; + reg = <0x54810000 0x2000>; + interrupts = <155 4>, /* SDIO wakeup interrupt for mxsdhc */ + <154 6>; /* Consolidated interrupt for mxsdhc */ + status = "disabled"; + }; + + sdhc1: sdhc@54820000 { + compatible = "infineon,cat1-sdhc-sdio"; + reg = <0x54820000 0x2000>; + interrupts = <157 4>, /* SDIO wakeup interrupt for mxsdhc */ + <156 6>; /* Consolidated interrupt for mxsdhc */ + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/infineon/edge/pse84/system_clocks.dtsi b/dts/arm/infineon/edge/pse84/system_clocks.dtsi new file mode 100644 index 0000000000000..368f9fc82835d --- /dev/null +++ b/dts/arm/infineon/edge/pse84/system_clocks.dtsi @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DIV_8_BIT 00 +#define DIV_16_BIT 01 +#define DIV_16_5_BIT 02 +#define DIV_24_5_BIT 03 + +#include +#include +/ { + /* iho */ + clk_iho: clk_iho { + #clock-cells = <0>; + compatible = "infineon,fixed-clock"; + clock-frequency = <12000000>; + system-clock = ; + status = "okay"; + }; + + /* pilo */ + clk_pilo: clk_pilo { + #clock-cells = <0>; + compatible = "infineon,fixed-clock"; + clock-frequency = <32768>; + system-clock = ; + status = "okay"; + }; + + dpll_hp: dpll_hp { + #clock-cells = <0>; + compatible = "infineon,fixed-clock"; + clock-frequency = <100000000>; + system-clock = ; + status = "disabled"; + }; + + path_mux0: path_mux0 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <0>; + source-path = ; + status = "disabled"; + }; + + path_mux1: path_mux1 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <1>; + source-path = ; + status = "disabled"; + }; + + path_mux2: path_mux2 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <2>; + source-path = ; + status = "disabled"; + }; + + path_mux3: path_mux3 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <3>; + source-path = ; + status = "disabled"; + }; + + path_mux4: path_mux4 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <4>; + source-path = ; + status = "disabled"; + }; + + path_mux5: path_mux5 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&clk_iho>; + system-clock = ; + instance = <5>; + source-path = ; + status = "disabled"; + }; + + clk_hf0: clk_hf0 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <0>; + status = "disabled"; + }; + + clk_hf1: clk_hf1 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <1>; + status = "disabled"; + }; + + clk_hf2: clk_hf2 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <2>; + status = "disabled"; + }; + + clk_hf3: clk_hf3 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <3>; + status = "disabled"; + }; + + clk_hf4: clk_hf4 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <4>; + status = "disabled"; + }; + + clk_hf5: clk_hf5 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <5>; + status = "disabled"; + }; + + clk_hf6: clk_hf6 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <6>; + status = "disabled"; + }; + + clk_hf7: clk_hf7 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <7>; + status = "disabled"; + }; + + clk_hf8: clk_hf8 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <8>; + status = "disabled"; + }; + + clk_hf9: clk_hf9 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <9>; + status = "disabled"; + }; + + clk_hf10: clk_hf10 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <10>; + status = "disabled"; + }; + + clk_hf11: clk_hf11 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <11>; + status = "disabled"; + }; + + clk_hf12: clk_hf12 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <12>; + status = "disabled"; + }; + + clk_hf13: clk_hf13 { + #clock-cells = <0>; + compatible = "infineon,fixed-factor-clock"; + clocks = <&path_mux0>; + clock-div = ; + system-clock = ; + instance = <13>; + status = "disabled"; + }; + + peri0: peri0 { + /* Peripheral clock dividers Group 1 */ + peri0_group1_8bit_0: peri0_group1_8bit_0 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <0>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_8bit_1: peri0_group1_8bit_1 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <1>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_8bit_2: peri0_group1_8bit_2 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <2>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_8bit_3: peri0_group1_8bit_3 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <3>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_8bit_4: peri0_group1_8bit_4 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <4>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16bit_0: peri0_group1_16bit_0 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <0>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16bit_1: peri0_group1_16bit_1 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <1>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16bit_2: peri0_group1_16bit_2 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <2>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16bit_3: peri0_group1_16bit_3 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <3>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16_5bit_0: peri0_group1_16_5bit_0 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <0>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_16_5bit_1: peri0_group1_16_5bit_1 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <1>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_24_5bit_0: peri0_group1_24_5bit_0 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <0>; + clock-div = <1>; + status = "disabled"; + }; + + peri0_group1_24_5bit_1: peri0_group1_24_5bit_1 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 01]; /* inst#, group# */ + div-type = ; + channel = <1>; + clock-div = <1>; + status = "disabled"; + }; + + /* Peripheral clock deviders Group 8 (Use for SCB1) */ + peri0_group8_16bit_0: peri0_group8_16bit_0 { + #clock-cells = <0>; + compatible = "infineon,peri-div"; + peri-group = [00 08]; /* inst#, group# */ + div-type = ; + channel = <0>; + clock-div = <1>; + status = "disabled"; + }; + }; +}; diff --git a/dts/bindings/clock/infineon,fixed-clock.yaml b/dts/bindings/clock/infineon,fixed-clock.yaml index 0c25ef7816909..129d6cb5ab32d 100644 --- a/dts/bindings/clock/infineon,fixed-clock.yaml +++ b/dts/bindings/clock/infineon,fixed-clock.yaml @@ -7,23 +7,13 @@ description: Generic fixed-rate clock provider compatible: "infineon,fixed-clock" -include: [base.yaml, clock-controller.yaml] +include: fixed-clock.yaml properties: - clock-frequency: + system-clock: type: int - description: output clock frequency (Hz) required: true - - clock-block: - type: int - description: Clock HW block number (refer to ifx_cat1_clock_block in clock_control_ifx_cat1.h) - required: true - - clock-instance: - type: int - description: TEMP - required: true - - "#clock-cells": - const: 0 + description: | + The type of clock (refer to include/.../dt-bindings/clock/ifx_clock_source_common.h): + clk_iho : system-clock = + clk_pilo : system-clock = diff --git a/dts/bindings/clock/infineon,fixed-factor-clock.yaml b/dts/bindings/clock/infineon,fixed-factor-clock.yaml index b926f24321d6e..f54045990f337 100644 --- a/dts/bindings/clock/infineon,fixed-factor-clock.yaml +++ b/dts/bindings/clock/infineon,fixed-factor-clock.yaml @@ -7,30 +7,25 @@ description: Generic fixed-rate clock provider compatible: "infineon,fixed-factor-clock" -include: [base.yaml, clock-controller.yaml] +include: fixed-factor-clock.yaml properties: - clocks: - type: phandle-array - description: input clock source - - clock-block: + system-clock: type: int - description: Clock HW block number (refer to ifx_cat1_clock_block in clock_control_ifx_cat1.h) required: true + description: | + The type of clock (refer to include/.../dt-bindings/clock/ifx_clock_source_common.h): + path_mux5 : system-clock = + clk_hf0 : system-clock = - clock-instance: + instance: type: int - description: TEMP required: true - - clock-divider: - type: int - description: TEMP + description: | + Instance of a given clock type. + path_mux5 : instance = <5> + clk_hf0 : instance = <0> source-path: type: int - description: TEMP - - "#clock-cells": - const: 0 + description: Path that indicates source clock. diff --git a/dts/bindings/clock/infineon,cat1-peri-div.yaml b/dts/bindings/clock/infineon,peri-div.yaml similarity index 54% rename from dts/bindings/clock/infineon,cat1-peri-div.yaml rename to dts/bindings/clock/infineon,peri-div.yaml index c6c6e4e9a2a6d..4b55806c0eef7 100644 --- a/dts/bindings/clock/infineon,cat1-peri-div.yaml +++ b/dts/bindings/clock/infineon,peri-div.yaml @@ -1,31 +1,33 @@ -# Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. # # SPDX-License-Identifier: Apache-2.0 -description: infineon cat1 peripheral divider 8bit. +description: infineon peripheral divider -compatible: "infineon,cat1-peri-div" +compatible: "infineon,peri-div" include: [clock-controller.yaml, base.yaml] properties: - clk-dst: + peri-group: type: uint8-array description: | - Clock Connections. PDL uses the target IP to identify the peri group + Peri instance and group of given peripheral divider: + peri0_group1_... : peri-group = [00 01] + peri1_group3_... : peri-group = [01 03] div-type: type: int description: | - Clock divider type. + Programmable clock divider types: DIV_8_BIT, DIV_16_BIT, DIV_16_5_BIT, DIV_24_5_BIT - div-num: + channel: type: int description: | - Programmable clock divider types: DIV_8_BIT, DIV_16_BIT, DIV_16_5_BIT, DIV_24_5_BIT + Channel of given peripheral divider. - div-value: + clock-div: type: int description: | For non-fractional clock dividers (div-type: DIV_8_BIT, DIV_16_BIT) @@ -45,11 +47,19 @@ properties: it divides the clock by 1/32 for each count. To divide the clock by 11/32nds set this value to 11. - scb-block: + resource-type: type: int required: true description: | - SCB device instance peripheral clock is assigned to: - &scb0 : scb-block = <0> - &scb3 : scb-block = <3> - &scb5 : scb-block = <5> + Resource type that the peripheral clock is assigned to: + &scb3 : resource-type = IFX_RSC_SCB + &tcpwm0_0 : resource-type = IFX_RSC_TCPWM + + resource-instance: + type: int + required: true + description: | + Resource instance that the peripheral clock is assigned to: + &scb0 : resource-instance = <0> + &scb3 : resource-instance = <3> + &scb5 : resource-instance = <5> diff --git a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml index d2345bdd677a1..3c9e8965213d8 100644 --- a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml +++ b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml @@ -120,3 +120,12 @@ child-binding: Encodes port/pin and alternate function. required: true type: int + drive-strength: + type: string + enum: + - "full" + - "half" + - "one-fourth" + - "one-eighth" + description: | + Pin output drive strength. diff --git a/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h b/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h index 7b0da7a4c05d7..8726743c492a5 100644 --- a/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h +++ b/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h @@ -10,6 +10,7 @@ #define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03)) +#if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) /* Converts the group/div pair into a unique block number. */ #define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div)) @@ -22,41 +23,25 @@ (gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \ IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \ (gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */ - -enum ifx_cat1_resource { - IFX_CAT1_RSC_ADC, /*!< Analog to digital converter */ - IFX_CAT1_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */ - IFX_CAT1_RSC_BLESS, /*!< Bluetooth communications block */ - IFX_CAT1_RSC_CAN, /*!< CAN communication block */ - IFX_CAT1_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */ - IFX_CAT1_RSC_CLOCK, /*!< Clock */ - IFX_CAT1_RSC_CRYPTO, /*!< Crypto hardware accelerator */ - IFX_CAT1_RSC_DAC, /*!< Digital to analog converter */ - IFX_CAT1_RSC_DMA, /*!< DMA controller */ - IFX_CAT1_RSC_DW, /*!< Datawire DMA controller */ - IFX_CAT1_RSC_ETH, /*!< Ethernet communications block */ - IFX_CAT1_RSC_GPIO, /*!< General purpose I/O pin */ - IFX_CAT1_RSC_I2S, /*!< I2S communications block */ - IFX_CAT1_RSC_I3C, /*!< I3C communications block */ - IFX_CAT1_RSC_KEYSCAN, /*!< KeyScan block */ - IFX_CAT1_RSC_LCD, /*!< Segment LCD controller */ - IFX_CAT1_RSC_LIN, /*!< LIN communications block */ - IFX_CAT1_RSC_LPCOMP, /*!< Low power comparator */ - IFX_CAT1_RSC_LPTIMER, /*!< Low power timer */ - IFX_CAT1_RSC_OPAMP, /*!< Opamp */ - IFX_CAT1_RSC_PDM, /*!< PCM/PDM communications block */ - IFX_CAT1_RSC_PTC, /*!< Programmable Threshold comparator */ - IFX_CAT1_RSC_SMIF, /*!< Quad-SPI communications block */ - IFX_CAT1_RSC_RTC, /*!< Real time clock */ - IFX_CAT1_RSC_SCB, /*!< Serial Communications Block */ - IFX_CAT1_RSC_SDHC, /*!< SD Host Controller */ - IFX_CAT1_RSC_SDIODEV, /*!< SDIO Device Block */ - IFX_CAT1_RSC_TCPWM, /*!< Timer/Counter/PWM block */ - IFX_CAT1_RSC_TDM, /*!< TDM block */ - IFX_CAT1_RSC_UDB, /*!< UDB Array */ - IFX_CAT1_RSC_USB, /*!< USB communication block */ - IFX_CAT1_RSC_INVALID, /*!< Placeholder for invalid type */ -}; +#else +/* Converts the group/div pair into a unique block number. */ +#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \ + (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div)) +#define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR) +#define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \ + ((clock >> 2) - \ + (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR)) + +#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \ + IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \ + IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \ + IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \ + IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \ + IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \ + IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \ + IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \ + IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT) +#endif enum ifx_cat1_clock_block { #if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A) @@ -280,6 +265,94 @@ enum ifx_cat1_clock_block { IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ IFX_CAT1_CLOCK_BLOCK_MEM, /*!< CLK MEM */ IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< CLK Timer */ +#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) + + IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = + CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ + IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT = + CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ + IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT = + CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT + */ + IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT = + CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT + */ + +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9), +#endif +#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11) +#warning "Unhandled PERI0 PCLK number" +#endif + +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6) + IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5), +#endif +#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7) +#warning "Unhandled PERI1 PCLK number" +#endif + + IFX_CAT1_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ + IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ + IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */ + IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ + IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ + + IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ + + IFX_CAT1_CLOCK_BLOCK_DPLL250, /*!< 250MHz Digital Phase-Locked Loop Clock */ + IFX_CAT1_CLOCK_BLOCK_DPLL500, /*!< 500MHz Digital Phase-Locked Loop Clock */ + IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ + + IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ + IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ + IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ + + IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ + IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ + #endif }; @@ -291,8 +364,8 @@ struct ifx_cat1_clock { }; struct ifx_cat1_resource_inst { - enum ifx_cat1_resource type; /* !< The resource block type */ - uint8_t block_num; /* !< The resource block index */ + uint8_t type; /* !< The resource block type */ + uint8_t block_num; /* !< The resource block index */ /** * The channel number, if the resource type defines multiple channels * per block instance. Otherwise, 0 @@ -307,7 +380,7 @@ en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num); static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock) { -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) return Cy_SysClk_PeriPclkEnableDivider( clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel); @@ -322,7 +395,7 @@ static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_de const struct ifx_cat1_clock *_clock, uint32_t div) { -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) return Cy_SysClk_PeriPclkSetDivider( clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div); @@ -338,7 +411,7 @@ ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div_int, uint32_t div_frac) { -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) return Cy_SysClk_PeriPclkSetFracDivider( clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int, div_frac); @@ -353,7 +426,7 @@ ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock) { -#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) +#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE) return Cy_SysClk_PeriPclkAssignDivider( clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel); diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h new file mode 100644 index 0000000000000..057764a7a66bb --- /dev/null +++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_PSE84) +#include "ifx_clock_source_pse8xx.h" +#elif defined(CONFIG_SOC_SERIES_PSC3) +#include "ifx_clock_source_psc3xx.h" +#endif diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h new file mode 100644 index 0000000000000..5e60871f26196 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define CLK_SOURCE_IHO +#define CLK_SOURCE_PILO + +#define IFX_IHO 1 /*!< Internal High Speed Oscillator Input Clock */ +#define IFX_IMO 2 /*!< Internal Main Oscillator Input Clock */ +#define IFX_ECO 3 /*!< External Crystal Oscillator Input Clock */ +#define IFX_EXT 4 /*!< External Input Clock */ +#define IFX_ALTHF 5 /*!< Alternate High Frequency Input Clock */ +#define IFX_ALTLF 6 /*!< Alternate Low Frequency Input Clock */ +#define IFX_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */ +#define IFX_PILO 8 /*!< Precision ILO Input Clock */ +#define IFX_WCO 9 /*!< Watch Crystal Oscillator Input Clock */ +#define IFX_MFO 10 /*!< Medium Frequency Oscillator Clock */ +#define IFX_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */ +#define IFX_FLL 12 /*!< Frequency-Locked Loop Clock */ +#define IFX_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */ +#define IFX_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */ +#define IFX_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */ +#define IFX_LF 16 /*!< Low Frequency Clock */ +#define IFX_MF 17 /*!< Medium Frequency Clock */ +#define IFX_HF 18 /*!< High Frequency Clock */ +#define IFX_PUMP 19 /*!< Analog Pump Clock */ +#define IFX_BAK 20 /*!< Backup Power Domain Clock */ +#define IFX_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */ +#define IFX_PERI 22 /*!< Peripheral Clock Group */ +#define IFX_DPLL250_0 23 /*!< 250MHz Digital Phase-Locked Loop Clock 0 */ +#define IFX_DPLL250_1 24 /*!< 250MHz Digital Phase-Locked Loop Clock 1 */ +#define IFX_DPLL500 25 /*!< 500MHz Digital Phase-Locked Loop Clock */ + +#define IFX_CLK_HF_NO_DIVIDE 0 /**< don't divide clkHf */ +#define IFX_CLK_HF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */ +#define IFX_CLK_HF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */ +#define IFX_CLK_HF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */ +#define IFX_CLK_HF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */ +#define IFX_CLK_HF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */ +#define IFX_CLK_HF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */ +#define IFX_CLK_HF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */ +#define IFX_CLK_HF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */ +#define IFX_CLK_HF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */ +#define IFX_CLK_HF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */ +#define IFX_CLK_HF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */ +#define IFX_CLK_HF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */ +#define IFX_CLK_HF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */ +#define IFX_CLK_HF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */ +#define IFX_CLK_HF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */ +#define IFX_CLK_HF_MAX_DIVIDER /**< Max divider */ + +/* Target resource types for peripheral dividers */ +#define IFX_RSC_ADC 0 /*!< Analog to digital converter */ +#define IFX_RSC_ADCMIC 1 /*!< Analog to digital converter with Analog Mic support */ +#define IFX_RSC_BLESS 2 /*!< Bluetooth communications block */ +#define IFX_RSC_CAN 3 /*!< CAN communication block */ +#define IFX_RSC_CLKPATH 4 /*!< Clock Path. DEPRECATED. */ +#define IFX_RSC_CLOCK 5 /*!< Clock */ +#define IFX_RSC_CRYPTO 6 /*!< Crypto hardware accelerator */ +#define IFX_RSC_DAC 7 /*!< Digital to analog converter */ +#define IFX_RSC_DMA 8 /*!< DMA controller */ +#define IFX_RSC_DW 9 /*!< Datawire DMA controller */ +#define IFX_RSC_ETH 10 /*!< Ethernet communications block */ +#define IFX_RSC_GPIO 11 /*!< General purpose I/O pin */ +#define IFX_RSC_I2S 12 /*!< I2S communications block */ +#define IFX_RSC_I3C 13 /*!< I3C communications block */ +#define IFX_RSC_KEYSCAN 14 /*!< KeyScan block */ +#define IFX_RSC_LCD 15 /*!< Segment LCD controller */ +#define IFX_RSC_LIN 16 /*!< LIN communications block */ +#define IFX_RSC_LPCOMP 17 /*!< Low power comparator */ +#define IFX_RSC_LPTIMER 18 /*!< Low power timer */ +#define IFX_RSC_OPAMP 19 /*!< Opamp */ +#define IFX_RSC_PDM 20 /*!< PCM/PDM communications block */ +#define IFX_RSC_PTC 21 /*!< Programmable Threshold comparator */ +#define IFX_RSC_SMIF 22 /*!< Quad-SPI communications block */ +#define IFX_RSC_RTC 23 /*!< Real time clock */ +#define IFX_RSC_SCB 24 /*!< Serial Communications Block */ +#define IFX_RSC_SDHC 25 /*!< SD Host Controller */ +#define IFX_RSC_SDIODEV 26 /*!< SDIO Device Block */ +#define IFX_RSC_TCPWM 27 /*!< Timer/Counter/PWM block */ +#define IFX_RSC_TDM 28 /*!< TDM block */ +#define IFX_RSC_UDB 29 /*!< UDB Array */ +#define IFX_RSC_USB 30 /*!< USB communication block */ +#define IFX_RSC_INVALID 31 /*!< Placeholder for invalid type */ diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_def.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_def.h deleted file mode 100644 index 01f8ed0375091..0000000000000 --- a/include/zephyr/dt-bindings/clock/ifx_clock_source_def.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define CLK_SOURCE_IHO -#define CLK_SOURCE_PILO - -#define IFX_CAT1_CLOCK_BLOCK_IHO 1 /*!< Internal High Speed Oscillator Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_IMO 2 /*!< Internal Main Oscillator Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ECO 3 /*!< External Crystal Oscillator Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_EXT 4 /*!< External Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ALTHF 5 /*!< Alternate High Frequency Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ALTLF 6 /*!< Alternate Low Frequency Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_PILO 8 /*!< Precision ILO Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_WCO 9 /*!< Watch Crystal Oscillator Input Clock */ -#define IFX_CAT1_CLOCK_BLOCK_MFO 10 /*!< Medium Frequency Oscillator Clock */ - -#define IFX_CAT1_CLOCK_BLOCK_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */ - -#define IFX_CAT1_CLOCK_BLOCK_FLL 12 /*!< Frequency-Locked Loop Clock */ -#define IFX_CAT1_CLOCK_BLOCK_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */ -#define IFX_CAT1_CLOCK_BLOCK_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */ - -#define IFX_CAT1_CLOCK_BLOCK_LF 16 /*!< Low Frequency Clock */ -#define IFX_CAT1_CLOCK_BLOCK_MF 17 /*!< Medium Frequency Clock */ -#define IFX_CAT1_CLOCK_BLOCK_HF 18 /*!< High Frequency Clock */ - -#define IFX_CAT1_CLOCK_BLOCK_PUMP 19 /*!< Analog Pump Clock */ -#define IFX_CAT1_CLOCK_BLOCK_BAK 20 /*!< Backup Power Domain Clock */ -#define IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */ -#define IFX_CAT1_CLOCK_BLOCK_PERI 22 /*!< Peripheral Clock Group */ - -#define IFX_CAT1_CLKHF_NO_DIVIDE 0 /**< don't divide clkHf */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */ -#define IFX_CAT1_CLKHF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */ -#define IFX_CAT1_CLKHF_MAX_DIVIDER /**< Max divider */ - -#define IFX_CAT1_CLKPATH_IN_IMO 0 /**< Select the IMO as the output of the path mux */ -#define IFX_CAT1_CLKPATH_IN_EXT 1 /**< Select the EXT as the output of the path mux */ -#define IFX_CAT1_CLKPATH_IN_ECO 2 /**< Select the ECO as the output of the path mux */ -#define IFX_CAT1_CLKPATH_IN_ALTHF 3 /**< Select the ALTHF as the output of the path mux */ -/* Select the DSI MUX output as the output of the path mux */ -#define IFX_CAT1_CLKPATH_IN_DSIMUX 4 -#define IFX_CAT1_CLKPATH_IN_LPECO 5 /**< Select the LPECO as the output of the path mux */ -#define IFX_CAT1_CLKPATH_IN_IHO 6 /**< Select the IHO as the output of the path mux */ -/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \ - * Make sure the DSI clock sources are available on used device. \ - */ -#define IFX_CAT1_CLKPATH_IN_DSI 0x100 -/**< Select the ILO (16) as the output of the DSI mux and path mux */ -#define IFX_CAT1_CLKPATH_IN_ILO 0x110 -/**< Select the WCO (17) as the output of the DSI mux and path mux */ -#define IFX_CAT1_CLKPATH_IN_WCO 0x111 -/**< Select the ALTLF (18) as the output of the DSI mux and path mux. \ - * Make sure the ALTLF clock sources in available on used device. \ - */ -#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112 -/**< Select the PILO (19) as the output of the DSI mux and path mux. \ - * Make sure the PILO clock sources in available on used device. \ - */ -#define IFX_CAT1_CLKPATH_IN_PILO 0x113 -/**< Select the ILO1 (20) as the output of the DSI mux and path mux */ -#define IFX_CAT1_CLKPATH_IN_ILO1 0x114 diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h new file mode 100644 index 0000000000000..7fec3735c5110 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define IFX_CAT1_CLKPATH_IN_IMO 0 /**< Select the IMO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_EXT 1 /**< Select the EXT as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_ECO 2 /**< Select the ECO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_ALTHF 3 /**< Select the ALTHF as the output of the path mux */ +/* Select the DSI MUX output as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_DSIMUX 4 +#define IFX_CAT1_CLKPATH_IN_LPECO 5 /**< Select the LPECO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_IHO 6 /**< Select the IHO as the output of the path mux */ +/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \ + * Make sure the DSI clock sources are available on used device. \ + */ +#define IFX_CAT1_CLKPATH_IN_DSI 0x100 +/**< Select the ILO (16) as the output of the DSI mux and path mux */ +#define IFX_CAT1_CLKPATH_IN_ILO 0x110 +/**< Select the WCO (17) as the output of the DSI mux and path mux */ +#define IFX_CAT1_CLKPATH_IN_WCO 0x111 +/**< Select the ALTLF (18) as the output of the DSI mux and path mux. \ + * Make sure the ALTLF clock sources in available on used device. \ + */ +#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112 +/**< Select the PILO (19) as the output of the DSI mux and path mux. \ + * Make sure the PILO clock sources in available on used device. \ + */ +#define IFX_CAT1_CLKPATH_IN_PILO 0x113 +/**< Select the ILO1 (20) as the output of the DSI mux and path mux */ +#define IFX_CAT1_CLKPATH_IN_ILO1 0x114 diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h new file mode 100644 index 0000000000000..94cccf671668f --- /dev/null +++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Select the IHO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_IHO 0 + +/* Select the EXT as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_EXT 1 + +/* Select the ECO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_ECO 2 + +/* Select the IMO as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_IMO 3 + +/* Select the ALTHF0 as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_ALTHF0 4 + +/* Select the ALTHF1 as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_ALTHF1 5 + +/* Select the DSI MUX output as the output of the path mux */ +#define IFX_CAT1_CLKPATH_IN_DSIMUX 7 + +/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. + * Make sure the DSI clock sources are available on used device. + */ +#define IFX_CAT1_CLKPATH_IN_DSI 0x100 + +/* Select the ILO (16) as the output of the DSI mux and path mux */ +#define IFX_CAT1_CLKPATH_IN_ILO 0x110 + +/* Select the WCO (17) as the output of the DSI mux and path mux */ +#define IFX_CAT1_CLKPATH_IN_WCO 0x111 + +/* Select the ALTLF (18) as the output of the DSI mux and path mux. + * Make sure the ALTLF clock sources in available on used device. + */ +#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112 + +/* Select the PILO (19) as the output of the DSI mux and path mux. + * Make sure the PILO clock sources in available on used device. + */ +#define IFX_CAT1_CLKPATH_IN_PILO 0x113 diff --git a/modules/hal_infineon/CMakeLists.txt b/modules/hal_infineon/CMakeLists.txt index 09cb72b0d8a3c..dbdc0c890d062 100644 --- a/modules/hal_infineon/CMakeLists.txt +++ b/modules/hal_infineon/CMakeLists.txt @@ -2,28 +2,42 @@ # Copyright (c) 2022 Cypress Semiconductor Corporation. # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_HAS_XMCLIB OR CONFIG_SOC_FAMILY_PSOC6_LEGACY OR CONFIG_SOC_FAMILY_INFINEON_CAT1) +if(CONFIG_HAS_XMCLIB + OR CONFIG_SOC_FAMILY_PSOC6_LEGACY + OR CONFIG_SOC_FAMILY_INFINEON_CAT1 + OR CONFIG_SOC_FAMILY_INFINEON_EDGE) + zephyr_library_named(modules_hal_infineon) zephyr_library_compile_options($) + + zephyr_include_directories(.) endif() ## Add PDL sources for XMC devices -if (CONFIG_HAS_XMCLIB) +if(CONFIG_HAS_XMCLIB) add_subdirectory(${ZEPHYR_HAL_INFINEON_MODULE_DIR}/XMCLib XMCLib) endif() -if (CONFIG_SOC_FAMILY_INFINEON_CAT1 OR CONFIG_SOC_FAMILY_PSOC6_LEGACY) +if(CONFIG_SOC_FAMILY_INFINEON_CAT1 + OR CONFIG_SOC_FAMILY_PSOC6_LEGACY + OR CONFIG_SOC_FAMILY_INFINEON_EDGE) + ## Add core-lib sources for CAT1 devices add_subdirectory(core-lib) - ## Add mtb-pdl-cat1 sources for CAT1 devices - add_subdirectory(mtb-pdl-cat1) + if(NOT CONFIG_SOC_FAMILY_INFINEON_EDGE) + ## Add mtb-pdl-cat1 sources for CAT1 devices + add_subdirectory(mtb-pdl-cat1) + endif() ## Add mtb-templates-cat1 sources for CAT1 devices add_subdirectory(mtb-template-cat1) endif() -if (CONFIG_SOC_FAMILY_INFINEON_CAT1 AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY) +if(CONFIG_SOC_FAMILY_INFINEON_CAT1 + AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY + AND NOT CONFIG_SOC_FAMILY_INFINEON_EDGE) + ## Add mtb-hal-cat1 sources for CAT1 devices add_subdirectory(mtb-hal-cat1) @@ -39,8 +53,25 @@ if (CONFIG_SOC_FAMILY_INFINEON_CAT1 AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY) endif() +if(CONFIG_SOC_FAMILY_INFINEON_EDGE) + if(CONFIG_CPU_CORTEX_M33 AND CONFIG_TRUSTED_EXECUTION_SECURE) + # Use secure device in cy_device_headers + zephyr_library_compile_definitions(COMPONENT_SECURE_DEVICE) + endif() + + zephyr_library_compile_definitions_ifdef(CONFIG_CPU_CORTEX_M33 COMPONENT_CM33) + zephyr_library_compile_definitions_ifdef(CONFIG_CPU_CORTEX_M33 CORE_NAME_CM33_0) + zephyr_library_compile_definitions_ifdef(CONFIG_CPU_CORTEX_M55 COMPONENT_CM55) + zephyr_library_compile_definitions_ifdef(CONFIG_CPU_CORTEX_M55 CORE_NAME_CM55_0) + + add_subdirectory(mtb-srf) + add_subdirectory(serial-memory) + add_subdirectory(zephyr-ifx-cycfg) + add_subdirectory(mtb-dsl-pse8xxgp) +endif() + ## Add Wi-Fi assets for AIROC devices -if (CONFIG_WIFI_AIROC) +if(CONFIG_WIFI_AIROC) add_subdirectory(wifi-host-driver) ## Add core-lib sources for CAT1 devices @@ -51,10 +82,10 @@ if (CONFIG_WIFI_AIROC) endif() ## Add BT assets for AIROC devices -if (CONFIG_BT_AIROC) +if(CONFIG_BT_AIROC) add_subdirectory(btstack-integration) endif() -if (CONFIG_BT_PSOC6_BLESS) -add_subdirectory(bless) +if(CONFIG_BT_PSOC6_BLESS) + add_subdirectory(bless) endif() diff --git a/modules/hal_infineon/Kconfig b/modules/hal_infineon/Kconfig index eba1a49e24e73..2b54d74265bd4 100644 --- a/modules/hal_infineon/Kconfig +++ b/modules/hal_infineon/Kconfig @@ -7,7 +7,7 @@ config ZEPHYR_HAL_INFINEON_MODULE config ZEPHYR_HAL_INFINEON_MODULE_BLOBS bool -if SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY +if SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_INFINEON_EDGE || SOC_FAMILY_PSOC6_LEGACY config USE_INFINEON_ADC bool @@ -24,6 +24,11 @@ config USE_INFINEON_I2C help Enable Inter-Integrated Circuit Interface (I2C) HAL module driver for Infineon devices +config USE_INFINEON_I3C + bool + help + Enable Improved Inter-Integrated Circuit Interface (I3C) HAL module driver for Infineon devices + config USE_INFINEON_RTC bool help @@ -89,7 +94,7 @@ config USE_INFINEON_SMIF help Enable SMIF HAL driver for Infineon devices -endif # SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY +endif # SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_INFINEON_EDGE || SOC_FAMILY_PSOC6_LEGACY config USE_INFINEON_ABSTRACTION_RTOS bool "Abstraction RTOS component (Zephyr support)" diff --git a/modules/hal_infineon/infineon_kconfig.h b/modules/hal_infineon/infineon_kconfig.h new file mode 100644 index 0000000000000..fb4d3655a4636 --- /dev/null +++ b/modules/hal_infineon/infineon_kconfig.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef INFINEON_KCONFIG_H__ +#define INFINEON_KCONFIG_H__ + +/* + * These are mappings of Kconfig options enabling Infineon SOCs and particular + * peripheral instances to the corresponding symbols used inside of Infineon code. + */ + +#if defined(CONFIG_SOC_PSE846GPS2DBZC4A) + +#define PSE846GPS2DBZC4A + +#if defined(CONFIG_CPU_CORTEX_M33) + +#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) +#define COMPONENT_SECURE_DEVICE +#endif /* CONFIG_TRUSTED_EXECUTION_SECURE */ + +#define COMPONENT_CM33 +#define CORE_NAME_CM33_0 + +#elif defined(CONFIG_CPU_CORTEX_M55) + +#define COMPONENT_CM55 +#define CORE_NAME_CM55_0 + +#endif /* CONFIG_CPU_CORTEXT_M33*/ +#endif /* CONFIG_SOC_PSE846GPS2DBZC4A*/ + +#endif /* INFINEON_KCONFIG_H__*/ diff --git a/modules/hal_infineon/mtb-dsl-pse8xxgp/CMakeLists.txt b/modules/hal_infineon/mtb-dsl-pse8xxgp/CMakeLists.txt new file mode 100644 index 0000000000000..54352b9df0ec4 --- /dev/null +++ b/modules/hal_infineon/mtb-dsl-pse8xxgp/CMakeLists.txt @@ -0,0 +1,103 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-dsl-pse8xxgp/pdl) +set(hal_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-dsl-pse8xxgp/hal) + +set(pdl_drv_dir ${pdl_dir}/drivers) +set(pdl_dev_edge_dir ${pdl_dir}/devices) + +# Generate PDL specific SOC defines +zephyr_library_compile_definitions($) + +# Add mtb-pdl-cat1 +zephyr_include_directories(${pdl_drv_dir}/include) +zephyr_include_directories(${pdl_drv_dir}/third_party/ethernet/include) + +zephyr_include_directories(${pdl_dev_edge_dir}/include) +zephyr_include_directories(${pdl_dev_edge_dir}/include/ip) +zephyr_library_sources(${pdl_dev_edge_dir}/source/cy_device.c) + +if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "armclang") + zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_ARM/cy_syslib_ext.S) +else() + zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S) +endif() + +# Peripheral drivers +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${pdl_drv_dir}/source/cy_scb_i2c.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I3C ${pdl_drv_dir}/source/cy_i3c.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${pdl_drv_dir}/source/cy_mcwdt.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${pdl_drv_dir}/source/cy_tcpwm_pwm.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC ${pdl_drv_dir}/source/cy_rtc.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO ${pdl_drv_dir}/source/cy_sd_host.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI ${pdl_drv_dir}/source/cy_scb_spi.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER ${pdl_drv_dir}/source/cy_tcpwm_counter.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${pdl_drv_dir}/source/cy_scb_uart.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT ${pdl_drv_dir}/source/cy_wdt.c) + +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${pdl_drv_dir}/source/cy_systrimm.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${pdl_drv_dir}/source/cy_rram.c) + +if(CONFIG_USE_INFINEON_TRNG) + zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto.c) + zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto_core_trng_v1.c) + zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto_core_trng_v2.c) +endif() + +if(CONFIG_USE_INFINEON_UART OR CONFIG_USE_INFINEON_I2C OR CONFIG_USE_INFINEON_SPI) + zephyr_library_sources(${pdl_drv_dir}/source/cy_scb_common.c) +endif() + +if(CONFIG_USE_INFINEON_DMA OR CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF) + zephyr_library_sources(${pdl_drv_dir}/source/cy_dma.c) + zephyr_library_sources(${pdl_drv_dir}/source/cy_dmac.c) +endif() + +zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_v4.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_syspm_v4.c LOCATION RAM) + +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif.c LOCATION RAM) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_sfdp.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_sfdp.c LOCATION RAM) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_memslot.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_memslot.c LOCATION RAM) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_hb_flash.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_hb_flash.c LOCATION RAM) + +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_memnum.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_memnum.c LOCATION RAM) + +zephyr_library_sources(${pdl_drv_dir}/source/cy_syslib.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_syslib.c LOCATION RAM) + +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog_sar.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog_ac.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog_ctb.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog_ptc.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_autanalog_dac.c) + +# Common part +zephyr_library_sources(${pdl_drv_dir}/source/cy_gpio.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_drv.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_pipe.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_sema.c) + +zephyr_library_sources(${pdl_drv_dir}/source/cy_sysclk_v2.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_mpc.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_ppc.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_pdcm.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_ppu.c) +zephyr_library_sources(${pdl_drv_dir}/source/ppu_v1.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_smif.c) + +zephyr_library_sources(${pdl_drv_dir}/source/cy_trigmux.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_wdt.c) +zephyr_library_sources(${pdl_drv_dir}/source/cy_tcpwm_pwm.c) + +zephyr_include_directories(${hal_dir}/include) +zephyr_library_sources(${hal_dir}/source/mtb_hal_clock.c) diff --git a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt index 2e92cc1e24021..bbe29ceda3085 100644 --- a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt +++ b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt @@ -1,13 +1,13 @@ -# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. # # SPDX-License-Identifier: Apache-2.0 -set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1) -set(pdl_drv_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/drivers) -set(pdl_dev_cat1a_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1A) -set(pdl_dev_cat1b_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1B) -set(pdl_dev_cat1c_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1C) +set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1) +set(pdl_drv_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/drivers) +set(pdl_dev_cat1a_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1A) +set(pdl_dev_cat1b_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1B) +set(pdl_dev_cat1c_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1C) # Generate PDL specific SOC defines diff --git a/modules/hal_infineon/mtb-srf/CMakeLists.txt b/modules/hal_infineon/mtb-srf/CMakeLists.txt new file mode 100644 index 0000000000000..760fd74cf9d4d --- /dev/null +++ b/modules/hal_infineon/mtb-srf/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +set(mtb_srf_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-srf) + +zephyr_include_directories(${mtb_srf_dir}/include) +zephyr_include_directories(${mtb_srf_dir}/include/COMPONENT_NON_SECURE_DEVICE) +zephyr_include_directories(${mtb_srf_dir}/export) diff --git a/modules/hal_infineon/mtb-template-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-template-cat1/CMakeLists.txt index 87c0a74486107..08f203f053db3 100644 --- a/modules/hal_infineon/mtb-template-cat1/CMakeLists.txt +++ b/modules/hal_infineon/mtb-template-cat1/CMakeLists.txt @@ -3,11 +3,18 @@ # # SPDX-License-Identifier: Apache-2.0 -set(template_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-template-cat1) +if(CONFIG_SOC_FAMILY_INFINEON_EDGE) + set(template_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-template-pse8xxgp) +else() + set(template_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-template-cat1) +endif() + set(cat1a_dir ${template_dir}/files/templates/cat1a) set(cat1b_dir ${template_dir}/files/templates/cat1b) set(cat1c_dir ${template_dir}/files/templates/cat1c) +set(edge_dir ${template_dir}/files) +# Add support for PSOC6 (CAT1A) if(CONFIG_SOC_FAMILY_INFINEON_CAT1A) zephyr_include_directories(${cat1a_dir}/COMPONENT_MTB) zephyr_include_directories(${cat1a_dir}/COMPONENT_MTB/COMPONENT_CM33/HEADER_FILES) @@ -33,3 +40,21 @@ if(CONFIG_SOC_FAMILY_INFINEON_CAT1C) zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS ${cat1c_dir}/COMPONENT_MTB/COMPONENT_CM0P/system_cm0plus.c) zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M7 ${cat1c_dir}/COMPONENT_MTB/COMPONENT_CM7/system_cm7.c) endif() + +# Add support for psoce84 (EDGE) +if(CONFIG_SOC_FAMILY_INFINEON_EDGE) + zephyr_include_directories(${edge_dir}) + zephyr_include_directories(${edge_dir}/devices/include) + + zephyr_library_sources(${edge_dir}/system_edge.c) + if(CONFIG_BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M33) + zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M33 + ${edge_dir}/COMPONENT_CM33/COMPONENT_SECURE_DEVICE/s_system_pse84.c) + zephyr_include_directories(${edge_dir}/COMPONENT_CM33/COMPONENT_SECURE_DEVICE) + else() + zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M33 + ${edge_dir}/COMPONENT_CM33/COMPONENT_NON_SECURE_DEVICE/ns_system_pse84.c) + endif() + zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M55 + ${edge_dir}/COMPONENT_CM55/COMPONENT_NON_SECURE_DEVICE/ns_system_pse84.c) +endif() diff --git a/modules/hal_infineon/serial-memory/CMakeLists.txt b/modules/hal_infineon/serial-memory/CMakeLists.txt new file mode 100644 index 0000000000000..33cf50e772477 --- /dev/null +++ b/modules/hal_infineon/serial-memory/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +set(serial_memory_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/serial-memory) + +zephyr_include_directories(${serial_memory_dir}/include) +zephyr_include_directories(${serial_memory_dir}/source) + +zephyr_library_sources(${serial_memory_dir}/source/mtb_serial_memory.c) diff --git a/modules/hal_infineon/zephyr-ifx-cycfg/CMakeLists.txt b/modules/hal_infineon/zephyr-ifx-cycfg/CMakeLists.txt new file mode 100644 index 0000000000000..7884d5d65e52c --- /dev/null +++ b/modules/hal_infineon/zephyr-ifx-cycfg/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_FAMILY_INFINEON_EDGE) + set(zephyr_ifx_cycfg_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/zephyr-ifx-cycfg/kit_pse84_eval) + + zephyr_include_directories(${zephyr_ifx_cycfg_dir}) + zephyr_library_sources(${zephyr_ifx_cycfg_dir}/cycfg_qspi_memslot.c) +endif() diff --git a/soc/infineon/edge/CMakeLists.txt b/soc/infineon/edge/CMakeLists.txt new file mode 100644 index 0000000000000..96d2c55060d85 --- /dev/null +++ b/soc/infineon/edge/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(pse84) diff --git a/soc/infineon/edge/Kconfig b/soc/infineon/edge/Kconfig new file mode 100644 index 0000000000000..be2003f484b9d --- /dev/null +++ b/soc/infineon/edge/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INFINEON_EDGE + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INFINEON_EDGE diff --git a/soc/infineon/edge/Kconfig.defconfig b/soc/infineon/edge/Kconfig.defconfig new file mode 100644 index 0000000000000..5b5c384641893 --- /dev/null +++ b/soc/infineon/edge/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# PSOC CAT1B Configuration + +if SOC_FAMILY_INFINEON_EDGE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_INFINEON_EDGE diff --git a/soc/infineon/edge/Kconfig.soc b/soc/infineon/edge/Kconfig.soc new file mode 100644 index 0000000000000..e4b496529ac41 --- /dev/null +++ b/soc/infineon/edge/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Family definitions +config SOC_FAMILY_INFINEON_EDGE + bool + +config SOC_FAMILY + default "infineon_edge" if SOC_FAMILY_INFINEON_EDGE + +# MPNs definitions +rsource "*/Kconfig.soc" diff --git a/soc/infineon/edge/common/CMakeLists.txt b/soc/infineon/edge/common/CMakeLists.txt new file mode 100644 index 0000000000000..4a6459f1607af --- /dev/null +++ b/soc/infineon/edge/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/infineon/edge/common/pinctrl_soc.h b/soc/infineon/edge/common/pinctrl_soc.h new file mode 100644 index 0000000000000..339bae9c7e11b --- /dev/null +++ b/soc/infineon/edge/common/pinctrl_soc.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Infineon CAT1 SoC specific helpers for pinctrl driver. + */ + +#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +/** + * Bit definition in PINMUX field + */ +#define SOC_PINMUX_PORT_POS (0) +#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS) +#define SOC_PINMUX_PIN_POS (8) +#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS) +#define SOC_PINMUX_HSIOM_FUNC_POS (16) +#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS) +#define SOC_PINMUX_SIGNAL_POS (24) +#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS) + +/* + * Pin flags/attributes + */ +#define SOC_GPIO_DEFAULT (0) +#define SOC_GPIO_FLAGS_POS (0) +#define SOC_GPIO_FLAGS_MASK (0x1FF << SOC_GPIO_FLAGS_POS) +#define SOC_GPIO_PULLUP_POS (0) +#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS) +#define SOC_GPIO_PULLDOWN_POS (1) +#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS) +#define SOC_GPIO_OPENDRAIN_POS (2) +#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS) +#define SOC_GPIO_OPENSOURCE_POS (3) +#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS) + +/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */ +#define SOC_GPIO_PUSHPULL_POS (4) +#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS) + +/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */ +#define SOC_GPIO_INPUTENABLE_POS (5) +#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS) + +#define SOC_GPIO_HIGHZ_POS (6) +#define SOC_GPIO_HIGHZ (1 << SOC_GPIO_HIGHZ_POS) + +#define SOC_GPIO_DRIVESTRENGTH_POS (6) +#define SOC_GPIO_DRIVESTRENGTH (0x7 << SOC_GPIO_DRIVESTRENGTH_POS) + +/** Type for CAT1 Soc pin. */ +typedef struct { + /** + * Pinmux settings (port, pin and function). + * [0..7] - Port nunder + * [8..15] - Pin number + * [16..23]- HSIOM function + */ + uint32_t pinmux; + + /** Pin configuration (bias, drive and slew rate). */ + uint32_t pincfg; +} pinctrl_soc_pin_t; + +#define CAT1_PINMUX_GET_PORT_NUM(pinmux) (((pinmux) & SOC_PINMUX_PORT_MASK) >> SOC_PINMUX_PORT_POS) +#define CAT1_PINMUX_GET_PIN_NUM(pinmux) (((pinmux) & SOC_PINMUX_PIN_MASK) >> SOC_PINMUX_PIN_POS) +#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) \ + (((pinmux) & SOC_PINMUX_HSIOM_MASK) >> SOC_PINMUX_HSIOM_FUNC_POS) + +/** + * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. + * @param node_id Node identifier. + */ +#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux) + +/** + * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t. + * @param node_id Node identifier. + */ +#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \ + (DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \ + (DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \ + (DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \ + (DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \ + (DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \ + (DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS)) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, CY_GPIO_DRIVE_1_2) \ + << SOC_GPIO_DRIVESTRENGTH_POS) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param state_prop State property name. + * @param idx State property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + {.pinmux = Z_PINCTRL_CAT1_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))}, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)} + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/infineon/edge/pse84/CMakeLists.txt b/soc/infineon/edge/pse84/CMakeLists.txt new file mode 100644 index 0000000000000..53d390c49b263 --- /dev/null +++ b/soc/infineon/edge/pse84/CMakeLists.txt @@ -0,0 +1,63 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_CPU_CORTEX_M33 AND CONFIG_TRUSTED_EXECUTION_SECURE) + zephyr_sources(soc_pse84_m33_s.c) + + zephyr_sources(security_config/pse84_s_mpc.c) + zephyr_sources(security_config/pse84_s_protection.c) + zephyr_sources(security_config/pse84_s_system.c) + zephyr_sources(security_config/pse84_s_sau.c) + + find_program(EDGEPROTECTTOOLS edgeprotecttools OPTIONAL) + + if(${EDGEPROTECTTOOLS} STREQUAL "EDGEPROTECTTOOLS-NOTFOUND") + message(WARNING "Could not find edgeprotecttools. + This will result in a nonfunctional secure cm33. + Please consult index.rst for kit_pse84_eval board.") + else() + message("-- Found edgeprotecttools: ${EDGEPROTECTTOOLS}") + + set(unsigned_hex ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.hex) + set(signed_hex ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.signed.hex) + dt_nodelabel(m33s_header NODELABEL "m33s_header") + dt_reg_addr(header_addr PATH ${m33s_header}) + dt_reg_size(header_size PATH ${m33s_header}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND edgeprotecttools image-metadata --image ${unsigned_hex} --output ${signed_hex} + --erased-val 0xff --hex-addr ${header_addr} --header-size ${header_size} + ) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts ${signed_hex}) + endif() +else() + zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M55 soc_pse84_m55.c) +endif() + +zephyr_include_directories(security_config) +zephyr_sources(security_config/pse84_boot.c) + +if(CONFIG_BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55 AND CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS) + zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M55 mpu_regions.c) +endif() + +zephyr_include_directories(.) + +if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "armclang") + zephyr_library_sources(cy_syslib_ext.S) +endif() + +# Add sections +if(CONFIG_BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M33) + zephyr_linker_sources(SECTIONS shared_mem_sec.ld) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +else() + zephyr_linker_sources(SECTIONS shared_mem.ld) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/edge/pse84/linker_exclude_syslib.ld CACHE INTERNAL "") +endif() + +zephyr_linker_sources_ifdef(CONFIG_CPU_CORTEX_M33 RWDATA rwdata.ld) +zephyr_linker_sources_ifdef(CONFIG_CPU_CORTEX_M55 RWDATA rwdata.ld) diff --git a/soc/infineon/edge/pse84/Kconfig b/soc/infineon/edge/pse84/Kconfig new file mode 100644 index 0000000000000..ac14e87ac2960 --- /dev/null +++ b/soc/infineon/edge/pse84/Kconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PSE84 + select ARM + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_HAS_ARM_MPU + select BUILD_OUTPUT_HEX + select BUILD_OUTPUT_BIN + select DYNAMIC_INTERRUPTS + select SOC_EARLY_INIT_HOOK + +config SOC_SERIES_PSE84_M33 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select ARM_TRUSTZONE_M + select ARCH_HAS_TRUSTED_EXECUTION + +config SOC_SERIES_PSE84_M55 + select CPU_CORTEX_M55 + +config SOC_SERIES_PSE84_M33 + select SOC_LATE_INIT_HOOK + +if SOC_SERIES_PSE84_M33 + +config SOC_PSE84_M55_ENABLE + bool "pse84 m55 core is enabled during setup" + help + This option enables the m55 core on pse84, by m33 core. + +endif # SOC_SERIES_PSE84_M33 diff --git a/soc/infineon/edge/pse84/Kconfig.defconfig b/soc/infineon/edge/pse84/Kconfig.defconfig new file mode 100644 index 0000000000000..b4c6e91416258 --- /dev/null +++ b/soc/infineon/edge/pse84/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSE84 based MCU default configuration + +if SOC_SERIES_PSE84 + +config CORTEX_M_SYSTICK + default y + +choice NULL_POINTER_EXCEPTION_DETECTION + default NULL_POINTER_EXCEPTION_DETECTION_NONE +endchoice + +config NUM_IRQS + default 197 if CPU_CORTEX_M33 + default 174 if CPU_CORTEX_M55 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CPU_CORTEX_M33 + default $(dt_node_int_prop_int,/cpus/cpu@1,clock-frequency) if CPU_CORTEX_M55 + +config BUILD_OUTPUT_ADJUST_LMA + depends on XIP + depends on CPU_CORTEX_M33 + default "0x60000000 - $(dt_node_reg_addr_hex,$(dt_nodelabel_path,flash0))" + +endif # SOC_SERIES_PSE84 diff --git a/soc/infineon/edge/pse84/Kconfig.soc b/soc/infineon/edge/pse84/Kconfig.soc new file mode 100644 index 0000000000000..ed91c48c850f5 --- /dev/null +++ b/soc/infineon/edge/pse84/Kconfig.soc @@ -0,0 +1,1048 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSE84 series MCUs +config SOC_SERIES_PSE84 + bool + +config SOC_SERIES_PSE84_M33 + bool + +config SOC_SERIES_PSE84_M55 + bool + +config SOC_SERIES + default "pse84" if SOC_SERIES_PSE84 + +config SOC_DIE_PSE8XXGP + bool + select SOC_FAMILY_INFINEON_EDGE + +config SOC_DIE_PSE8XXGO + bool + select SOC_FAMILY_INFINEON_EDGE + +config SOC_DIE_PSE8XXGM + bool + select SOC_FAMILY_INFINEON_EDGE + +# SOC Packages for Infineon PSE84 series MCUs +config SOC_PACKAGE_PSE84_LQFP_144 + bool + +config SOC_PACKAGE_PSE84_BGA_220 + bool + +config SOC_PACKAGE_PSE84_EWLB_235 + bool + +config SOC_PACKAGE_PSE84_WLB_154 + bool + +# Infineon PSE84 series MPNs +config SOC_PSE846GPS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS4DBZC4B + +config SOC_PSE846GPS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS4DBZC4B + +config SOC_PSE846GPS4DBZC4A + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS4DBZC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS4DBZC4A + +config SOC_PSE846GPS4DBZC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS4DBZC4A + +config SOC_PSE846GPS2DBZC4A + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS2DBZC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS2DBZC4A + +config SOC_PSE846GPS2DBZC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS2DBZC4A + +config SOC_PSE846GOS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE846GOS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GOS4DBZC4B + +config SOC_PSE846GOS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GOS4DBZC4B + +config SOC_PSE846GOS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE846GOS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GOS2DBZC4B + +config SOC_PSE846GOS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GOS2DBZC4B + +config SOC_PSE845GPS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS4DFNC4B + +config SOC_PSE845GPS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS4DFNC4B + +config SOC_PSE845GPS4DFMC4B + bool + select SOC_PACKAGE_PSE84_EWLB_235 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS4DFMC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS4DFMC4B + +config SOC_PSE845GPS4DFMC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS4DFMC4B + +config SOC_PSE845GPS2DFNC4A + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS2DFNC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS2DFNC4A + +config SOC_PSE845GPS2DFNC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS2DFNC4A + +config SOC_PSE845GPS2DFMC4A + bool + select SOC_PACKAGE_PSE84_EWLB_235 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS2DFMC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS2DFMC4A + +config SOC_PSE845GPS2DFMC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS2DFMC4A + +config SOC_PSE845GOS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE845GOS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GOS4DFNC4B + +config SOC_PSE845GOS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GOS4DFNC4B + +config SOC_PSE845GOS4DFMC4B + bool + select SOC_PACKAGE_PSE84_EWLB_235 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE845GOS4DFMC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GOS4DFMC4B + +config SOC_PSE845GOS4DFMC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GOS4DFMC4B + +config SOC_PSE845GOS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE845GOS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GOS2DFNC4B + +config SOC_PSE845GOS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GOS2DFNC4B + +config SOC_PSE845GOS2DFMC4B + bool + select SOC_PACKAGE_PSE84_EWLB_235 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE845GOS2DFMC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GOS2DFMC4B + +config SOC_PSE845GOS2DFMC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GOS2DFMC4B + +config SOC_PSE846GPS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS4DBZQ3B + +config SOC_PSE846GPS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS4DBZQ3B + +config SOC_PSE846GPS2DBZQ3A + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS2DBZQ3A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS2DBZQ3A + +config SOC_PSE846GPS2DBZQ3A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS2DBZQ3A + +config SOC_PSE846GOS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE846GOS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GOS4DBZQ3B + +config SOC_PSE846GOS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GOS4DBZQ3B + +config SOC_PSE846GOS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE846GOS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GOS2DBZQ3B + +config SOC_PSE846GOS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GOS2DBZQ3B + +config SOC_PSE832GOS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE832GOS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE832GOS4DFNC4B + +config SOC_PSE832GOS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE832GOS4DFNC4B + +config SOC_PSE833GOS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE833GOS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GOS4DBZC4B + +config SOC_PSE833GOS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GOS4DBZC4B + +config SOC_PSE832GOS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE832GOS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE832GOS2DFNC4B + +config SOC_PSE832GOS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE832GOS2DFNC4B + +config SOC_PSE833GOS2DBZC4A + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE833GOS2DBZC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GOS2DBZC4A + +config SOC_PSE833GOS2DBZC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GOS2DBZC4A + +config SOC_PSE832GMS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE832GMS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE832GMS4DFNC4B + +config SOC_PSE832GMS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE832GMS4DFNC4B + +config SOC_PSE833GMS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE833GMS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GMS4DBZC4B + +config SOC_PSE833GMS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GMS4DBZC4B + +config SOC_PSE832GMS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE832GMS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE832GMS2DFNC4B + +config SOC_PSE832GMS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE832GMS2DFNC4B + +config SOC_PSE833GMS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE833GMS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GMS2DBZC4B + +config SOC_PSE833GMS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GMS2DBZC4B + +config SOC_PSE833GOS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE833GOS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GOS4DBZQ3B + +config SOC_PSE833GOS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GOS4DBZQ3B + +config SOC_PSE833GOS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE833GOS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GOS2DBZQ3B + +config SOC_PSE833GOS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GOS2DBZQ3B + +config SOC_PSE833GMS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE833GMS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GMS4DBZQ3B + +config SOC_PSE833GMS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GMS4DBZQ3B + +config SOC_PSE833GMS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE833GMS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GMS2DBZQ3B + +config SOC_PSE833GMS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GMS2DBZQ3B + +config SOC_PSE822GOS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE822GOS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE822GOS4DFNC4B + +config SOC_PSE822GOS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE822GOS4DFNC4B + +config SOC_PSE823GOS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE823GOS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GOS4DBZC4B + +config SOC_PSE823GOS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GOS4DBZC4B + +config SOC_PSE822GOS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE822GOS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE822GOS2DFNC4B + +config SOC_PSE822GOS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE822GOS2DFNC4B + +config SOC_PSE823GOS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE823GOS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GOS2DBZC4B + +config SOC_PSE823GOS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GOS2DBZC4B + +config SOC_PSE822GMS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE822GMS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE822GMS4DFNC4B + +config SOC_PSE822GMS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE822GMS4DFNC4B + +config SOC_PSE823GMS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE823GMS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GMS4DBZC4B + +config SOC_PSE823GMS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GMS4DBZC4B + +config SOC_PSE822GMS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE822GMS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE822GMS2DFNC4B + +config SOC_PSE822GMS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE822GMS2DFNC4B + +config SOC_PSE823GMS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE823GMS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GMS2DBZC4B + +config SOC_PSE823GMS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GMS2DBZC4B + +config SOC_PSE823GOS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE823GOS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GOS4DBZQ3B + +config SOC_PSE823GOS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GOS4DBZQ3B + +config SOC_PSE823GOS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE823GOS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GOS2DBZQ3B + +config SOC_PSE823GOS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GOS2DBZQ3B + +config SOC_PSE823GMS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE823GMS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GMS4DBZQ3B + +config SOC_PSE823GMS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GMS4DBZQ3B + +config SOC_PSE823GMS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE823GMS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE823GMS2DBZQ3B + +config SOC_PSE823GMS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE823GMS2DBZQ3B + +config SOC_PSE812GOS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE812GOS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE812GOS4DFNC4B + +config SOC_PSE812GOS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE812GOS4DFNC4B + +config SOC_PSE813GOS4DBZC4A + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE813GOS4DBZC4A_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GOS4DBZC4A + +config SOC_PSE813GOS4DBZC4A_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GOS4DBZC4A + +config SOC_PSE812GOS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE812GOS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE812GOS2DFNC4B + +config SOC_PSE812GOS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE812GOS2DFNC4B + +config SOC_PSE813GOS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE813GOS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GOS2DBZC4B + +config SOC_PSE813GOS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GOS2DBZC4B + +config SOC_PSE812GMS4DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE812GMS4DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE812GMS4DFNC4B + +config SOC_PSE812GMS4DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE812GMS4DFNC4B + +config SOC_PSE813GMS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE813GMS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GMS4DBZC4B + +config SOC_PSE813GMS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GMS4DBZC4B + +config SOC_PSE812GMS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE812GMS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE812GMS2DFNC4B + +config SOC_PSE812GMS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE812GMS2DFNC4B + +config SOC_PSE813GMS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE813GMS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GMS2DBZC4B + +config SOC_PSE813GMS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GMS2DBZC4B + +config SOC_PSE813GOS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE813GOS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GOS4DBZQ3B + +config SOC_PSE813GOS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GOS4DBZQ3B + +config SOC_PSE813GOS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE813GOS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GOS2DBZQ3B + +config SOC_PSE813GOS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GOS2DBZQ3B + +config SOC_PSE813GMS4DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE813GMS4DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GMS4DBZQ3B + +config SOC_PSE813GMS4DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GMS4DBZQ3B + +config SOC_PSE813GMS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGM + +config SOC_PSE813GMS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GMS2DBZQ3B + +config SOC_PSE813GMS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GMS2DBZQ3B + +config SOC_PSE846GPS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS2DBZC4B + +config SOC_PSE846GPS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS2DBZC4B + +config SOC_PSE845GPS2DFNC4B + bool + select SOC_PACKAGE_PSE84_WLB_154 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS2DFNC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS2DFNC4B + +config SOC_PSE845GPS2DFNC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS2DFNC4B + +config SOC_PSE845GPS2DFMC4B + bool + select SOC_PACKAGE_PSE84_EWLB_235 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE845GPS2DFMC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE845GPS2DFMC4B + +config SOC_PSE845GPS2DFMC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE845GPS2DFMC4B + +config SOC_PSE846GPS2DBZQ3B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGP + +config SOC_PSE846GPS2DBZQ3B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE846GPS2DBZQ3B + +config SOC_PSE846GPS2DBZQ3B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE846GPS2DBZQ3B + +config SOC_PSE833GOS2DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE833GOS2DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE833GOS2DBZC4B + +config SOC_PSE833GOS2DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE833GOS2DBZC4B + +config SOC_PSE813GOS4DBZC4B + bool + select SOC_PACKAGE_PSE84_BGA_220 + select SOC_SERIES_PSE84 + select SOC_DIE_PSE8XXGO + +config SOC_PSE813GOS4DBZC4B_M33 + bool + select SOC_SERIES_PSE84_M33 + select SOC_PSE813GOS4DBZC4B + +config SOC_PSE813GOS4DBZC4B_M55 + bool + select SOC_SERIES_PSE84_M55 + select SOC_PSE813GOS4DBZC4B + +config SOC + default "pse846gps4dbzc4b" if SOC_PSE846GPS4DBZC4B + default "pse846gps4dbzc4a" if SOC_PSE846GPS4DBZC4A + default "pse846gps2dbzc4a" if SOC_PSE846GPS2DBZC4A + default "pse846gos4dbzc4b" if SOC_PSE846GOS4DBZC4B + default "pse846gos2dbzc4b" if SOC_PSE846GOS2DBZC4B + default "pse845gps4dfnc4b" if SOC_PSE845GPS4DFNC4B + default "pse845gps4dfmc4b" if SOC_PSE845GPS4DFMC4B + default "pse845gps2dfnc4a" if SOC_PSE845GPS2DFNC4A + default "pse845gps2dfmc4a" if SOC_PSE845GPS2DFMC4A + default "pse845gos4dfnc4b" if SOC_PSE845GOS4DFNC4B + default "pse845gos4dfmc4b" if SOC_PSE845GOS4DFMC4B + default "pse845gos2dfnc4b" if SOC_PSE845GOS2DFNC4B + default "pse845gos2dfmc4b" if SOC_PSE845GOS2DFMC4B + default "pse846gps4dbzq3b" if SOC_PSE846GPS4DBZQ3B + default "pse846gps2dbzq3a" if SOC_PSE846GPS2DBZQ3A + default "pse846gos4dbzq3b" if SOC_PSE846GOS4DBZQ3B + default "pse846gos2dbzq3b" if SOC_PSE846GOS2DBZQ3B + default "pse832gos4dfnc4b" if SOC_PSE832GOS4DFNC4B + default "pse833gos4dbzc4b" if SOC_PSE833GOS4DBZC4B + default "pse832gos2dfnc4b" if SOC_PSE832GOS2DFNC4B + default "pse833gos2dbzc4a" if SOC_PSE833GOS2DBZC4A + default "pse832gms4dfnc4b" if SOC_PSE832GMS4DFNC4B + default "pse833gms4dbzc4b" if SOC_PSE833GMS4DBZC4B + default "pse832gms2dfnc4b" if SOC_PSE832GMS2DFNC4B + default "pse833gms2dbzc4b" if SOC_PSE833GMS2DBZC4B + default "pse833gos4dbzq3b" if SOC_PSE833GOS4DBZQ3B + default "pse833gos2dbzq3b" if SOC_PSE833GOS2DBZQ3B + default "pse833gms4dbzq3b" if SOC_PSE833GMS4DBZQ3B + default "pse833gms2dbzq3b" if SOC_PSE833GMS2DBZQ3B + default "pse822gos4dfnc4b" if SOC_PSE822GOS4DFNC4B + default "pse823gos4dbzc4b" if SOC_PSE823GOS4DBZC4B + default "pse822gos2dfnc4b" if SOC_PSE822GOS2DFNC4B + default "pse823gos2dbzc4b" if SOC_PSE823GOS2DBZC4B + default "pse822gms4dfnc4b" if SOC_PSE822GMS4DFNC4B + default "pse823gms4dbzc4b" if SOC_PSE823GMS4DBZC4B + default "pse822gms2dfnc4b" if SOC_PSE822GMS2DFNC4B + default "pse823gms2dbzc4b" if SOC_PSE823GMS2DBZC4B + default "pse823gos4dbzq3b" if SOC_PSE823GOS4DBZQ3B + default "pse823gos2dbzq3b" if SOC_PSE823GOS2DBZQ3B + default "pse823gms4dbzq3b" if SOC_PSE823GMS4DBZQ3B + default "pse823gms2dbzq3b" if SOC_PSE823GMS2DBZQ3B + default "pse812gos4dfnc4b" if SOC_PSE812GOS4DFNC4B + default "pse813gos4dbzc4a" if SOC_PSE813GOS4DBZC4A + default "pse812gos2dfnc4b" if SOC_PSE812GOS2DFNC4B + default "pse813gos2dbzc4b" if SOC_PSE813GOS2DBZC4B + default "pse812gms4dfnc4b" if SOC_PSE812GMS4DFNC4B + default "pse813gms4dbzc4b" if SOC_PSE813GMS4DBZC4B + default "pse812gms2dfnc4b" if SOC_PSE812GMS2DFNC4B + default "pse813gms2dbzc4b" if SOC_PSE813GMS2DBZC4B + default "pse813gos4dbzq3b" if SOC_PSE813GOS4DBZQ3B + default "pse813gos2dbzq3b" if SOC_PSE813GOS2DBZQ3B + default "pse813gms4dbzq3b" if SOC_PSE813GMS4DBZQ3B + default "pse813gms2dbzq3b" if SOC_PSE813GMS2DBZQ3B + default "pse846gps2dbzc4b" if SOC_PSE846GPS2DBZC4B + default "pse845gps2dfnc4b" if SOC_PSE845GPS2DFNC4B + default "pse845gps2dfmc4b" if SOC_PSE845GPS2DFMC4B + default "pse846gps2dbzq3b" if SOC_PSE846GPS2DBZQ3B + default "pse833gos2dbzc4b" if SOC_PSE833GOS2DBZC4B + default "pse813gos4dbzc4b" if SOC_PSE813GOS4DBZC4B diff --git a/soc/infineon/edge/pse84/cy_syslib_ext.S b/soc/infineon/edge/pse84/cy_syslib_ext.S new file mode 100644 index 0000000000000..02cab76ef625d --- /dev/null +++ b/soc/infineon/edge/pse84/cy_syslib_ext.S @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.section .text,"ax" +.text + + +/******************************************************************************* +* Function Name: Cy_SysLib_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void Cy_SysLib_DelayCycles(uint32_t cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global Cy_SysLib_DelayCycles +.type Cy_SysLib_DelayCycles, %function +Cy_SysLib_DelayCycles: /* cycles bytes */ + + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ Cy_DelayCycles_done /* 2 2 Skip if 0 */ + +Cy_DelayCycles_loop: + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE Cy_DelayCycles_loop /* (1)2 2 2 CPU cycles (if branch is taken) */ + NOP /* 1 2 Loop alignment padding */ + +Cy_DelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ + + +/******************************************************************************* +* Function Name: Cy_SysLib_EnterCriticalSection +****************************************************************************//** +* +* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t Cy_SysLib_EnterCriticalSection(void) */ +.global Cy_SysLib_EnterCriticalSection +.type Cy_SysLib_EnterCriticalSection, %function + +Cy_SysLib_EnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + cpsid i /* Disable interrupts */ + BX lr + + + +/******************************************************************************* +* Function Name: Cy_SysLib_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value +* returned from \ref Cy_SysLib_EnterCriticalSection(). +* +* \param uint8_t savedIntrStatus: +* Saved interrupt status returned by the \ref Cy_SysLib_EnterCriticalSection(). +* +*******************************************************************************/ +/* void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) */ +.global Cy_SysLib_ExitCriticalSection +.type Cy_SysLib_ExitCriticalSection, %function + +Cy_SysLib_ExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr + +.end + + +/* [] END OF FILE */ diff --git a/soc/infineon/edge/pse84/linker.ld b/soc/infineon/edge/pse84/linker.ld new file mode 100644 index 0000000000000..2104c5d43546b --- /dev/null +++ b/soc/infineon/edge/pse84/linker.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * This is the linker script for both standard images and XIP images. + */ + +#include +#include diff --git a/soc/infineon/edge/pse84/linker_exclude_syslib.ld b/soc/infineon/edge/pse84/linker_exclude_syslib.ld new file mode 100644 index 0000000000000..74bde4d978705 --- /dev/null +++ b/soc/infineon/edge/pse84/linker_exclude_syslib.ld @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the Cortex-M platforms. + */ + +#include +#include + +#include +#include +#include + +/* physical address of RAM */ +#ifdef CONFIG_XIP +#define ROMABLE_REGION FLASH +#else +#define ROMABLE_REGION RAM +#endif +#define RAMABLE_REGION RAM + +/* Region of the irq vectors and boot-vector SP/PC */ +#if defined(CONFIG_ROMSTART_RELOCATION_ROM) +#define ROMSTART_ADDR CONFIG_ROMSTART_REGION_ADDRESS +#define ROMSTART_SIZE (CONFIG_ROMSTART_REGION_SIZE * 1K) +#else +#define ROMSTART_REGION ROMABLE_REGION +#endif + +#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0) +#define ROM_ADDR RAM_ADDR +#else +#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET) +#endif + +#if defined(CONFIG_ROM_END_OFFSET) +#define ROM_END_OFFSET CONFIG_ROM_END_OFFSET +#else +#define ROM_END_OFFSET 0 +#endif + +#if CONFIG_FLASH_LOAD_SIZE > 0 +#define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET) +#else +#define ROM_SIZE (CONFIG_FLASH_SIZE * 1024 - CONFIG_FLASH_LOAD_OFFSET - ROM_END_OFFSET) +#endif + +#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) +#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS + +#if defined(CONFIG_CUSTOM_SECTION_ALIGN) +_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE; +#else +/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE + * to make linker section alignment comply with MPU granularity. + */ +#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE) +_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE; +#else +/* If building without MPU support, use default 4-byte alignment. */ +_region_min_align = 4; +#endif +#endif + +#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT) +#define MPU_ALIGN(region_size) \ + . = ALIGN(_region_min_align); \ + . = ALIGN( 1 << LOG2CEIL(region_size)) +#else +#define MPU_ALIGN(region_size) \ + . = ALIGN(_region_min_align) +#endif + +#include + +MEMORY + { +#if defined(CONFIG_ROMSTART_RELOCATION_ROM) + ROMSTART_REGION (rx) : ORIGIN = ROMSTART_ADDR, LENGTH = ROMSTART_SIZE +#endif + FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE + RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE +#if defined(CONFIG_LINKER_DEVNULL_MEMORY) + DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE +#endif + LINKER_DT_REGIONS() + /* Used by and documented in include/linker/intlist.ld */ + IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K + } + +ENTRY(CONFIG_KERNEL_ENTRY) + +SECTIONS + { + +#include + +#ifdef CONFIG_LLEXT +#include +#endif + + /* + * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose', + * before text section. + */ + /DISCARD/ : + { + *(.plt) + } + + /DISCARD/ : + { + *(.iplt) + } + + GROUP_START(ROMABLE_REGION) + + __rom_region_start = ROM_ADDR; + + SECTION_PROLOGUE(rom_start,,) + { + +/* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_START ...). This typically contains the vector + * table and debug information. + */ +#include + + } GROUP_LINK_IN(ROMSTART_REGION) + +#ifdef CONFIG_CODE_DATA_RELOCATION + +#include + +#endif /* CONFIG_CODE_DATA_RELOCATION */ + + SECTION_PROLOGUE(_TEXT_SECTION_NAME,,) + { + __text_region_start = .; + +#include + + // *(.text) + *(EXCLUDE_FILE(cy_syslib_ext.S.obj) .text) + *(".text.*") + *(".TEXT.*") + *(.gnu.linkonce.t.*) + + /* + * These are here according to 'arm-zephyr-elf-ld --verbose', + * after .gnu.linkonce.t.* + */ + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + . = ALIGN(4); + + } GROUP_LINK_IN(ROMABLE_REGION) + + __text_region_end = .; + +#if defined (CONFIG_CPP) || defined(CONFIG_RUST) + SECTION_PROLOGUE(.ARM.extab,,) + { + /* + * .ARM.extab section containing exception unwinding information. + */ + *(.ARM.extab* .gnu.linkonce.armextab.*) + } GROUP_LINK_IN(ROMABLE_REGION) +#endif + + SECTION_PROLOGUE(.ARM.exidx,,) + { + /* + * This section, related to stack and exception unwinding, is placed + * explicitly to prevent it from being shared between multiple regions. + * It must be defined for gcc to support 64-bit math and avoid + * section overlap. + */ + __exidx_start = .; +#if defined (__GCC_LINKER_CMD__) || defined (__LLD_LINKER_CMD__) + *(.ARM.exidx* gnu.linkonce.armexidx.*) +#endif + __exidx_end = .; + } GROUP_LINK_IN(ROMABLE_REGION) + + __rodata_region_start = .; + +#include +/* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. + */ +#include +#include + + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + *(.rodata) + *(".rodata.*") + *(.gnu.linkonce.r.*) + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#include + + /* + * For XIP images, in order to avoid the situation when __data_rom_start + * is 32-bit aligned, but the actual data is placed right after rodata + * section, which may not end exactly at 32-bit border, pad rodata + * section, so __data_rom_start points at data and it is 32-bit aligned. + * + * On non-XIP images this may enlarge image size up to 3 bytes. This + * generally is not an issue, since modern ROM and FLASH memory is + * usually 4k aligned. + */ + . = ALIGN(4); + } GROUP_LINK_IN(ROMABLE_REGION) + +#include + +#if defined(CONFIG_BUILD_ALIGN_LMA) + /* + * Include a padding section here to make sure that the LMA address + * of the sections in the RAMABLE_REGION are aligned with those + * section's VMA alignment requirements. + */ + SECTION_PROLOGUE(padding_section,,) + { + __rodata_region_end = .; + MPU_ALIGN(__rodata_region_end - ADDR(rom_start)); + } GROUP_LINK_IN(ROMABLE_REGION) +#else + __rodata_region_end = .; + MPU_ALIGN(__rodata_region_end - ADDR(rom_start)); +#endif + __rom_region_end = __rom_region_start + . - ADDR(rom_start); + + GROUP_END(ROMABLE_REGION) + + /* + * These are here according to 'arm-zephyr-elf-ld --verbose', + * before data section. + */ + /DISCARD/ : { + *(.got.plt) + *(.igot.plt) + *(.got) + *(.igot) + } + + GROUP_START(RAMABLE_REGION) + +#if ROM_ADDR != RAM_ADDR + . = RAM_ADDR; +#endif + + /* Align the start of image RAM with the + * minimum granularity required by MPU. + */ + . = ALIGN(_region_min_align); + _image_ram_start = .; + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#if defined(CONFIG_USERSPACE) +#define APP_SHARED_ALIGN . = ALIGN(_region_min_align); +#define SMEM_PARTITION_ALIGN MPU_ALIGN + +#include + + _app_smem_size = _app_smem_end - _app_smem_start; + _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); +#endif /* CONFIG_USERSPACE */ + + GROUP_START(DATA_REGION) + + SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) + { + __data_region_start = .; + __data_start = .; + *(.data) + *(".data.*") + *(".kernel.*") + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#ifdef CONFIG_CODE_DATA_RELOCATION +#include +#endif + __data_end = .; + + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + __data_size = __data_end - __data_start; + __data_load_start = LOADADDR(_DATA_SECTION_NAME); + + __data_region_load_start = LOADADDR(_DATA_SECTION_NAME); + +#include +#include + +#include + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + + __data_region_end = .; + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) +GROUP_START(ITCM) + + SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4)) + { + __itcm_start = .; + *(.itcm) + *(".itcm.*") + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. */ +#include + + __itcm_end = .; + } GROUP_LINK_IN(ITCM AT> ROMABLE_REGION) + + __itcm_size = __itcm_end - __itcm_start; + __itcm_load_start = LOADADDR(_ITCM_SECTION_NAME); + +GROUP_END(ITCM) +#endif + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) +GROUP_START(DTCM) + + SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4)) + { + __dtcm_start = .; + __dtcm_bss_start = .; + *(.dtcm_bss) + *(".dtcm_bss.*") + __dtcm_bss_end = .; + } GROUP_LINK_IN(DTCM) + + SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4)) + { + __dtcm_noinit_start = .; + *(.dtcm_noinit) + *(".dtcm_noinit.*") + __dtcm_noinit_end = .; + } GROUP_LINK_IN(DTCM) + + SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4)) + { + __dtcm_data_start = .; + *(.dtcm_data) + *(".dtcm_data.*") + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. */ +#include + + __dtcm_data_end = .; + } GROUP_LINK_IN(DTCM AT> ROMABLE_REGION) + + __dtcm_end = .; + + __dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME); + +GROUP_END(DTCM) +#endif + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#include + + /DISCARD/ : { *(.note.GNU-stack) } + + SECTION_PROLOGUE(.ARM.attributes, 0,) + { + KEEP(*(.ARM.attributes)) + KEEP(*(.gnu.attributes)) + } + +/* Output section descriptions are needed for these sections to suppress + * warnings when "--orphan-handling=warn" is set for lld. + */ +#if defined(CONFIG_LLVM_USE_LLD) + SECTION_PROLOGUE(.symtab, 0,) { *(.symtab) } + SECTION_PROLOGUE(.strtab, 0,) { *(.strtab) } + SECTION_PROLOGUE(.shstrtab, 0,) { *(.shstrtab) } +#endif + + /* Sections generated from 'zephyr,memory-region' nodes */ + LINKER_DT_SECTIONS() + +/* Must be last in romable region */ +SECTION_PROLOGUE(.last_section,,) +{ + /* .last_section contains a fixed word to ensure location counter and actual + * rom region data usage match when CONFIG_LINKER_LAST_SECTION_ID=y. */ + KEEP(*(.last_section)) +} GROUP_LINK_IN(ROMABLE_REGION) + +/* To provide the image size as a const expression, + * calculate this value here. */ +_flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start; + + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + /* + * For performance, BSS section is assumed to be 4 byte aligned and + * a multiple of 4 bytes + */ + . = ALIGN(4); + __bss_start = .; + __kernel_ram_start = .; + + *(.bss) + *(".bss.*") + *(COMMON) + *(".kernel_bss.*") + +#ifdef CONFIG_CODE_DATA_RELOCATION +#include +#endif + + /* + * As memory is cleared in words only, it is simpler to ensure the BSS + * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes. + */ + __bss_end = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +#include + + /* Define linker symbols */ + + __kernel_ram_end = RAM_ADDR + RAM_SIZE; + __kernel_ram_size = __kernel_ram_end - __kernel_ram_start; + +#include + + GROUP_END(RAMABLE_REGION) + + } diff --git a/soc/infineon/edge/pse84/mpu_regions.c b/soc/infineon/edge/pse84/mpu_regions.c new file mode 100644 index 0000000000000..137245c4b30f7 --- /dev/null +++ b/soc/infineon/edge/pse84/mpu_regions.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* We are expected to give *CONFIG_SIZE* in KB, but REGION_ATTR + * expects bytes, so we multiply by 1024 to convert. + */ +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)), + + MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS, + REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)), + +#if DT_NODE_EXISTS(DT_NODELABEL(itcm)) + MPU_REGION_ENTRY( + "ITCM", DT_REG_ADDR(DT_NODELABEL(itcm)), + REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)), DT_REG_SIZE(DT_NODELABEL(itcm)))), +#endif + +#if DT_NODE_EXISTS(DT_NODELABEL(dtcm)) + MPU_REGION_ENTRY( + "DTCM", DT_REG_ADDR(DT_NODELABEL(dtcm)), + REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)), DT_REG_SIZE(DT_NODELABEL(dtcm)))), +#endif +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/infineon/edge/pse84/rwdata.ld b/soc/infineon/edge/pse84/rwdata.ld new file mode 100644 index 0000000000000..cde66b1c56399 --- /dev/null +++ b/soc/infineon/edge/pse84/rwdata.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +KEEP(*(.cy_ramfunc)) +KEEP(*(.cy_socmem_data)) +KEEP(*(.cy_itcm)) +*cy_syslib_ext.S.obj(.text*) diff --git a/soc/infineon/edge/pse84/security_config/pse84_boot.c b/soc/infineon/edge/pse84/security_config/pse84_boot.c new file mode 100644 index 0000000000000..5026fc25136ab --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_boot.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pse84_boot.h" + +#if defined(CONFIG_SOC_PSE84_M55_ENABLE) +void ifx_pse84_cm55_startup(void) +{ + /* SAU Init */ + cy_sau_init(); + + /* Setup System Control Block */ + SysCtrlBlk_Setup(); + /* Setup NS NVIC interrupts */ + NVIC_NS_Setup(); + +#if defined(__FPU_USED) && (__FPU_USED == 1U) && defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + /* FPU initialization */ + initFPU(); +#endif + + /* Enable global interrupts */ + __enable_irq(); + + /* Enables PD1 power domain */ + Cy_System_EnablePD1(); + + /* Enables APP_MMIO_TCM memory for CM55 core */ + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_CM55_TCM_512K_PERI_NR, CY_MMIO_CM55_TCM_512K_GROUP_NR, + CY_MMIO_CM55_TCM_512K_SLAVE_NR, + CY_MMIO_CM55_TCM_512K_CLK_HF_NR); + + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF0_PERI_NR, CY_MMIO_SMIF0_GROUP_NR, + CY_MMIO_SMIF0_SLAVE_NR, CY_MMIO_SMIF0_CLK_HF_NR); + + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF01_PERI_NR, CY_MMIO_SMIF01_GROUP_NR, + CY_MMIO_SMIF01_SLAVE_NR, CY_MMIO_SMIF01_CLK_HF_NR); + + /* Enable SOCMEM */ + Cy_SysEnableSOCMEM(true); + + /* Configure MPC for NS */ + cy_mpc_init(); + + /* Reduce deepsleep wakeup time in hardware */ + cy_pd_pdcm_clear_dependency(CY_PD_PDCM_APPCPUSS, CY_PD_PDCM_SYSCPU); + + /* Clear SYSCPU and APPCPU power domain dependency set by boot code */ + cy_pd_pdcm_clear_dependency(CY_PD_PDCM_APPCPU, CY_PD_PDCM_SYSCPU); + + /* Enable CM55 */ + Cy_SysEnableCM55(MXCM55, DT_REG_ADDR(DT_NODELABEL(m55_xip)), CM55_BOOT_WAIT_TIME_USEC); + + /* System Domain Idle Power Mode Configuration */ + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); + + /* SoCMEM Idle Power Mode Configuration */ + Cy_SysPm_SetSOCMEMDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); + + /* Configure PPC for NS*/ + cy_ppc0_init(); + cy_ppc1_init(); + + sys_clock_disable(); + + for (;;) { + } +} +#endif diff --git a/soc/infineon/edge/pse84/security_config/pse84_boot.h b/soc/infineon/edge/pse84/security_config/pse84_boot.h new file mode 100644 index 0000000000000..0b7e09b983f2c --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_boot.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include +#include "cy_pdl.h" + +#if defined(CONFIG_SOC_PSE84_M55_ENABLE) +#include "partition_ARMCM33.h" +#include + +#include "pse84_s_system.h" +#include "pse84_s_sau.h" +#include "pse84_s_protection.h" +#include "pse84_s_mpc.h" + +#define CM55_BOOT_WAIT_TIME_USEC (10U) + +void ifx_pse84_cm55_startup(void); +#endif diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_mpc.c b/soc/infineon/edge/pse84/security_config/pse84_s_mpc.c new file mode 100644 index 0000000000000..5f39e3f1bf82e --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_mpc.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pse84_s_mpc.h" +#include "pse84_s_protection.h" +#include + +#if (SMIF_0_MPC_0_REGION_COUNT > 0U) || (SMIF_1_MPC_0_REGION_COUNT > 0U) +#include "cy_smif.h" + +#define SMIF_DESELECT_DELAY (7U) +#define TIMEOUT_1_MS (1000U) +#endif /* (SMIF_0_MPC_0_REGION_COUNT > 0U)|| (SMIF_1_MPC_0_REGION_COUNT > 0U) */ + +/* Value generated through device-configurator settings */ +#define CY_MPC_PC_LAST (8) + +static cy_rslt_t mpc_init(const cy_stc_mpc_regions_t *region, const cy_stc_mpc_rot_cfg_t *config, + uint8_t cfg_count) +{ + /* Will return an error if one occurs at all in the setup process */ + cy_rslt_t return_result = CY_RSLT_SUCCESS; + /* Will track the current iteration for errors */ + cy_rslt_t current_result = CY_RSLT_SUCCESS; + + for (uint32_t cfg_idx = 0; cfg_idx < cfg_count; ++cfg_idx) { + /* Call the configuration function for each region and config */ + current_result = Cy_Mpc_ConfigRotMpcStruct(region->base, region->offset, + region->size, &config[cfg_idx]); + if (CY_RSLT_SUCCESS != current_result) { + return_result = current_result; + } + } + + return return_result; +} + +cy_rslt_t cy_mpc_init(void) +{ + /* Will return an error if one occurs at all in the setup process */ + cy_rslt_t return_result = CY_RSLT_SUCCESS; + /* Will track the current iteration for errors */ + cy_rslt_t current_result = CY_RSLT_SUCCESS; + + /* When executing from RRAM, the SMIF must be initialized and enabled to + * hold onto any MPC configurations performed on the SMIF memory regions. + * We can disable them after performing the MPC configurations. + */ +#if (SMIF_0_MPC_0_REGION_COUNT > 0U) + bool is_smif0_uninit = false; + + if (!Cy_SMIF_IsEnabled(SMIF0_CORE)) { + is_smif0_uninit = true; + + cy_stc_smif_context_t smif_core0_context; + + static const cy_stc_smif_config_t smif_0_core0_config = { + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = SMIF_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .enable_internal_dll = false}; + + /* Enable IP with default configuration */ + (void)Cy_SMIF_Init(SMIF0_CORE, &smif_0_core0_config, TIMEOUT_1_MS, + &smif_core0_context); + Cy_SMIF_Enable(SMIF0_CORE, &smif_core0_context); + } +#endif /* (SMIF_0_MPC_0_REGION_COUNT > 0U) */ + +#if (SOCMEM_0_MPC_0_REGION_COUNT > 0U) + /* Enable SOCMEM */ + Cy_SysEnableSOCMEM(true); +#endif /* (SOCMEM_0_MPC_0_REGION_COUNT > 0U) */ + + for (size_t memory_idx = 0; memory_idx < cy_response_mpcs_count; memory_idx++) { + Cy_Mpc_SetViolationResponse(cy_response_mpcs[memory_idx].base, + cy_response_mpcs[memory_idx].response); + } + + for (size_t domain_idx = 0; domain_idx < unified_mpc_domains_count; ++domain_idx) { + const cy_stc_mpc_unified_t *domain = &unified_mpc_domains[domain_idx]; + + for (uint32_t region_idx = 0; region_idx < domain->region_count; ++region_idx) { + const cy_stc_mpc_regions_t *region = &domain->regions[region_idx]; + + /* If using RRAM separate init is required. Refer to MTB secure app. */ + if (region->base != (MPC_Type *)RRAMC0_MPC0) { + /* Check for an empty regions struct */ + if (region->base != NULL) { + current_result = mpc_init(region, &(domain->cfg[0]), + domain->cfg_count); + } + } + + if (CY_RSLT_SUCCESS != current_result) { + return_result = current_result; + } + } + } + +#if (SMIF_0_MPC_0_REGION_COUNT > 0U) + if (is_smif0_uninit) { + /* Disable IP as MPC configuration is complete*/ + Cy_SMIF_Disable(SMIF0_CORE); + } +#endif /* (SMIF_0_MPC_0_REGION_COUNT > 0U) */ + + return return_result; +} diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_mpc.h b/soc/infineon/edge/pse84/security_config/pse84_s_mpc.h new file mode 100644 index 0000000000000..8b86e85f13b31 --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_mpc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef pse84_s_mpc_h +#define pse84_s_mpc_h +#include +#include + +#include +#include "cy_device.h" +#include "cy_mpc.h" + +cy_rslt_t cy_mpc_init(void); + +#endif /* #ifndef pse84_s_mpc_h */ diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_protection.c b/soc/infineon/edge/pse84/security_config/pse84_s_protection.c new file mode 100644 index 0000000000000..f2bb8cca4b0ea --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_protection.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pse84_s_protection.h" + +const cy_stc_mpc_rot_cfg_t m33s_mpc_cfg[] = { + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; + +const cy_stc_mpc_rot_cfg_t m33_mpc_cfg[] = { + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; + +const cy_stc_mpc_rot_cfg_t m55_mpc_cfg[] = { + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; + +const cy_stc_mpc_rot_cfg_t m33nsc_mpc_cfg[] = { + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_SECURE, + .access = CY_MPC_ACCESS_R, + }, +}; + +const cy_stc_mpc_rot_cfg_t m33_m55_mpc_cfg[] = { + { + .pc = CY_MPC_PC_2, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_5, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_6, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, + { + .pc = CY_MPC_PC_7, + .secure = CY_MPC_NON_SECURE, + .access = CY_MPC_ACCESS_RW, + }, +}; + +const cy_stc_mpc_regions_t m33s_mpc_regions[] = { + { + .base = (MPC_Type *)RRAMC0_MPC0, + .offset = 0x00011000, + .size = 0x0004A000, + }, + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00100000, + .size = 0x00200000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00100000, + .size = 0x00200000, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .offset = 0x00001000, + .size = 0x00057000, + }, +}; + +const cy_stc_mpc_regions_t m33_mpc_regions[] = { + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00300000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00300000, + .size = 0x00240000, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .offset = 0x00058000, + .size = 0x00028000, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .offset = 0x00000000, + .size = 0x0003D000, + }, +}; + +const cy_stc_mpc_regions_t m55_mpc_regions[] = { + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .offset = 0x00500000, + .size = 0x00300000, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .offset = 0x00500000, + .size = 0x00300000, + }, + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .offset = 0x00000000, + .size = 0x00040000, + }, +}; + +const cy_stc_mpc_regions_t m33nsc_mpc_regions[] = {0}; + +const cy_stc_mpc_regions_t m33_m55_mpc_regions[] = { + { + .base = (MPC_Type *)RRAMC0_MPC0, + .offset = 0x0005B000, + .size = 0x00008000, + }, + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .offset = 0x00040000, + .size = 0x004C0000, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .offset = 0x0003D000, + .size = 0x00043000, + }, +}; + +const cy_stc_mpc_resp_cfg_t cy_response_mpcs[] = { + { + .base = (MPC_Type *)SOCMEM_SRAM_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)RAMC0_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)RAMC1_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)SMIF0_CACHE_BLOCK_CACHEBLK_AHB_MPC0, + .response = CY_MPC_BUS_ERR, + }, + { + .base = (MPC_Type *)SMIF0_CORE_AXI_MPC0, + .response = CY_MPC_BUS_ERR, + }, +}; + +const size_t cy_response_mpcs_count = sizeof(cy_response_mpcs) / sizeof(cy_stc_mpc_resp_cfg_t); + +const cy_stc_mpc_unified_t unified_mpc_domains[] = { + { + .regions = m33s_mpc_regions, + .region_count = sizeof(m33s_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = m33s_mpc_cfg, + .cfg_count = sizeof(m33s_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = m33_mpc_regions, + .region_count = sizeof(m33_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = m33_mpc_cfg, + .cfg_count = sizeof(m33_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = m55_mpc_regions, + .region_count = sizeof(m55_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = m55_mpc_cfg, + .cfg_count = sizeof(m55_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = m33nsc_mpc_regions, + .region_count = sizeof(m33nsc_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = m33nsc_mpc_cfg, + .cfg_count = sizeof(m33nsc_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, + { + .regions = m33_m55_mpc_regions, + .region_count = sizeof(m33_m55_mpc_regions) / sizeof(cy_stc_mpc_regions_t), + .cfg = m33_m55_mpc_cfg, + .cfg_count = sizeof(m33_m55_mpc_cfg) / sizeof(cy_stc_mpc_rot_cfg_t), + }, +}; + +const size_t unified_mpc_domains_count = sizeof(unified_mpc_domains) / sizeof(cy_stc_mpc_unified_t); + +const cy_stc_ppc_attribute_t cycfg_unused_ppc_cfg = { + .pcMask = 0xFF, + .secAttribute = CY_PPC_NON_SECURE, + .secPrivAttribute = CY_PPC_SEC_NONPRIV, + .nsPrivAttribute = CY_PPC_NON_SEC_NONPRIV, +}; + +cy_rslt_t cy_ppc_unsecure_init(PPC_Type *base, cy_en_prot_region_t start, cy_en_prot_region_t end) +{ + cy_rslt_t ret = Cy_Ppc_InitPpc(base, CY_PPC_BUS_ERR); + + for (cy_en_prot_region_t region = start; ret == CY_PPC_SUCCESS && region <= end; region++) { + /* Not sure why yet, but writing to these two cause a fault. Skip for now... */ + if (region == PROT_PERI1_PPC1_PPC_PPC_SECURE || + region == PROT_PERI1_PPC1_PPC_PPC_NONSECURE) { + continue; + } + + ret = Cy_Ppc_ConfigAttrib(base, region, &cycfg_unused_ppc_cfg); + if (ret == CY_RSLT_SUCCESS) { + ret = Cy_Ppc_SetPcMask(base, region, PPC_PC_MASK_ALL_ACCESS); + } + } + return ret; +} + +cy_rslt_t cy_ppc0_init(void) +{ + return cy_ppc_unsecure_init(PPC0, PROT_PERI0_START, PROT_PERI0_END); +} + +cy_rslt_t cy_ppc1_init(void) +{ + return cy_ppc_unsecure_init(PPC1, PROT_PERI1_START, PROT_PERI1_END); +} diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_protection.h b/soc/infineon/edge/pse84/security_config/pse84_s_protection.h new file mode 100644 index 0000000000000..2dc7bc3a50490 --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_protection.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(pse84_s_protection_h) +#define pse84_s_protection_h + +#include +#include "cy_mpc.h" +#include "pse84_s_system.h" +#include "pse84_s_mpc.h" +#include "cy_ppc.h" + +#include "pse84_s_sau.h" + +#define vres_0_protection_0_ENABLED 1U +#define M33S_ENABLED 1U +#define M33_ENABLED 1U +#define M55_ENABLED 1U +#define M33NSC_ENABLED 1U +#define M33_M55_ENABLED 1U +#define reserved_ENABLED 1U +#define vres_0_protection_0_mpc_0_ENABLED 1U +#define M33S_UNIFIED_MPC_DOMAIN_IDX 0U +#define M33_UNIFIED_MPC_DOMAIN_IDX 1U +#define M55_UNIFIED_MPC_DOMAIN_IDX 2U +#define M33NSC_UNIFIED_MPC_DOMAIN_IDX 3U +#define M33_M55_UNIFIED_MPC_DOMAIN_IDX 4U +#define PPC_PC_MASK_ALL_ACCESS 0xFFU + +extern const cy_stc_mpc_rot_cfg_t m33s_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t m33_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t m55_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t m33nsc_mpc_cfg[]; +extern const cy_stc_mpc_rot_cfg_t m33_m55_mpc_cfg[]; +extern const cy_stc_mpc_regions_t m33s_mpc_regions[]; +extern const cy_stc_mpc_regions_t m33_mpc_regions[]; +extern const cy_stc_mpc_regions_t m55_mpc_regions[]; +extern const cy_stc_mpc_regions_t m33nsc_mpc_regions[]; +extern const cy_stc_mpc_regions_t m33_m55_mpc_regions[]; +extern const cy_stc_mpc_resp_cfg_t cy_response_mpcs[]; +extern const size_t cy_response_mpcs_count; +extern const cy_stc_mpc_unified_t unified_mpc_domains[]; +extern const size_t unified_mpc_domains_count; + +extern const cy_stc_ppc_attribute_t cycfg_unused_ppc_cfg; + +cy_rslt_t cy_ppc0_init(void); +cy_rslt_t cy_ppc1_init(void); + +#endif /* pse84_s_protection_h */ diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_sau.c b/soc/infineon/edge/pse84/security_config/pse84_s_sau.c new file mode 100644 index 0000000000000..d10c510204d9e --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_sau.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pse84_s_sau.h" + +const cy_sau_config_t sau_config[CY_SAU_REGION_CNT] = { + { + .reg_num = 0U, + .base_addr = 0x00000000U, + .size = 0x10000000U, + .end_addr = 0x0FFFFFFFU, + .nsc = false, + }, + { + .reg_num = 1U, + .base_addr = 0x20000000U, + .size = 0x10000000U, + .end_addr = 0x2FFFFFFFU, + .nsc = false, + }, + { + .reg_num = 2U, + .base_addr = 0x40000000U, + .size = 0xc0000000U, + .end_addr = 0xFFFFFFFFU, + .nsc = false, + }, +}; + +void cy_sau_init(void) +{ + SAU->CTRL |= SAU_CTRL_ENABLE_Msk; + for (uint8_t i = 0U; i < CY_SAU_REGION_CNT; i++) { + SAU->RNR = sau_config[i].reg_num; + SAU->RBAR = (sau_config[i].base_addr & SAU_RBAR_BADDR_Msk); + SAU->RLAR = ((sau_config[i].end_addr & SAU_RLAR_LADDR_Msk) | + (sau_config[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | SAU_RLAR_ENABLE_Msk); + } +} diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_sau.h b/soc/infineon/edge/pse84/security_config/pse84_s_sau.h new file mode 100644 index 0000000000000..1960aa732077e --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_sau.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(pse84_s_sau_h) +#define pse84_s_sau_h + +#include +#include "cmsis_compiler.h" +#include "cy_device.h" + +#define CY_SAU_REGION_CNT (3U) +#define CY_SAU_MAX_REGION_CNT (8U) + +typedef struct { + uint8_t reg_num; /* Region number. */ + uint32_t base_addr; /* Base address of SAU region. */ + uint32_t size; /* Size of SAU region. */ + uint32_t end_addr; /* End address of SAU region. */ + bool nsc; /* Is this region Non-Secure Callable? */ +} cy_sau_config_t; + +void cy_sau_init(void); +extern const cy_sau_config_t sau_config[CY_SAU_REGION_CNT]; + +#endif /* #if !defined(pse84_s_sau_h) */ diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_system.c b/soc/infineon/edge/pse84/security_config/pse84_s_system.c new file mode 100644 index 0000000000000..2a3fda3ce1e97 --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_system.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pse84_s_system.h" + +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_REGULATOR_MODE_MIN 0 +#define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_USING_LP 0 +#define CY_CFG_PWR_USING_HP 1 + +const mtb_srf_protection_range_s_t mxrramc_0_mpc_0_srf_range[MXRRAMC_0_MPC_0_REGION_COUNT] = { + { + .start = (void *)0x22011000, + .length = 0x4A000U, + .is_secure = true, + }, + { + .start = (void *)0x2205B000, + .length = 0x8000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t mxsramc_0_mpc_0_srf_range[MXSRAMC_0_MPC_0_REGION_COUNT] = { + { + .start = (void *)0x24001000, + .length = 0x57000U, + .is_secure = true, + }, + { + .start = (void *)0x24058000, + .length = 0x28000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t mxsramc_1_mpc_0_srf_range[MXSRAMC_1_MPC_0_REGION_COUNT] = { + { + .start = (void *)0x24080000, + .length = 0x3D000U, + .is_secure = false, + }, + { + .start = (void *)0x240BD000, + .length = 0x43000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t smif_0_mpc_0_srf_range[SMIF_0_MPC_0_REGION_COUNT] = { + { + .start = (void *)0x60100000, + .length = 0x200000U, + .is_secure = true, + }, + { + .start = (void *)0x60300000, + .length = 0x200000U, + .is_secure = false, + }, + { + .start = (void *)0x60580000, + .length = 0x300000U, + .is_secure = false, + }, + { + .start = (void *)0x60100000, + .length = 0x200000U, + .is_secure = true, + }, + { + .start = (void *)0x60300000, + .length = 0x200000U, + .is_secure = false, + }, + { + .start = (void *)0x60580000, + .length = 0x300000U, + .is_secure = false, + }, +}; +const mtb_srf_protection_range_s_t socmem_0_mpc_0_srf_range[SOCMEM_0_MPC_0_REGION_COUNT] = { + { + .start = (void *)0x26000000, + .length = 0x40000U, + .is_secure = false, + }, + { + .start = (void *)0x26040000, + .length = 0x4C0000U, + .is_secure = false, + }, +}; + +void init_cycfg_power(void) +{ + Cy_SysPm_Init(); + +/* **System Active Power Mode Profile Configuration** */ +#if (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_HP) + Cy_SysPm_SystemEnterHp(); +#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_ULP) + Cy_SysPm_SystemEnterUlp(); +#elif (CY_CFG_PWR_SYS_ACTIVE_PROFILE == CY_CFG_PWR_MODE_LP) + Cy_SysPm_SystemEnterLp(); +#endif /* CY_CFG_PWR_SYS_IDLE_MODE */ + +/* **System Domain Idle Power Mode Configuration** */ +#if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP); +#elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_RAM) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_RAM); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_RAM); +#elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_OFF) + Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_OFF); + Cy_SysPm_SetAppDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_OFF); +#endif /* CY_CFG_PWR_SYS_IDLE_MODE */ + +/* **Power domains Configuration** */ +#if (CY_CFG_PWR_PD1_DOMAIN) +#if defined(CORE_NAME_CM33_0) && defined(CY_PDL_TZ_ENABLED) + /* Enables PD1 power domain */ + Cy_System_EnablePD1(); + /* Enables APP_MMIO_TCM memory for CM55 core */ + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_CM55_TCM_512K_PERI_NR, CY_MMIO_CM55_TCM_512K_GROUP_NR, + CY_MMIO_CM55_TCM_512K_SLAVE_NR, + CY_MMIO_CM55_TCM_512K_CLK_HF_NR); + + /* Clear SYSCPU and APPCPU power domain dependency set by boot code */ + cy_pd_pdcm_clear_dependency(CY_PD_PDCM_APPCPU, CY_PD_PDCM_SYSCPU); + +#endif /* defined(CORE_NAME_CM33_0) && defined(CY_PDL_TZ_ENABLED) */ +#endif /* (CY_CFG_PWR_PD1_DOMAIN) */ +} +void init_cycfg_system(void) +{ +#if defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_PWR_INIT) + init_cycfg_power(); +#endif /* defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_PWR_INIT) */ +} diff --git a/soc/infineon/edge/pse84/security_config/pse84_s_system.h b/soc/infineon/edge/pse84/security_config/pse84_s_system.h new file mode 100644 index 0000000000000..cd8b1f4cda4f4 --- /dev/null +++ b/soc/infineon/edge/pse84/security_config/pse84_s_system.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if !defined(pse84_s_system_h) +#define pse84_s_system_h + +#include +#include "cy_syspm.h" +#include "system_edge.h" +#include "cy_sysclk.h" +#include "cy_syspm_pdcm.h" +#include "pse84_s_mpc.h" + +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_HP 0x03UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 20UL +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_HP +#define CY_CFG_PWR_SYS_ACTIVE_PROFILE CY_CFG_PWR_MODE_HP +#define CY_CFG_PWR_VDDA_MV 1800 +#define CY_CFG_PWR_VDDD_MV 1800 +#define CY_CFG_PWR_VDDIO0_MV 1800 +#define CY_CFG_PWR_VDDIO1_MV 1800 +#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V +#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP +#define CY_CFG_PWR_SRAMLDO_VOLT CY_SYSPM_SRAMLDO_VOLTAGE_0_80V +#define CY_CFG_PWR_PD1_DOMAIN 1 +#define CY_CFG_PWR_PPU_MAIN PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_PD1 PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_SRAM0 PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_SRAM1 PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_SYSCPU PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_APPCPUSS PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_APPCPU PPU_V1_MODE_FULL_RET +#define CY_CFG_PWR_PPU_SOCMEM PPU_V1_MODE_MEM_RET +#define CY_CFG_PWR_PPU_U55 PPU_V1_MODE_ON +#define MXRRAMC_0_MPC_0_REGION_COUNT 4U +#define MXSRAMC_0_MPC_0_REGION_COUNT 3U +#define MXSRAMC_1_MPC_0_REGION_COUNT 2U +#define SMIF_0_MPC_0_REGION_COUNT 6U +#define SMIF_1_MPC_0_REGION_COUNT 0U +#define SOCMEM_0_MPC_0_REGION_COUNT 2U + +extern const mtb_srf_protection_range_s_t mxrramc_0_mpc_0_srf_range[MXRRAMC_0_MPC_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t mxsramc_0_mpc_0_srf_range[MXSRAMC_0_MPC_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t mxsramc_1_mpc_0_srf_range[MXSRAMC_1_MPC_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t smif_0_mpc_0_srf_range[SMIF_0_MPC_0_REGION_COUNT]; +extern const mtb_srf_protection_range_s_t socmem_0_mpc_0_srf_range[SOCMEM_0_MPC_0_REGION_COUNT]; + +void init_cycfg_power(void); +void init_cycfg_system(void); + +#endif /* pse84_s_system_h */ diff --git a/soc/infineon/edge/pse84/shared_mem.ld b/soc/infineon/edge/pse84/shared_mem.ld new file mode 100644 index 0000000000000..d772d49918446 --- /dev/null +++ b/soc/infineon/edge/pse84/shared_mem.ld @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +GROUP_START(SHARED_MEMORY) + + SECTION_PROLOGUE(.cy_sharedmem,(NOLOAD),) + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } GROUP_LINK_IN(SHARED_MEMORY) + +GROUP_END(SHARED_MEMORY) diff --git a/soc/infineon/edge/pse84/shared_mem_sec.ld b/soc/infineon/edge/pse84/shared_mem_sec.ld new file mode 100644 index 0000000000000..635626f5efb10 --- /dev/null +++ b/soc/infineon/edge/pse84/shared_mem_sec.ld @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +GROUP_START(SHARED_MEMORY) + + SECTION_PROLOGUE(.cy_sharedmem,(NOLOAD),) + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } GROUP_LINK_IN(SHARED_MEMORY) + +GROUP_END(SHARED_MEMORY) + +GROUP_START(SHARED_MEMORY_SEC) + + SECTION_PROLOGUE(.cy_sharedmem_sec,(NOLOAD),) + { + . = ALIGN(4); + __sec_ram_start__ = .; + KEEP(*(.cy_sharedmem_sec)) + . = ALIGN(4); + __sec_ram_end__ = .; + } GROUP_LINK_IN(SHARED_MEMORY_SEC) + +GROUP_END(SHARED_MEMORY_SEC) diff --git a/soc/infineon/edge/pse84/soc.h b/soc/infineon/edge/pse84/soc.h new file mode 100644 index 0000000000000..0e3e69b8976d7 --- /dev/null +++ b/soc/infineon/edge/pse84/soc.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Infineon PSOC EDGE84 soc. + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE +#include +#include +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/infineon/edge/pse84/soc_pse84_m33_s.c b/soc/infineon/edge/pse84/soc_pse84_m33_s.c new file mode 100644 index 0000000000000..499238dd6d619 --- /dev/null +++ b/soc/infineon/edge/pse84/soc_pse84_m33_s.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Infineon PSOC EDGE84 soc. + */ + +#include +#include +#include + +#include "soc.h" +#include +#include +#include "cy_pdl.h" + +#include "pse84_boot.h" + +#define CY_IPC_MAX_ENDPOINTS (8UL) + +static void systeminit_enable_clocks(void) +{ + /* Void all return types to suppress compiler warnings about unused return values */ + + /* For enabling SYS_MMIO_3, we need CLK_HF11 to be enabled first */ + (void)Cy_SysClk_ClkHfSetSource(11U, CY_SYSCLK_CLKHF_IN_CLKPATH0); + (void)Cy_SysClk_ClkHfSetDivider(11U, CY_SYSCLK_CLKHF_NO_DIVIDE); + (void)Cy_SysClk_ClkHfEnable(11U); + + /* enable HF3 and HF4 for SMIF */ + (void)Cy_SysClk_ClkHfSetSource(3U, CY_SYSCLK_CLKHF_IN_CLKPATH0); + (void)Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE); + (void)Cy_SysClk_ClkHfEnable(3U); + + (void)Cy_SysClk_ClkHfSetSource(4U, CY_SYSCLK_CLKHF_IN_CLKPATH0); + (void)Cy_SysClk_ClkHfSetDivider(4U, CY_SYSCLK_CLKHF_NO_DIVIDE); + (void)Cy_SysClk_ClkHfEnable(4U); +} + +static void systeminit_enable_peri(void) +{ + /* Void all return types to suppress compiler warnings about unused return values */ + + /* Release reset for all groups IP except group 0 */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_1, CY_SYSCLK_PERI_GROUP_SL_CTL2, + 0x0U); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_2, CY_SYSCLK_PERI_GROUP_SL_CTL2, + 0x0U); + + /* release reset of nnlite */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_4, CY_SYSCLK_PERI_GROUP_SL_CTL2, + 0x0U); + + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_1, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_2, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); + + /* enable nnlite */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_4, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0x1U); + + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_0_GROUP_3, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); + + /* Perform setup for CM33_NS and CM55 */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_2, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0x3U); + + /* Release reset for all groups IP except group 0 */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_1, CY_SYSCLK_PERI_GROUP_SL_CTL2, + 0x0U); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_2, CY_SYSCLK_PERI_GROUP_SL_CTL2, + 0x0U); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_0, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_1, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); + (void)Cy_SysClk_PeriGroupSetSlaveCtl((uint32_t)PERI_1_GROUP_2, CY_SYSCLK_PERI_GROUP_SL_CTL, + 0xFFFFFFFFU); +} + +void soc_early_init_hook(void) +{ + systeminit_enable_clocks(); + systeminit_enable_peri(); + + /* Initializes the system */ + SystemInit(); +} + +void soc_late_init_hook(void) +{ +#if defined(CONFIG_SOC_PSE84_M55_ENABLE) + ifx_pse84_cm55_startup(); +#endif +} diff --git a/soc/infineon/edge/pse84/soc_pse84_m55.c b/soc/infineon/edge/pse84/soc_pse84_m55.c new file mode 100644 index 0000000000000..316d3d3dd409e --- /dev/null +++ b/soc/infineon/edge/pse84/soc_pse84_m55.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Infineon PSOC EDGE84 soc. + */ + +#include +#include +#include + +#include "soc.h" +#include +#include +#include "cy_pdl.h" + +#define CY_IPC_MAX_ENDPOINTS (8UL) + +/** + * Config_noncacheable_region() copied from + * hal_infineon\...\ + * COMPONENT_CM55\COMPONENT_NON_SECURE_DEVICE\ns_start_pse84.c + */ +#define MPU_SRAM1_SHARED_MEM_REG_ID 0x6 +#define MPU_SRAM1_SHARED_MEM_ATTR_IDX 0x6 + +#define CM55_STARTUP_WAIT_MS 25u + +void config_noncacheable_region(void) +{ + ARM_MPU_Disable(); + + /* Program MAIR0 and MAIR1 */ + ARM_MPU_SetMemAttr(MPU_SRAM1_SHARED_MEM_ATTR_IDX, + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + ARM_MPU_SetRegion(MPU_SRAM1_SHARED_MEM_REG_ID, + ARM_MPU_RBAR(SRAM1_NS_SAHB_SHARED_START, ARM_MPU_SH_INNER, 0UL, 1UL, 1UL), + ARM_MPU_RLAR((SRAM1_NS_SAHB_SHARED_START + SRAM1_SHARED_SIZE - 1UL), + MPU_SRAM1_SHARED_MEM_ATTR_IDX)); + + ARM_MPU_Enable(4); +} + +/* + * This function will allow execute from sram region. This is needed only for + * this sample because by default all soc will disable the execute from SRAM. + * An application that requires that the code be executed from SRAM will have + * to configure the region appropriately in arm_mpu_regions.c. + */ +#ifdef CONFIG_ARM_MPU +void disable_mpu_rasr_xn(void) +{ + uint32_t index; + + /* + * Kept the max index as 8(irrespective of soc) because the sram would + * most likely be set at index 2. + */ + for (index = 0U; index < 8; index++) { + MPU->RNR = index; +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + if (MPU->RBAR & MPU_RBAR_XN_Msk) { + MPU->RBAR ^= MPU_RBAR_XN_Msk; + } +#else + if (MPU->RASR & MPU_RASR_XN_Msk) { + MPU->RASR ^= MPU_RASR_XN_Msk; + } +#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */ + } +} +#endif /* CONFIG_ARM_MPU */ + +void soc_early_init_hook(void) +{ + /* Config non-cacheable region */ + config_noncacheable_region(); + +#ifdef CONFIG_ARM_MPU + disable_mpu_rasr_xn(); +#endif /* CONFIG_ARM_MPU */ + + /* Enable Loop and branch info cache */ + __DMB(); + __ISB(); + SCB_EnableICache(); + SCB_EnableDCache(); + + /* Initializes the system */ + SystemInit(); + + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + /* This time is needed for m55 core to wait for the m33 to finish + * configuring peripherals. + */ + Cy_SysLib_Delay(CM55_STARTUP_WAIT_MS); +} + +cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) +{ + return 0; +} diff --git a/soc/infineon/edge/soc.yml b/soc/infineon/edge/soc.yml new file mode 100644 index 0000000000000..5f537af518c2b --- /dev/null +++ b/soc/infineon/edge/soc.yml @@ -0,0 +1,246 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +family: +- name: edge + series: + - name: pse84 + socs: + - name: pse846gps4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps4dbzc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps2dbzc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gos4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gos2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps4dfmc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps2dfnc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps2dfmc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gos4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gos4dfmc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gos2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gos2dfmc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps2dbzq3a + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gos4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gos2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse832gos4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gos4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse832gos2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gos2dbzc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse832gms4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gms4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse832gms2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gms2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gos4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gos2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gms4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gms2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse822gos4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gos4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse822gos2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gos2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse822gms4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gms4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse822gms2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gms2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gos4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gos2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gms4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse823gms2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse812gos4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gos4dbzc4a + cpuclusters: + - name: m33 + - name: m55 + - name: pse812gos2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gos2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse812gms4dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gms4dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse812gms2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gms2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gos4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gos2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gms4dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gms2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps2dfnc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse845gps2dfmc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse846gps2dbzq3b + cpuclusters: + - name: m33 + - name: m55 + - name: pse833gos2dbzc4b + cpuclusters: + - name: m33 + - name: m55 + - name: pse813gos4dbzc4b + cpuclusters: + - name: m33 + - name: m55 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m33.overlay new file mode 100644 index 0000000000000..dd1a0998f9c7a --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m33.overlay @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio_prt15 2 0>; + in-gpios = <&gpio_prt15 3 0>; + }; +}; + +&gpio_prt15 { + status = "okay"; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m55.overlay b/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m55.overlay new file mode 100644 index 0000000000000..dd1a0998f9c7a --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/kit_pse84_eval_pse846gps2dbzc4a_m55.overlay @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio_prt15 2 0>; + in-gpios = <&gpio_prt15 3 0>; + }; +}; + +&gpio_prt15 { + status = "okay"; +}; diff --git a/west.yml b/west.yml index 8ddf3001a042d..0bd6cb3fbc959 100644 --- a/west.yml +++ b/west.yml @@ -185,7 +185,7 @@ manifest: groups: - hal - name: hal_infineon - revision: f78b8f8202db0115dc41aedda6f77dee8985254f + revision: 3ef39bda93a67cf2ef735f1679aee5a103f92275 path: modules/hal/infineon groups: - hal