diff --git a/boards/ruiside/art_pi/Kconfig.art_pi b/boards/ruiside/art_pi/Kconfig.art_pi new file mode 100644 index 0000000000000..333b3fb6b99a1 --- /dev/null +++ b/boards/ruiside/art_pi/Kconfig.art_pi @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Dejiang He <2995560796@qq.com> +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ART_PI + select SOC_STM32H750XX diff --git a/boards/ruiside/art_pi/art_pi.dts b/boards/ruiside/art_pi/art_pi.dts new file mode 100644 index 0000000000000..cfb9d546ce2a3 --- /dev/null +++ b/boards/ruiside/art_pi/art_pi.dts @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2025 Dejiang He <2995560796@qq.com> + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + model = "Ruiside Electronic ART-Pi board"; + compatible = "ruiside,art-pi"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,uart-mcumgr = &uart4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &w25q64_qspi; + zephyr,display = <dc; + zephyr,sdhc = &sdmmc1; + zephyr,udc = &usbotg_fs; + zephyr,code-partition = &slot0_partition; + zephyr,touch = >911; + }; + + sdram1: memory@c0000000 { + compatible = "zephyr,memory-region","mmio-sram"; + device_type = "memory"; + reg = <0xC0000000 0x00600000>; /* Use 6 MB MAX 32MB */ + zephyr,memory-region = "SDRAM1"; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; + }; + + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(8)>; /* 8MB QSPI Flash */ + zephyr,memory-region = "EXTMEM"; + zephyr,memory-attr = ; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_1 { + gpios = <&gpioc 15 GPIO_ACTIVE_LOW>; + label = "USER LED1"; + }; + + blue_led: led_2 { + gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + label = "USER LED2"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &red_led; + led1 = &blue_led; + sw0 = &user_button; + touch = >911; + sdhc0 = &sdmmc1; + sram-ext = &sdram1; + rs232 = &usart6; + rs485 = &uart5; + eth = &mac; + mdio = &mdio; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&pll { + div-m = <5>; /* 25/5 */ + mul-n = <192>; /* 5*192=960 */ + div-p = <2>; /* 960/2=480MHz */ + div-q = <4>; /* 960/4=240MHz */ + div-r = <4>; /* 960/4=240MHz */ + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll2 { + div-m = <5>; /* 25/5 */ + mul-n = <160>; /* 5*160=800 */ + div-p = <4>; /* 800/4=200MHz */ + div-q = <4>; /* 800/4=200MHz */ + div-r = <4>; /* 800/4=200MHz */ + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll3 { + div-m = <5>; /* 25/5 */ + mul-n = <100>; /* 5*100=500 */ + div-p = <2>; /* 500/2=250MHz */ + div-q = <20>; /* 500/20=25MHz */ + div-r = <20>; /* 500/20=25MHz */ + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; /* 25/5*192/2 = 480 */ + clock-frequency = ; + d1cpre = <1>; /* 480/1 = 480MHz CPU Clocks */ + hpre = <2>; /* 480/2 = 240MHz */ + d1ppre = <2>; /* 240/2 = 120MHz APB3 Clocks */ + d2ppre1 = <2>; /* 240/2 = 120MHz APB1 Clocks */ + d2ppre2 = <2>; /* 240/2 = 120MHz APB2 Clocks */ + d3ppre = <2>; /* 240/2 = 120MHz APB4 Clocks */ +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Flash has 128KB sector size */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pi9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; + label = "debug"; +}; + +&uart5 { + pinctrl-0 = <&uart5_tx_pb13 &uart5_rx_pb12>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; + label = "rs485"; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; + label = "rs232"; +}; + +&sdmmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 &sdmmc1_d2_pc10 + &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + clocks = <&rcc STM32_CLOCK(AHB3, 16)>, + <&rcc STM32_SRC_PLL2_R SDMMC_SEL(0)>; + bus-width = <4>; + cd-gpios = <&gpiod 5 (GPIO_PULL_UP|GPIO_ACTIVE_HIGH)>; + disk-name = "SD"; + resets; + reset-names = "sdmmc1_reset"; + clk-div = <4>; +}; + +<dc { + pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2 + <dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6 + <dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10 + <dc_g4_pj11 <dc_g5_pk0 <dc_g6_pk1 <dc_g7_pk2 + <dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15 + <dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6 + <dc_hsync_pi12 <dc_vsync_pi13 <dc_de_pk7 <dc_clk_pi14>; + pinctrl-names = "default"; + bl-ctrl-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + ext-sdram = <&sdram1>; + status = "okay"; + clocks = <&rcc STM32_CLOCK(APB3, 3)>,<&rcc STM32_SRC_PLL3_R NO_SEL>; + width = <800>; + height = <480>; + pixel-format = ; + def-back-color-red = <0X00>; + def-back-color-green = <0X00>; + def-back-color-blue = <0X00>; + + display-timings { + compatible = "zephyr,panel-timing"; + de-active = <1>; + pixelclk-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + hsync-len = <4>; + hback-porch = <8>; + hfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + vfront-porch = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + + gt911: touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + alt-addr = <0x14>; + irq-gpios = <&gpiog 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&quadspi { + pinctrl-0 = <&quadspi_bk1_io0_pf8 &quadspi_bk1_io1_pf9 &quadspi_bk1_io2_pf7 + &quadspi_bk1_io3_pf6 &quadspi_clk_pf10 &quadspi_bk1_ncs_pg6>; + pinctrl-names = "default"; + status = "okay"; + + w25q64_qspi: qspi-nor-flash@0 { + compatible = "st,stm32-qspi-nor"; + reg = <0>; + size = ; /* 64Mbit */ + qspi-max-frequency = <100000000>; + cs-high-time = <2>; + status = "okay"; + spi-bus-width = <4>; + writeoc = "PP_1_4_4"; + reset-cmd; + reset-cmd-wait = <2000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(2048)>; /* 2MB */ + }; + + slot1_partition: partition@200000 { + label = "image-1"; + reg = <0x00200000 DT_SIZE_K(2048)>; /* 2MB */ + }; + + storage_partition: partition@400000 { + label = "storage"; + reg = <0x00400000 DT_SIZE_K(4096)>; /* 4MB */ + }; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pg9 &spi1_mosi_pb5>; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; + + w25q128_spi: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + size = ; /* 128Mbit */ + status = "okay"; + jedec-id = [ef 40 18]; + has-dpd; + t-enter-dpd = <3500>; + t-exit-dpd = <3500>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spi_storage_partition: partition@0 { + label = "storage_spi"; + reg = <0x00000000 DT_SIZE_M(16)>; /* 16MB */ + }; + }; + }; +}; + +&fmc { + pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_ph5 + &fmc_sdcke0_pc3 &fmc_sdne0_pc2 &fmc_sdnras_pf11 &fmc_sdncas_pg15 + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 + &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 &fmc_a9_pf15 + &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 &fmc_a14_pg4 &fmc_a15_pg5 + &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 + &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 + &fmc_d10_pe13 &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 + &fmc_d15_pd10>; + pinctrl-names = "default"; + status = "okay"; + + sdram { + status = "okay"; + power-up-delay = <100>; + num-auto-refresh = <8>; + mode-register = <0x230>; + refresh-rate = <0x395>; + + bank@0 { + reg = <0>; + st,sdram-control = ; + st,sdram-timing = <2 9 6 8 2 2 3>; + }; + }; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK(AHB1, 27)>, + <&rcc STM32_SRC_HSI48 USB_SEL(3)>; + maximum-speed = "full-speed"; + ram-size = <1280>; + num-bidir-endpoints = <8>; + status = "okay"; + + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + label = "CDC_ACM_0"; + }; +}; + +&mac { + status = "okay"; + phy-connection-type = "rmii"; + phy-handle = <ð_phy>; + local-mac-address = [00 80 E1 2A 75 01]; + pinctrl-0 = <ð_ref_clk_pa1 + ð_crs_dv_pa7 + ð_rxd0_pc4 + ð_rxd1_pc5 + ð_tx_en_pg11 + ð_txd0_pg13 + ð_txd1_pg14>; + pinctrl-names = "default"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; + pinctrl-names = "default"; + + eth_phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + default-speeds = "10BASE Full-Duplex","100BASE Full-Duplex"; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ruiside/art_pi/art_pi.yaml b/boards/ruiside/art_pi/art_pi.yaml new file mode 100644 index 0000000000000..a67f3fbe3cd4b --- /dev/null +++ b/boards/ruiside/art_pi/art_pi.yaml @@ -0,0 +1,18 @@ +identifier: art_pi +name: art pi +type: mcu +arch: arm +toolchain: + - zephyr +ram: 1024 +flash: 128 +supported: + - gpio + - uart + - i2c + - spi + - flash + - display + - sdmmc + - usb +vendor: ruiside diff --git a/boards/ruiside/art_pi/art_pi_defconfig b/boards/ruiside/art_pi/art_pi_defconfig new file mode 100644 index 0000000000000..49f67c7750f4b --- /dev/null +++ b/boards/ruiside/art_pi/art_pi_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Dejiang He <2995560796@qq.com> +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW Stack Protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/ruiside/art_pi/board.cmake b/boards/ruiside/art_pi/board.cmake new file mode 100644 index 0000000000000..66f985070e4ad --- /dev/null +++ b/boards/ruiside/art_pi/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=ART-Pi_W25Q64.stldr") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) \ No newline at end of file diff --git a/boards/ruiside/art_pi/board.yml b/boards/ruiside/art_pi/board.yml new file mode 100644 index 0000000000000..0947989931f94 --- /dev/null +++ b/boards/ruiside/art_pi/board.yml @@ -0,0 +1,6 @@ +board: + name: art_pi + full_name: ART-Pi + vendor: ruiside + socs: + - name: stm32h750xx diff --git a/boards/ruiside/art_pi/doc/img/art_pi.webp b/boards/ruiside/art_pi/doc/img/art_pi.webp new file mode 100644 index 0000000000000..49042d306453d Binary files /dev/null and b/boards/ruiside/art_pi/doc/img/art_pi.webp differ diff --git a/boards/ruiside/art_pi/doc/index.rst b/boards/ruiside/art_pi/doc/index.rst new file mode 100644 index 0000000000000..7a04a46d56c51 --- /dev/null +++ b/boards/ruiside/art_pi/doc/index.rst @@ -0,0 +1,138 @@ +.. zephyr:board:: art_pi + +Overview +******** + +The ART-Pi is an open-source hardware platform designed by the +RT-Thread team specifically for embedded software engineers +and open-source makers, offering extensive expandability for DIY projects. + +Key Features + +- STM32H750XBH6 microcontroller featuring 128 Kbytes of Flash and 1024 Kbytes of SRAM in an TFBGA225 package +- On-board ST-LINK/V2.1 debugger/programmer +- SDIO TF Card slot +- SDIO WIFI:AP6212 +- HDC UART BuleTooth:AP6212 +- 32-MB SDRAM +- 16-Mbytes SPI FLASH +- 8-Mbytes QSPI FLASH +- One Power LED (blue) for 3.3 V power-on +- Two user LEDs blue and red +- Two ST-LINK LEDs: blue and red +- Two push-buttons (user and reset) +- Board connectors: + + - USB OTG with Type-C connector + - RGB888 FPC connector + +More information about the board can be found at the `ART-Pi website`_. + +Hardware +******** + +ART-Pi provides the following hardware components: + +The STM32H750xx devices are a high-performance microcontrollers family (STM32H7 +Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core. +They operate at a frequency of up to 480 MHz. + +More information about STM32H750xx can be found here: + +- `STM32H750 on www.st.com`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The ART-Pi board features a On-board ST-LINK/V2.1 debugger/programmer. Board is configured as follows: + +- UART4 TX/RX : PA0/PI9 (ST-Link Virtual Port Com) +- LED1 (red) : PC15 +- LED2 (blue) : PI8 +- USER PUSH-BUTTON : PH4 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. note:: + + Check if your ST-LINK V2.1 has newest FW version. It can be done with `STM32CubeProgrammer`_ + +Flashing +======== + +First, connect the art_pi to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your art_pi board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: art_pi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.2.0-3809-g1d6b6759aa1a *** + Hello World! art_pi/stm32h750xx + +Blinky example can also be used: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: art_pi + :goals: build flash + +To flash an application that requires loading firmware on +external flash, see `ART_PI Externloader`_ + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: art_pi + :maybe-skip-config: + :goals: debug + +References +********** +.. target-notes:: + +.. _ART-Pi website: + https://github.com/RT-Thread-Studio/sdk-bsp-stm32h750-realthread-artpi + +.. _STM32H750 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h750xb.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _ART_PI Externloader: + https://github.com/newbie-jiang/art_pi_use_externalLoader_doc diff --git a/boards/ruiside/art_pi/support/openocd.cfg b/boards/ruiside/art_pi/support/openocd.cfg new file mode 100644 index 0000000000000..5ddb55e297657 --- /dev/null +++ b/boards/ruiside/art_pi/support/openocd.cfg @@ -0,0 +1,30 @@ +source [find interface/stlink-dap.cfg] +transport select dapdirect_swd + +set WORKAREASIZE 0x2000 +set CHIPNAME STM32H750XB +set BOARDNAME ART_PI + +source [find target/stm32h7x.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +}