diff --git a/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay index 1bf3123c3b8e7..9dd79fb000058 100644 --- a/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay +++ b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay @@ -5,24 +5,6 @@ * */ -&st_cam_i2c { - pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; - -&st_cam_dvp { - pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7 - &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9 - &dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9>; - pinctrl-names = "default"; -}; - &dma1 { status = "okay"; }; - -&dmamux1 { - status = "okay"; -}; diff --git a/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay index d760f240f5976..325412ca6f68d 100644 --- a/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay +++ b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay @@ -14,6 +14,8 @@ }; &st_cam_i2c { + status = "okay"; + ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; diff --git a/boards/shields/st_stm32f4dis_cam/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_stm32f4dis_cam/boards/stm32h747i_disco_stm32h747xx_m7.overlay new file mode 100644 index 0000000000000..edcd8dba94560 --- /dev/null +++ b/boards/shields/st_stm32f4dis_cam/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma1 { + status = "okay"; +}; diff --git a/boards/shields/st_stm32f4dis_cam/boards/stm32l4r9i_disco.overlay b/boards/shields/st_stm32f4dis_cam/boards/stm32l4r9i_disco.overlay new file mode 100644 index 0000000000000..d2b3293eb5c6d --- /dev/null +++ b/boards/shields/st_stm32f4dis_cam/boards/stm32l4r9i_disco.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; + +&mco1 { + clocks = <&rcc STM32_SRC_SYSCLK MCO1_SEL(MCO_SEL_SYSCLK)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_pa8>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/shields/st_stm32f4dis_cam/st_stm32f4dis_cam.overlay b/boards/shields/st_stm32f4dis_cam/st_stm32f4dis_cam.overlay index f1e16a339a0ff..844dfefda638d 100644 --- a/boards/shields/st_stm32f4dis_cam/st_stm32f4dis_cam.overlay +++ b/boards/shields/st_stm32f4dis_cam/st_stm32f4dis_cam.overlay @@ -10,14 +10,6 @@ }; }; -&dma2 { - status = "okay"; -}; - -&dmamux1 { - status = "okay"; -}; - &st_cam_i2c { ov9655: camera@30 { compatible = "ovti,ov9655"; @@ -32,24 +24,9 @@ }; }; -#define MCO1_SEL_SYSCLK 1 - -#define MCO1_PRE_DIV_4 2 - -&mco1 { - status = "okay"; - clocks = <&rcc STM32_SRC_SYSCLK MCO1_SEL(MCO1_SEL_SYSCLK)>; - prescaler = ; - pinctrl-0 = <&rcc_mco_pa8>; - pinctrl-names = "default"; -}; - &st_cam_dvp { status = "okay"; - /* DMA config is already hardcoded within the DCMI driver */ - dmas = <&dma2 5 0 0>; - port { dcmi_ep_in: endpoint { remote-endpoint-label = "ov9655_ep_out"; diff --git a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay index d5070ff5380f3..9a10bf4858558 100644 --- a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay +++ b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay @@ -6,7 +6,7 @@ /* AHB clocks must respect the minimum ratio AHB / DCMI_PIXCLK of 2.5 (AN5020 - Rev 3). * The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48 - * and MCO1_PRE_DIV_4. + * and MCO_PRE_DIV_4. */ &rcc { clocks = <&pll>; @@ -19,20 +19,10 @@ d3ppre = <2>; }; -/* See reference manual (RM0433 Rev 8) page 390: - * 100: HSI48 clock selected (hsi48_ck) - */ -#define MCO1_SEL_HSI48 4 - -/* See reference manual (RM0433 Rev 8) page 391: - * 0100: division by 4 - */ -#define MCO1_PRE_DIV_4 4 - &mco1 { status = "okay"; clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>; - prescaler = ; + prescaler = ; pinctrl-0 = <&rcc_mco_1_pa8>; pinctrl-names = "default"; }; diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi b/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi index 3f80d8d311e17..0745cc853adc5 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi +++ b/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi @@ -100,6 +100,28 @@ <53 0 &gpioj 12 0>, /* LCD_BL_CTRL */ <57 0 &gpiog 3 0>; /* DSI_RESET */ }; + + dcmi_camera_connector: connector_dcmi_camera { + compatible = "st,stm32-dcmi-camera-fpu-330zh"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <3 0 &gpiod 12 0>, /* I2C4_SCL */ + <4 0 &gpiod 13 0>, /* I2C4_SDA */ + /* RESET is directly connected to MCU reset */ + <6 0 &gpioj 14 0>, /* PWDN_EN */ + <12 0 &gpiob 7 0>, /* DCMI_VSYNC */ + <14 0 &gpioa 4 0>, /* DCMI_HSYNC */ + <16 0 &gpioa 6 0>, /* DCMI_PIXCK */ + <20 0 &gpiob 9 0>, /* DCMI_D7 */ + <21 0 &gpiob 8 0>, /* DCMI_D6 */ + <22 0 &gpiod 3 0>, /* DCMI_D5 */ + <23 0 &gpioc 11 0>, /* DCMI_D4 */ + <24 0 &gpioc 9 0>, /* DCMI_D3 */ + <25 0 &gpiog 10 0>, /* DCMI_D2 */ + <26 0 &gpioc 7 0>, /* DCMI_D1 */ + <27 0 &gpioc 6 0>; /* DCMI_D0 */ + }; }; &rcc { diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts index bf06ea2e6ce2e..6adc60c145858 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts @@ -298,3 +298,13 @@ zephyr_mipi_dsi: &mipi_dsi {}; /* alias used by LCD display shields */ zephyr_lcd_controller: <dc {}; + +/* alias used by camera shields */ +st_cam_i2c: &i2c4 {}; + +st_cam_dvp: &dcmi { + pinctrl-0 = <&dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9 + &dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9 + &dcmi_pixclk_pa6 &dcmi_hsync_pa4 &dcmi_vsync_pb7>; + pinctrl-names = "default"; +}; diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index a68a7e84988dc..25354edd4646a 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -163,7 +163,7 @@ status = "okay"; }; -&i2c4 { +st_cam_i2c: &i2c4 { pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>; pinctrl-names = "default"; clock-frequency = ; @@ -309,6 +309,9 @@ }; }; -st_cam_i2c: &i2c4 {}; - -st_cam_dvp: &dcmi {}; +st_cam_dvp: &dcmi { + pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7 + &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9 + &dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9>; + pinctrl-names = "default"; +}; diff --git a/drivers/dma/dma_stm32.h b/drivers/dma/dma_stm32.h index a0d0674de7d2b..dcb41a6b2eaeb 100644 --- a/drivers/dma/dma_stm32.h +++ b/drivers/dma/dma_stm32.h @@ -95,11 +95,6 @@ void stm32_dma_enable_stream(DMA_TypeDef *dma, uint32_t id); bool stm32_dma_is_enabled_stream(DMA_TypeDef *dma, uint32_t id); int stm32_dma_disable_stream(DMA_TypeDef *dma, uint32_t id); -#if !defined(CONFIG_DMAMUX_STM32) -void stm32_dma_config_channel_function(DMA_TypeDef *dma, uint32_t id, - uint32_t slot); -#endif - #ifdef CONFIG_DMA_STM32_V1 void stm32_dma_disable_fifo_irq(DMA_TypeDef *dma, uint32_t id); bool stm32_dma_check_fifo_mburst(LL_DMA_InitTypeDef *DMAx); diff --git a/drivers/dma/dma_stm32_bdma.h b/drivers/dma/dma_stm32_bdma.h index ea6ee145283bd..c6374692bb150 100644 --- a/drivers/dma/dma_stm32_bdma.h +++ b/drivers/dma/dma_stm32_bdma.h @@ -73,11 +73,6 @@ bool stm32_bdma_is_irq_happened(BDMA_TypeDef *dma, uint32_t id); void stm32_bdma_enable_channel(BDMA_TypeDef *dma, uint32_t id); int stm32_bdma_disable_channel(BDMA_TypeDef *dma, uint32_t id); -#if !defined(CONFIG_DMAMUX_STM32) -void stm32_dma_config_channel_function(BDMA_TypeDef *dma, uint32_t id, - uint32_t slot); -#endif - #ifdef CONFIG_DMAMUX_STM32 /* bdma_stm32_ api functions are exported to the bdmamux_stm32 */ #define BDMA_STM32_EXPORT_API diff --git a/drivers/dma/dma_stm32_v1.c b/drivers/dma/dma_stm32_v1.c index c22b171d9c5a7..58bd15494d621 100644 --- a/drivers/dma/dma_stm32_v1.c +++ b/drivers/dma/dma_stm32_v1.c @@ -35,7 +35,7 @@ uint32_t dma_stm32_id_to_stream(uint32_t id) return stream_nr[id]; } -#if !defined(CONFIG_DMAMUX_STM32) +#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32MP1X) uint32_t dma_stm32_slot_to_channel(uint32_t slot) { static const uint32_t channel_nr[] = { @@ -345,15 +345,6 @@ void stm32_dma_disable_fifo_irq(DMA_TypeDef *dma, uint32_t id) LL_DMA_DisableIT_FE(dma, dma_stm32_id_to_stream(id)); } -#if !defined(CONFIG_DMAMUX_STM32) -void stm32_dma_config_channel_function(DMA_TypeDef *dma, uint32_t id, - uint32_t slot) -{ - LL_DMA_SetChannelSelection(dma, dma_stm32_id_to_stream(id), - dma_stm32_slot_to_channel(slot)); -} -#endif - uint32_t stm32_dma_get_mburst(struct dma_config *config, bool source_periph) { uint32_t memory_burst; diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi index 15ee5f0f0e1d9..33cc58ef87aad 100644 --- a/dts/arm/st/l4/stm32l4p5.dtsi +++ b/dts/arm/st/l4/stm32l4p5.dtsi @@ -359,7 +359,7 @@ interrupts = <85 0>; interrupt-names = "dcmi"; clocks = <&rcc STM32_CLOCK(AHB2, 14)>; - dmas = <&dma1 0 91 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + dmas = <&dma1 1 91 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; status = "disabled"; diff --git a/dts/arm/st/l4/stm32l4r5.dtsi b/dts/arm/st/l4/stm32l4r5.dtsi index 352512bef45d9..675562a9cc8b4 100644 --- a/dts/arm/st/l4/stm32l4r5.dtsi +++ b/dts/arm/st/l4/stm32l4r5.dtsi @@ -38,7 +38,7 @@ }; dcmi@50050000 { - dmas = <&dma2 0 90 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + dmas = <&dma1 1 90 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; }; diff --git a/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/include/zephyr/dt-bindings/clock/stm32h7_clock.h index accdffbb2ddf1..ae8df9b9a0965 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7_clock.h @@ -133,4 +133,19 @@ #define MCO_PRE_DIV_14 14 #define MCO_PRE_DIV_15 15 +/* MCO1 clock output */ +#define MCO1_SEL_HSI 0 +#define MCO1_SEL_LSE 1 +#define MCO1_SEL_HSE 2 +#define MCO1_SEL_PLL1QCLK 3 +#define MCO1_SEL_HSI48 4 + +/* MCO2 clock output */ +#define MCO2_SEL_SYSCLK 0 +#define MCO2_SEL_PLL2PCLK 1 +#define MCO2_SEL_HSE 2 +#define MCO2_SEL_PLL1PCLK 3 +#define MCO2_SEL_CSI 4 +#define MCO2_SEL_LSI 5 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h index 0f9da9234b837..7fe6e514bce4c 100644 --- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h @@ -89,4 +89,21 @@ #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG) #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 0 +#define MCO_PRE_DIV_2 1 +#define MCO_PRE_DIV_4 2 +#define MCO_PRE_DIV_8 3 +#define MCO_PRE_DIV_16 4 + +/* MCO clock output */ +#define MCO_SEL_SYSCLK 1 +#define MCO_SEL_MSI 2 +#define MCO_SEL_HSI16 3 +#define MCO_SEL_HSE 4 +#define MCO_SEL_PLLCLK 5 +#define MCO_SEL_LSI 6 +#define MCO_SEL_LSE 7 +#define MCO_SEL_HSI48 8 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */