From b3dde1a0162b5492860289b7effc5782348845f5 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 19 Sep 2025 11:17:44 +0200 Subject: [PATCH 1/2] include: drivers: stm32 clock mux CK48 definition Define the STM32_CK48_ENABLED especially for the stm32F4 series when ck48 node is enabled to leverage its already implemented support. Signed-off-by: Francois Ramu --- .../clock_control/stm32_clock_control.h | 5 +++++ .../boards/f4_sdmmc48_pll.overlay | 22 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index 8852c252007c5..033dd0f89e188 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -172,6 +172,11 @@ #define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler) #endif /* rcc node compatible st_stm32n6_rcc and okay */ +/** clock 48MHz node related symbols */ +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk48), st_stm32_clock_mux, okay) +#define STM32_CK48_ENABLED 1 +#endif + /** PLL node related symbols */ #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay index 529877847332c..f71ca17c6a0f8 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay @@ -12,6 +12,28 @@ status = "okay"; }; +/* + * In case the clk48 is selecting the STM32_SRC_PLL_Q with + * clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; + * one possible PLL config to give 48MHz on the pll_q output is as follows : + &pll { + div-m = <4>; + mul-n = <192>; + div-p = <4>; + div-q = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <2>; + apb2-prescaler = <1>; +}; +*/ + &plli2s { div-m = <4>; mul-n = <96>; From d9708c80abfcfff5114a45be404c850616e76c3d Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 13 Oct 2025 09:56:30 +0200 Subject: [PATCH 2/2] drivers: clock control: stm32 common clock enables clk48 This commit enables the clk48 clock mux if STM32_CK48_ENABLED is set by the device tree. Signed-off-by: Francois Ramu --- drivers/clock_control/clock_stm32_ll_common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index c788e4025ffcd..36ed32ddae39a 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -186,6 +186,13 @@ int enabled_clock(uint32_t src_clk) } break; #endif /* STM32_SRC_MSI */ +#if defined(STM32_SRC_CK48) + case STM32_SRC_CK48: + if (!IS_ENABLED(STM32_CK48_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_CK48 */ #if defined(STM32_SRC_PLLCLK) case STM32_SRC_PLLCLK: if (!IS_ENABLED(STM32_PLL_ENABLED)) {