diff --git a/boards/witte/linum/CMakeLists.txt b/boards/witte/linum/CMakeLists.txt
new file mode 100644
index 0000000000000..0901337610a12
--- /dev/null
+++ b/boards/witte/linum/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Felipe Neves
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources_ifdef(CONFIG_MEMC
+  SECTIONS sdram.ld)
diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts
index 8435b543c198c..80bf163970ded 100644
--- a/boards/witte/linum/linum.dts
+++ b/boards/witte/linum/linum.dts
@@ -19,6 +19,8 @@
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,dtcm = &dtcm;
+		zephyr,display = &ltdc;
+		zephyr,touch = &ft5446;
 		zephyr,code-partition = &slot0_partition;
 		zephyr,canbus = &fdcan1;
 	};
@@ -54,6 +56,13 @@
 		led0 = &green_led;
 		led1 = &blue_led;
 	};
+
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&ft5446>;
+		swap-xy;
+	};
+
 };
 
 &gpiod {
@@ -190,6 +199,12 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-names = "default";
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_FAST>;
+
+	ft5446: ft5446@38 {
+		compatible = "focaltech,ft5336";
+		reg = <0x38>;
+		int-gpios = <&gpioh 9 0>;
+	};
 };
 
 &timers12 {
@@ -265,17 +280,44 @@ zephyr_udc0: &usbotg_fs {
 };
 
 &fmc {
-	pinctrl-0 = <&fmc_nbl0_pe0
-		     &fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
-		     &fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15
-		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
-		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
-		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
-		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
-		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
-		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
-		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
-		     &fmc_d15_pd10>;
+	pinctrl-0 = <&fmc_a0_pf0
+			&fmc_a1_pf1
+			&fmc_a2_pf2
+			&fmc_a3_pf3
+			&fmc_a4_pf4
+			&fmc_a5_pf5
+			&fmc_a6_pf12
+			&fmc_a7_pf13
+			&fmc_a8_pf14
+			&fmc_a9_pf15
+			&fmc_a10_pg0
+			&fmc_a11_pg1
+			&fmc_a14_pg4
+			&fmc_a15_pg5
+			&fmc_d0_pd14
+			&fmc_d1_pd15
+			&fmc_d2_pd0
+			&fmc_d3_pd1
+			&fmc_d4_pe7
+			&fmc_d5_pe8
+			&fmc_d6_pe9
+			&fmc_d7_pe10
+			&fmc_d8_pe11
+			&fmc_d9_pe12
+			&fmc_d10_pe13
+			&fmc_d11_pe14
+			&fmc_d12_pe15
+			&fmc_d13_pd8
+			&fmc_d14_pd9
+			&fmc_d15_pd10
+			&fmc_nbl0_pe0
+			&fmc_nbl1_pe1
+			&fmc_sdcke0_pc3_c
+			&fmc_sdclk_pg8
+			&fmc_sdncas_pg15
+			&fmc_sdne0_pc2_c
+			&fmc_sdnras_pf11
+			&fmc_sdnwe_pc0>;
 	pinctrl-names = "default";
 	status = "okay";
 
@@ -284,57 +326,71 @@ zephyr_udc0: &usbotg_fs {
 		power-up-delay = <100>;
 		num-auto-refresh = <8>;
 		mode-register = <0x220>;
-		refresh-rate = <0x603>;
-
-		bank@1 {
-			reg = <1>;
+		refresh-rate = <1562>;
+		bank@0 {
+			reg = <0>;
 			st,sdram-control = <STM32_FMC_SDRAM_NC_8
-					    STM32_FMC_SDRAM_NR_12
-					    STM32_FMC_SDRAM_MWID_16
-					    STM32_FMC_SDRAM_NB_4
-					    STM32_FMC_SDRAM_CAS_3
-					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
-					    STM32_FMC_SDRAM_RBURST_ENABLE
-					    STM32_FMC_SDRAM_RPIPE_0>;
-			st,sdram-timing = <2 7 4 7 2 2 2>;
+					STM32_FMC_SDRAM_NR_12
+					STM32_FMC_SDRAM_MWID_16
+					STM32_FMC_SDRAM_NB_4
+					STM32_FMC_SDRAM_CAS_2
+					STM32_FMC_SDRAM_SDCLK_PERIOD_3
+					STM32_FMC_SDRAM_RBURST_ENABLE
+					STM32_FMC_SDRAM_RPIPE_0>;
+			st,sdram-timing = <2 6 4 6 2 2 2>;
 		};
 	};
 };
 
 &ltdc {
-	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
-		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
-		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
-		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
-		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
-		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
-		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
+	pinctrl-0 = <&ltdc_b0_pj12
+			&ltdc_b1_pj13
+			&ltdc_b2_pj14
+			&ltdc_b3_pj15
+			&ltdc_b4_pk3
+			&ltdc_b5_pk4
+			&ltdc_b6_pk5
+			&ltdc_b7_pk6
+			&ltdc_r0_pi15
+			&ltdc_r1_pj0
+			&ltdc_r2_pj1
+			&ltdc_r3_pj2
+			&ltdc_r4_pj3
+			&ltdc_r5_pj4
+			&ltdc_r6_pj5
+			&ltdc_r7_pj6
+			&ltdc_g0_pj7
+			&ltdc_g1_pj8
+			&ltdc_g2_pj9
+			&ltdc_g3_pj10
+			&ltdc_g4_pj11
+			&ltdc_g5_pk0
+			&ltdc_g6_pk1
+			&ltdc_g7_pk2
+			&ltdc_de_pk7
+			&ltdc_clk_pi14
+			&ltdc_hsync_pi10
+			&ltdc_vsync_pi9>;
 	pinctrl-names = "default";
-
-	disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
-
+	disp-on-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
 	ext-sdram = <&sdram1>;
 	status = "okay";
-
-	clocks = <&rcc STM32_CLOCK(APB3, 3)>,
-		 <&rcc STM32_SRC_PLL3_R NO_SEL>;
-
-	width = <480>;
-	height = <272>;
+	width = <1024>;
+	height = <600>;
 	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
 
 	display-timings {
 		compatible = "zephyr,panel-timing";
-		de-active = <1>;
+		de-active = <0>;
 		pixelclk-active = <0>;
 		hsync-active = <0>;
 		vsync-active = <0>;
 		hsync-len = <1>;
-		vsync-len = <10>;
-		hback-porch = <43>;
-		vback-porch = <12>;
-		hfront-porch = <8>;
-		vfront-porch = <4>;
+		vsync-len = <1>;
+		hback-porch = <160>;
+		vback-porch = <23>;
+		hfront-porch = <160>;
+		vfront-porch = <12>;
 	};
 	def-back-color-red = <0xFF>;
 	def-back-color-green = <0xFF>;
diff --git a/boards/witte/linum/sdram.ld b/boards/witte/linum/sdram.ld
new file mode 100644
index 0000000000000..4b4508ccaba76
--- /dev/null
+++ b/boards/witte/linum/sdram.ld
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Felipe Neves.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)
+GROUP_START(SDRAM1)
+
+	SECTION_PROLOGUE(_STM32_SDRAM1_SECTION_NAME, (NOLOAD),)
+	{
+		*(.lvgl_buf)
+		*(.lvgl_heap)
+	} GROUP_LINK_IN(SDRAM1)
+
+GROUP_END(SDRAM1)
+#endif