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boards: witte: linum: add suport for the display subsystem #96378

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uLipe
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@uLipe uLipe commented Sep 22, 2025

  • Enable the LTDC controller and bind the zephyr,display node to it
  • Enable the touch controller and bind the lvgl pointer to it.
  • Enable the SDRAM to put framebuffers and LVGL stuff to there

@uLipe uLipe requested review from erwango and kartben September 22, 2025 14:51
erwango
erwango requested changes Sep 22, 2025
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In the first commit, please restrict on the functional changes and remove all the formatting changes.

@uLipe uLipe force-pushed the feature/fix_linum branch 3 times, most recently from 8f5b80f to 4fc7be5 Compare September 22, 2025 17:26
@uLipe
boards: witte: linum: add display support
e28f4ed 
By enabling the LTDC controller and attaching it to
the zephyr, display node

Signed-off-by: Felipe Neves <[email protected]>
@uLipe
boards: witte: linum: enable SDRAM support
e884947 
To allow the display framebuffers to be placed
at the external RAM memory available on the
Linum board.

Signed-off-by: Felipe Neves <[email protected]>
@uLipe uLipe requested a review from erwango September 22, 2025 17:28
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Quality Gate Passed Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

erwango
erwango reviewed Sep 23, 2025
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boards/witte/linum/linum.dts
Comment on lines -292 to +339
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_3
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
st,sdram-timing = <2 7 4 7 2 2 2>;
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_3
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
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Please keep indentation here

erwango
erwango reviewed Sep 23, 2025
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boards/witte/linum/linum.dts
Comment on lines +346 to +373
pinctrl-0 = <&ltdc_b0_pj12
&ltdc_b1_pj13
&ltdc_b2_pj14
&ltdc_b3_pj15
&ltdc_b4_pk3
&ltdc_b5_pk4
&ltdc_b6_pk5
&ltdc_b7_pk6
&ltdc_r0_pi15
&ltdc_r1_pj0
&ltdc_r2_pj1
&ltdc_r3_pj2
&ltdc_r4_pj3
&ltdc_r5_pj4
&ltdc_r6_pj5
&ltdc_r7_pj6
&ltdc_g0_pj7
&ltdc_g1_pj8
&ltdc_g2_pj9
&ltdc_g3_pj10
&ltdc_g4_pj11
&ltdc_g5_pk0
&ltdc_g6_pk1
&ltdc_g7_pk2
&ltdc_de_pk7
&ltdc_clk_pi14
&ltdc_hsync_pi10
&ltdc_vsync_pi9>;
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I assume this was made on purpose for readability, but that there are on going efforts to lint zephyr dts files, see #92805, #92803, #96317 and #92334, and tit was decided otherwise in those discussions.
Please conform to the rules applied in those PRs. (But you can still jump in these discussions and make your point there of course ;) )

nordicjm
nordicjm requested changes Sep 23, 2025
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boards/witte/linum/linum.dts
bank@1 {
reg = <1>;
refresh-rate = <1562>;
bank@0 {
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this previously complied with the coding standard, now it does not, newline missing on line 330

@erwango erwango mentioned this pull request Sep 23, 2025
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erwango commented Sep 23, 2025

@uLipe You will be able to drop second commit once #96322 is merged.

@avolmat-st avolmat-st self-requested a review September 23, 2025 16:08
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@uLipe You will be able to drop second commit once #96322 is merged.

As soon as PR #96322 will be merged, you can simply add the following 4 CONFIG within your .conf file to make LVGL point to the SDRAM1.

Ensure the following 2 are disabled:

CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION=n
CONFIG_LV_Z_VDB_CUSTOM_SECTION=n

Then set below 4 configs:

CONFIG_LV_Z_MEMORY_POOL_ZEPHYR_REGION=y
CONFIG_LV_Z_MEMORY_POOL_ZEPHYR_REGION_NAME="SDRAM1"
CONFIG_LV_Z_VDB_ZEPHYR_REGION=y
CONFIG_LV_Z_VDB_ZEPHYR_REGION_NAME="SDRAM1"

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uLipe commented Sep 23, 2025

Thanks @avolmat-st and @erwango in this case I will wait #96322 to get merged, in meantime I will check the format details.

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@erwango erwango erwango requested changes

@nordicjm nordicjm nordicjm requested changes

@kartben kartben Awaiting requested review from kartben

@avolmat-st avolmat-st Awaiting requested review from avolmat-st

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@uLipe @erwango @avolmat-st @nordicjm