diff --git a/boards/nxp/frdm_mcxa344/CMakeLists.txt b/boards/nxp/frdm_mcxa344/CMakeLists.txt new file mode 100644 index 0000000000000..c06b9273965c0 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxa344/Kconfig b/boards/nxp/frdm_mcxa344/Kconfig new file mode 100644 index 0000000000000..9e41ea4cc16a3 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/Kconfig @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA344 + select BOARD_EARLY_INIT_HOOK diff --git a/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344 b/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344 new file mode 100644 index 0000000000000..4d895ff6d8efa --- /dev/null +++ b/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA344 + select SOC_MCXA344 + select SOC_PART_NUMBER_MCXA344VLL diff --git a/boards/nxp/frdm_mcxa344/board.c b/boards/nxp/frdm_mcxa344/board.c new file mode 100644 index 0000000000000..7a8cc80a63143 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/board.c @@ -0,0 +1,148 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/* Core clock frequency: 180MHz */ +#define CLOCK_INIT_CORE_CLOCK 180000000U +#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +void board_early_init_hook(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P2V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */ + CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */ + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P2V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U); /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */ + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta)) + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb)) + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc)) + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd)) + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte)) + RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) + RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) + RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0); + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1); + RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2); + RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3); + RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; +} diff --git a/boards/nxp/frdm_mcxa344/board.cmake b/boards/nxp/frdm_mcxa344/board.cmake new file mode 100644 index 0000000000000..d111b15af049a --- /dev/null +++ b/boards/nxp/frdm_mcxa344/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXA344") +board_runner_args(linkserver "--device=MCXA344:FRDM-MCXA344") +board_runner_args(pyocd "--target=MCXA344") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_mcxa344/board.yml b/boards/nxp/frdm_mcxa344/board.yml new file mode 100644 index 0000000000000..20a587665eacc --- /dev/null +++ b/boards/nxp/frdm_mcxa344/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_mcxa344 + full_name: FRDM-MCXA344 + vendor: nxp + socs: + - name: mcxa344 diff --git a/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp b/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp new file mode 100644 index 0000000000000..7412adb76ac8a Binary files /dev/null and b/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp differ diff --git a/boards/nxp/frdm_mcxa344/doc/index.rst b/boards/nxp/frdm_mcxa344/doc/index.rst new file mode 100644 index 0000000000000..8948e03f88a80 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/doc/index.rst @@ -0,0 +1,180 @@ +.. zephyr:board:: frdm_mcxa344 + +Overview +******** + +The MCXA344 Mixed-Signal MCUs, featuring an Arm® Cortex®-M33, support running up to +180 MHz, 256 KB Flash and 64 kB RAM. The MCX A344 targets motor control applications, +optimized with high performance and MAU engine, integrated 2x FlexPWM with 4x submodule +combined with AOI, up to 2x ADC and rich serial peripheral and SmartDMA. The MCX MCX-A344 +devices are supported by the MCUXpresso Developer Experience to optimize, ease and help +accelerate embedded system development. + +Hardware +******** + +- MCX-A344 Arm Cortex-M33 microcontroller running at 180 MHz +- 256KB dual-bank on chip Flash +- 64 KB RAM +- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, SmartDMA/Camera Header, mikroBUS + +For more information about the MCX-A344 SoC and FRDM-MCXA344 board, see: + +- `MCX-A344 SoC Website`_ +- `MCX-A344 Datasheet`_ +- `MCX-A344 Reference Manual`_ +- `FRDM-MCXA344 Website`_ +- `FRDM-MCXA344 User Guide`_ +- `FRDM-MCXA344 Board User Manual`_ +- `FRDM-MCXA344 Schematics`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The MCX-A344 SoC has 5 gpio controllers and has pinmux registers which +can be used to configure the functionality of a pin. + ++------------+-----------------+----------------------------+ +| Name | Function | Usage | ++============+=================+============================+ +| PIO2_3 | UART | UART RX | ++------------+-----------------+----------------------------+ +| PIO2_2 | UART | UART TX | ++------------+-----------------+----------------------------+ + +System Clock +============ + +The MCX-A344 SoC is configured to use FRO running at 180MHz as a source for +the system clock. + +Serial Port +=========== + +The FRDM-MCXA344 SoC has 4 LPUART interfaces for serial communication. +LPUART 2 is configured as UART for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``ISP mode`` to program the firmware, +short jumper JP4. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``ISP mode`` +by shortening the jumper JP4. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must +be shorted. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J13, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa344 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa344/mcxa344 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa344/mcxa344 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa344/mcxa344 + +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +.. _MCX-A344 SoC Website: + TBD + +.. _MCX-A344 Datasheet: + TBD + +.. _MCX-A344 Reference Manual: + TBD + +.. _FRDM-MCXA344 Website: + TBD + +.. _FRDM-MCXA344 User Guide: + TBD + +.. _FRDM-MCXA344 Board User Manual: + TBD + +.. _FRDM-MCXA344 Schematics: + TBD diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi new file mode 100644 index 0000000000000..0179bb4093d2e --- /dev/null +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_lpuart2: pinmux_lpuart2 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts new file mode 100644 index 0000000000000..8028d7df658b9 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts @@ -0,0 +1,162 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxa344-pinctrl.dtsi" +#include +#include + +/ { + model = "NXP FRDM_MCXA344 board"; + compatible = "nxp,mcxa344", "nxp,mcx"; + + aliases{ + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + + green_led: led_1 { + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + + blue_led: led_2 { + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_2: button_2 { + label = "User SW2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + user_button_3: button_3 { + label = "User SW3"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + +&cpu0 { + clock-frequency = <180000000>; +}; + +&edma0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart2>; + pinctrl-names = "default"; +}; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(16)>; + read-only; + }; + + slot0_partition: partition@4000 { + label = "image-0"; + reg = <0x00004000 DT_SIZE_K(100)>; + }; + + slot1_partition: partition@1D000 { + label = "image-1"; + reg = <0x0001D000 DT_SIZE_K(100)>; + }; + + storage_partition: partition@36000 { + label = "storage"; + reg = <0x00036000 DT_SIZE_K(28)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml new file mode 100644 index 0000000000000..567723c5de8e0 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxa344 +name: NXP FRDM MCXA344 +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - arduino_gpio + - flash + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig b/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig new file mode 100644 index 0000000000000..7d2f14fdd3cb9 --- /dev/null +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_LPADC_DO_OFFSET_CALIBRATION=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/dts/arm/nxp/nxp_mcxa344.dtsi b/dts/arm/nxp/nxp_mcxa344.dtsi new file mode 100644 index 0000000000000..8701f53c4e831 --- /dev/null +++ b/dts/arm/nxp/nxp_mcxa344.dtsi @@ -0,0 +1,477 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,port-pinctrl"; + status = "okay"; + }; + + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + + soc { + syscon: syscon@40091000 { + compatible = "nxp,lpc-syscon"; + reg = <0x40091000 0x4000>; + #clock-cells = <1>; + reset: reset { + compatible = "nxp,lpc-syscon-reset"; + #reset-cells = <1>; + }; + }; + + sramx: memory@4000000 { + compatible = "mmio-sram"; + reg = <0x4000000 DT_SIZE_K(16)>; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(48)>; + }; + + porta: pinmux@400bc000 { + compatible = "nxp,port-pinmux"; + reg = <0x400bc000 0x1000>; + clocks = <&syscon MCUX_PORT0_CLK>; + }; + + portb: pinmux@400bd000 { + compatible = "nxp,port-pinmux"; + reg = <0x400bd000 0x1000>; + clocks = <&syscon MCUX_PORT1_CLK>; + }; + + portc: pinmux@400be000 { + compatible = "nxp,port-pinmux"; + reg = <0x400be000 0x1000>; + clocks = <&syscon MCUX_PORT2_CLK>; + }; + + portd: pinmux@400bf000 { + compatible = "nxp,port-pinmux"; + reg = <0x400bf000 0x1000>; + clocks = <&syscon MCUX_PORT3_CLK>; + }; + + porte: pinmux@400c0000 { + compatible = "nxp,port-pinmux"; + reg = <0x400c0000 0x1000>; + clocks = <&syscon MCUX_PORT4_CLK>; + }; + + gpio0: gpio@40102000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40102000 0x1000>; + interrupts = <71 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&porta>; + }; + + gpio1: gpio@40103000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40103000 0x1000>; + interrupts = <72 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portb>; + }; + + gpio2: gpio@40104000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40104000 0x1000>; + interrupts = <73 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portc>; + }; + + gpio3: gpio@40105000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40105000 0x1000>; + interrupts = <74 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portd>; + }; + + gpio4: gpio@40106000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40106000 0x1000>; + interrupts = <75 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&porte>; + }; + + lpuart0: lpuart@4009f000 { + compatible = "nxp,lpuart"; + status = "disabled"; + reg = <0x4009f000 0x1000>; + interrupts = <31 0>; + clocks = <&syscon MCUX_LPUART0_CLK>; + /* DMA channels 0 and 1, muxed to LPUART0 RX and TX */ + dmas = <&edma0 0 21>, <&edma0 1 22>; + dma-names = "rx", "tx"; + }; + + lpuart1: lpuart@400a0000 { + compatible = "nxp,lpuart"; + status = "disabled"; + reg = <0x400a0000 0x1000>; + interrupts = <32 0>; + clocks = <&syscon MCUX_LPUART1_CLK>; + /* DMA channels 2 and 3, muxed to LPUART1 RX and TX */ + dmas = <&edma0 2 23>, <&edma0 3 24>; + dma-names = "rx", "tx"; + }; + + lpuart2: lpuart@400a1000 { + compatible = "nxp,lpuart"; + status = "disabled"; + reg = <0x400a1000 0x1000>; + interrupts = <33 0>; + clocks = <&syscon MCUX_LPUART2_CLK>; + /* DMA channels 4 and 5, muxed to LPUART2 RX and TX */ + dmas = <&edma0 4 25>, <&edma0 5 26>; + dma-names = "rx", "tx"; + }; + + lpuart3: lpuart@400a2000 { + compatible = "nxp,lpuart"; + status = "disabled"; + reg = <0x400a2000 0x1000>; + interrupts = <34 0>; + clocks = <&syscon MCUX_LPUART3_CLK>; + /* DMA channels 6 and 7, muxed to LPUART3 RX and TX */ + dmas = <&edma0 6 27>, <&edma0 7 28>; + dma-names = "rx", "tx"; + }; + + fmu: flash-controller@40095000 { + compatible = "nxp,msf1"; + reg = <0x40095000 0x1000>; + interrupts = <12 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 DT_SIZE_K(256)>; + erase-block-size = <8192>; + write-block-size = <128>; + }; + + uuid: uuid@1100800 { + compatible = "nxp,lpc-uid"; + reg = <0x1100800 0x10>; + }; + }; + + ctimer0: ctimer@40004000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x40004000 0x1000>; + interrupts = <39 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&syscon MCUX_CTIMER0_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + ctimer1: ctimer@40005000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x40005000 0x1000>; + interrupts = <40 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&syscon MCUX_CTIMER1_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + ctimer2: ctimer@40006000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x40006000 0x1000>; + interrupts = <41 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&syscon MCUX_CTIMER2_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + edma0: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma"; + nxp,version = <4>; + dma-channels = <8>; + dma-requests = <86>; + + reg = <0x40080000 0x1000>; + interrupts = <2 0>, <3 0>, <4 0>, <5 0>, + <6 0>, <7 0>, <8 0>, <9 0>; + no-error-irq; + status = "disabled"; + }; + + flexcan0: can@400cc000 { + compatible = "nxp,flexcan"; + reg = <0x400cc000 0x1000>; + interrupts = <19 0>; + interrupt-names = "common"; + clocks = <&syscon MCUX_FLEXCAN0_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexpwm0: flexpwm@400a9000 { + compatible = "nxp,flexpwm"; + reg = <0x400a9000 0x1000>; + interrupt-names = "RELOAD-ERROR", "FAULT"; + interrupts = <44 0>, <45 0>; + flexpwm0_pwm0: pwm0 { + compatible = "nxp,imx-pwm"; + index = <0>; + interrupts = <46 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + + flexpwm0_pwm1: pwm1 { + compatible = "nxp,imx-pwm"; + index = <1>; + interrupts = <47 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + + flexpwm0_pwm2: pwm2 { + compatible = "nxp,imx-pwm"; + index = <2>; + interrupts = <48 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + }; + + flexpwm1: flexpwm@400aa000 { + compatible = "nxp,flexpwm"; + reg = <0x400aa000 0x1000>; + interrupt-names = "RELOAD-ERROR", "FAULT"; + interrupts = <79 0>, <80 0>; + flexpwm1_pwm0: pwm0 { + compatible = "nxp,imx-pwm"; + index = <0>; + interrupts = <81 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + + flexpwm1_pwm1: pwm1 { + compatible = "nxp,imx-pwm"; + index = <1>; + interrupts = <82 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + + flexpwm1_pwm2: pwm2 { + compatible = "nxp,imx-pwm"; + index = <2>; + interrupts = <83 0>; + #pwm-cells = <3>; + clocks = <&syscon MCUX_BUS_CLK>; + nxp,prescaler = <128>; + status = "disabled"; + run-in-wait; + }; + }; + + lpadc0: lpadc@400af000 { + compatible = "nxp,lpc-lpadc"; + reg = <0x400af000 0x1000>; + interrupts = <62 0>; + status = "disabled"; + clk-divider = <1>; + clk-source = <0>; + voltage-ref= <2>; + calibration-average = <128>; + power-level = <0>; + offset-value-a = <0>; + offset-value-b = <0>; + #io-channel-cells = <1>; + clocks = <&syscon MCUX_LPADC1_CLK>; + }; + + lpadc1: lpadc@400b0000 { + compatible = "nxp,lpc-lpadc"; + reg = <0x400b0000 0x1000>; + interrupts = <63 0>; + status = "disabled"; + clk-divider = <1>; + clk-source = <0>; + voltage-ref= <2>; + calibration-average = <128>; + power-level = <1>; + offset-value-a = <0>; + offset-value-b = <0>; + #io-channel-cells = <1>; + clocks = <&syscon MCUX_LPADC2_CLK>; + }; + + lpcmp0: lpcmp@400b1000 { + compatible = "nxp,lpcmp"; + reg = <0x400b1000 0x1000>; + interrupts = <64 0>; + status = "disabled"; + #io-channel-cells = <2>; + }; + + lpcmp1: lpcmp@400b2000 { + compatible = "nxp,lpcmp"; + reg = <0x400b2000 0x1000>; + interrupts = <65 0>; + status = "disabled"; + #io-channel-cells = <2>; + }; + + lpcmp2: lpcmp@400b3000 { + compatible = "nxp,lpcmp"; + reg = <0x400b3000 0x1000>; + interrupts = <66 0>; + status = "disabled"; + #io-channel-cells = <2>; + }; + + lpi2c0: i2c@4009a000 { + compatible = "nxp,lpi2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4009a000 0x1000>; + interrupts = <26 0>; + clocks = <&syscon MCUX_LPI2C0_CLK>; + status = "disabled"; + }; + + lpi2c1: i2c@4009b000 { + compatible = "nxp,lpi2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4009b000 0x1000>; + interrupts = <27 0>; + clocks = <&syscon MCUX_LPI2C1_CLK>; + status = "disabled"; + }; + + lpspi0: spi@4009c000 { + compatible = "nxp,lpspi"; + reg = <0x4009c000 0x1000>; + interrupts = <28 0>; + clocks = <&syscon MCUX_LPSPI0_CLK>; + tx-fifo-size = <4>; + rx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi1: spi@4009d000 { + compatible = "nxp,lpspi"; + reg = <0x4009d000 0x1000>; + interrupts = <29 0>; + clocks = <&syscon MCUX_LPSPI1_CLK>; + tx-fifo-size = <4>; + rx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lptmr0: lptmr@400ab000 { + compatible = "nxp,lptmr"; + reg = <0x400ab000 0x1000>; + interrupts = <55 0>; + clock-frequency = <16000>; + prescaler = <1>; + clk-source = <1>; + resolution = <32>; + status = "disabled"; + }; + + ostimer0: timers@400ad000 { + compatible = "nxp,os-timer"; + reg = <0x400ad000 0x1000>; + interrupts = <57 0>; + status = "disabled"; + }; + + temp0: temp0 { + compatible = "nxp,lpadc-temp40"; + status = "disabled"; + }; + + wwdt0: watchdog@4000c000 { + compatible = "nxp,lpc-wwdt"; + reg = <0x4000c000 0x1000>; + interrupts = <60 0>; + status = "disabled"; + clk-divider = <1>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/soc/nxp/mcx/mcxa/Kconfig b/soc/nxp/mcx/mcxa/Kconfig index af34d311ebaad..df1092cda6a0a 100644 --- a/soc/nxp/mcx/mcxa/Kconfig +++ b/soc/nxp/mcx/mcxa/Kconfig @@ -40,3 +40,10 @@ config SOC_MCXA366 select CPU_HAS_FPU select ARMV8_M_DSP select HAS_MCUX_CACHE + +config SOC_MCXA344 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select HAS_MCUX_CACHE diff --git a/soc/nxp/mcx/mcxa/Kconfig.soc b/soc/nxp/mcx/mcxa/Kconfig.soc index 1928fe2e42d3b..549204be406ef 100644 --- a/soc/nxp/mcx/mcxa/Kconfig.soc +++ b/soc/nxp/mcx/mcxa/Kconfig.soc @@ -27,12 +27,17 @@ config SOC_MCXA366 bool select SOC_FAMILY_MCXA +config SOC_MCXA344 + bool + select SOC_FAMILY_MCXA + config SOC default "mcxa153" if SOC_MCXA153 default "mcxa156" if SOC_MCXA156 default "mcxa346" if SOC_MCXA346 default "mcxa266" if SOC_MCXA266 default "mcxa366" if SOC_MCXA366 + default "mcxa344" if SOC_MCXA344 config SOC_PART_NUMBER_MCXA153VFM bool @@ -91,6 +96,18 @@ config SOC_PART_NUMBER_MCXA366VLH config SOC_PART_NUMBER_MCXA366VPN bool +config SOC_PART_NUMBER_MCXA344VFM + bool + +config SOC_PART_NUMBER_MCXA344VLF + bool + +config SOC_PART_NUMBER_MCXA344VLH + bool + +config SOC_PART_NUMBER_MCXA344VLL + bool + config SOC_PART_NUMBER default "MCXA153VFM" if SOC_PART_NUMBER_MCXA153VFM default "MCXA153VFT" if SOC_PART_NUMBER_MCXA153VFT @@ -111,3 +128,7 @@ config SOC_PART_NUMBER default "MCXA366VLL" if SOC_PART_NUMBER_MCXA366VLL default "MCXA366VLH" if SOC_PART_NUMBER_MCXA366VLH default "MCXA366VPN" if SOC_PART_NUMBER_MCXA366VPN + default "MCXA344VFM" if SOC_PART_NUMBER_MCXA344VFM + default "MCXA344VLF" if SOC_PART_NUMBER_MCXA344VLF + default "MCXA344VLH" if SOC_PART_NUMBER_MCXA344VLH + default "MCXA344VLL" if SOC_PART_NUMBER_MCXA344VLL diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml index 23bce577c193a..fae16fdbd8f8b 100644 --- a/soc/nxp/mcx/soc.yml +++ b/soc/nxp/mcx/soc.yml @@ -23,6 +23,7 @@ family: - name: mcxa346 - name: mcxa266 - name: mcxa366 + - name: mcxa344 - name: mcxw series: - name: mcxw2xx @@ -70,6 +71,8 @@ runners: - mcxw716c - qualifiers: - mcxw236 + - qualifiers: + - mcxa344 '--reset': - run: last runners: @@ -102,3 +105,5 @@ runners: - mcxw716c - qualifiers: - mcxw236 + - qualifiers: + - mcxa344 diff --git a/west.yml b/west.yml index 8ddf3001a042d..cdd42bba55df0 100644 --- a/west.yml +++ b/west.yml @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 4377ecfba52fe0ff7352eadf426b523ed3e1d27f + revision: pull/612/head path: modules/hal/nxp groups: - hal