From 605cda17178e5eb04e6dd6e934d3954829bf7576 Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Mon, 29 Sep 2025 10:09:13 +0000 Subject: [PATCH 1/5] drivers: flash: Add support Renesas MRAM driver Add support Renesas MRAM driver for RA devices Signed-off-by: Khoa Nguyen --- drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig.renesas_ra | 12 + drivers/flash/soc_flash_renesas_ra_mram.c | 254 ++++++++++++++++++ .../renesas,ra-mram-controller.yaml | 8 + dts/bindings/mtd/renesas,ra-nv-mram.yaml | 12 + modules/Kconfig.renesas | 5 + 6 files changed, 292 insertions(+) create mode 100644 drivers/flash/soc_flash_renesas_ra_mram.c create mode 100644 dts/bindings/flash_controller/renesas,ra-mram-controller.yaml create mode 100644 dts/bindings/mtd/renesas,ra-nv-mram.yaml diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 2ff0f66a59084..0aebf81894709 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -63,6 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAMC soc_flash_nrf_mramc.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER_RMC soc_flash_numaker_rmc.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RENESAS_RA_MRAM soc_flash_renesas_ra_mram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RENESAS_RX soc_flash_renesas_rx.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RTS5912 flash_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c) diff --git a/drivers/flash/Kconfig.renesas_ra b/drivers/flash/Kconfig.renesas_ra index 19078f1d0d856..e84a391eda0e2 100644 --- a/drivers/flash/Kconfig.renesas_ra +++ b/drivers/flash/Kconfig.renesas_ra @@ -41,3 +41,15 @@ config FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING are undefined. endif # SOC_FLASH_RENESAS_RA_HP + +config SOC_FLASH_RENESAS_RA_MRAM + bool "RA Flash MRAM driver" + depends on DT_HAS_RENESAS_RA_MRAM_CONTROLLER_ENABLED + default y + select FLASH_HAS_DRIVER_ENABLED + select FLASH_PAGE_LAYOUT + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_NO_EXPLICIT_ERASE + select USE_RA_FSP_MRAM + help + Enable Flash MRAM driver for RA series diff --git a/drivers/flash/soc_flash_renesas_ra_mram.c b/drivers/flash/soc_flash_renesas_ra_mram.c new file mode 100644 index 0000000000000..43c6042294cac --- /dev/null +++ b/drivers/flash/soc_flash_renesas_ra_mram.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DT_DRV_COMPAT renesas_ra_mram_controller + +LOG_MODULE_REGISTER(flash_renesas_ra_mram, CONFIG_FLASH_LOG_LEVEL); + +struct mram_renesas_ra_controller_data { + mram_instance_ctrl_t mram_controller; + struct st_flash_cfg f_config; + struct k_mutex code_mram_mtx; +}; + +struct mram_renesas_ra_config { + struct flash_parameters mram_parameters; + size_t erase_block_size; +#ifdef CONFIG_FLASH_PAGE_LAYOUT + struct flash_pages_layout device_page_layout; +#endif +}; + +struct mram_renesas_ra_data { + struct mram_renesas_ra_controller_data *controller_data; + uint32_t area_address; + uint32_t area_size; +}; + +static struct mram_renesas_ra_controller_data mram_controller_data = { + .f_config = { + .data_flash_bgo = false, + .irq = FSP_INVALID_VECTOR, + .err_irq = FSP_INVALID_VECTOR, + .ipl = BSP_IRQ_DISABLED, + .err_ipl = BSP_IRQ_DISABLED, + .p_callback = NULL, + }, +}; + +static bool mram_renesas_ra_valid_range(struct mram_renesas_ra_data *mram_data, off_t offset, + size_t len) +{ + if ((offset < 0) || (offset >= mram_data->area_size) || + (mram_data->area_size - offset < len) || (len > UINT32_MAX - offset)) { + return false; + } + + return true; +} + +static int mram_renesas_ra_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + struct mram_renesas_ra_data *mram_data = dev->data; + struct mram_renesas_ra_controller_data *ctrl_data = mram_data->controller_data; + + if (!len) { + return 0; + } + + if (!mram_renesas_ra_valid_range(mram_data, offset, len)) { + return -EINVAL; + } + + LOG_DBG("mram: read 0x%lx, len: %u", (long)(offset), len); + + k_mutex_lock(&ctrl_data->code_mram_mtx, K_FOREVER); + + memcpy(data, (uint8_t *)(offset + mram_data->area_address), len); + + k_mutex_unlock(&ctrl_data->code_mram_mtx); + + return 0; +} + +static int mram_renesas_ra_write(const struct device *dev, off_t offset, const void *data, + size_t len) +{ + struct mram_renesas_ra_data *mram_data = dev->data; + struct mram_renesas_ra_controller_data *ctrl_data = mram_data->controller_data; + fsp_err_t err; + + if (!len) { + return 0; + } + + if (!mram_renesas_ra_valid_range(mram_data, offset, len)) { + return -EINVAL; + } + + k_mutex_lock(&ctrl_data->code_mram_mtx, K_FOREVER); + + err = R_MRAM_Write(ctrl_data, (uint32_t)data, (uint32_t)(offset + mram_data->area_address), + len); + + k_mutex_unlock(&ctrl_data->code_mram_mtx); + + if (err != FSP_SUCCESS) { + return -EIO; + } + + return 0; +} + +static int mram_renesas_ra_erase(const struct device *dev, off_t offset, size_t size) +{ + const struct mram_renesas_ra_config *mram_config = dev->config; + struct mram_renesas_ra_data *mram_data = dev->data; + struct mram_renesas_ra_controller_data *ctrl_data = mram_data->controller_data; + fsp_err_t err; + uint32_t block_num; + + if (!size) { + return 0; + } + + if (!mram_renesas_ra_valid_range(mram_data, offset, size)) { + return -EINVAL; + } + + block_num = DIV_ROUND_UP(size, mram_config->erase_block_size); + + k_mutex_lock(&ctrl_data->code_mram_mtx, K_FOREVER); + + err = R_MRAM_Erase(ctrl_data, (uint32_t)(offset + mram_data->area_address), block_num); + + k_mutex_unlock(&ctrl_data->code_mram_mtx); + + if (err != FSP_SUCCESS) { + return -EIO; + } + + return 0; +} + +static const struct flash_parameters *mram_renesas_ra_get_parameters(const struct device *dev) +{ + const struct mram_renesas_ra_config *mram_config = dev->config; + + return &mram_config->mram_parameters; +} + +static int mram_renesas_ra_get_size(const struct device *dev, uint64_t *size) +{ + struct mram_renesas_ra_data *mram_data = dev->data; + + *size = (uint64_t)mram_data->area_size; + return 0; +} + +#ifdef CONFIG_FLASH_PAGE_LAYOUT + +void mram_renesas_ra_page_layout(const struct device *dev, const struct flash_pages_layout **layout, + size_t *layout_size) +{ + const struct mram_renesas_ra_config *mram_config = dev->config; + + *layout = &(mram_config->device_page_layout); + *layout_size = 1; +} + +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +static int mram_renesas_ra_controller_init(const struct device *dev) +{ + fsp_err_t err; + struct mram_renesas_ra_controller_data *data = dev->data; + + k_mutex_init(&data->code_mram_mtx); + + err = R_MRAM_Open(&data->mram_controller, &data->f_config); + + if (err != FSP_SUCCESS) { + LOG_DBG("flash: open error=%d", (int)err); + return -EIO; + } + + return 0; +} + +static int mram_renesas_ra_init(const struct device *dev) +{ + const struct device *dev_ctrl = DEVICE_DT_INST_GET(0); + struct mram_renesas_ra_data *mram_data = dev->data; + + if (!device_is_ready(dev_ctrl)) { + return -ENODEV; + } + + mram_data->controller_data = dev_ctrl->data; + + return 0; +} + +static DEVICE_API(flash, mram_renesas_ra_api) = { + .erase = mram_renesas_ra_erase, + .write = mram_renesas_ra_write, + .read = mram_renesas_ra_read, + .get_parameters = mram_renesas_ra_get_parameters, + .get_size = mram_renesas_ra_get_size, +#ifdef CONFIG_FLASH_PAGE_LAYOUT + .page_layout = mram_renesas_ra_page_layout, +#endif +}; + +#ifdef CONFIG_FLASH_PAGE_LAYOUT +#define MRAM_RENESAS_RA_INIT_DEVICE_PAGE_LAYOUT(index) \ + .device_page_layout = { \ + .pages_count = (DT_REG_SIZE(index) / DT_PROP(index, erase_block_size)), \ + .pages_size = DT_PROP(index, erase_block_size), \ + } +#else +#define MRAM_RENESAS_RA_INIT_DEVICE_PAGE_LAYOUT(index) +#endif + +#define MRAM_RENESAS_RA_INIT(index) \ + static struct mram_renesas_ra_data mram_renesas_ra_data_##index = { \ + .area_address = DT_REG_ADDR(index), \ + .area_size = DT_REG_SIZE(index), \ + }; \ + static const struct mram_renesas_ra_config mram_renesas_ra_config_##index = { \ + .mram_parameters = \ + { \ + .write_block_size = DT_PROP(index, write_block_size), \ + .erase_value = 0xff, \ + .caps = \ + { \ + .no_explicit_erase = true, \ + }, \ + }, \ + .erase_block_size = DT_PROP(index, erase_block_size), \ + MRAM_RENESAS_RA_INIT_DEVICE_PAGE_LAYOUT(index), \ + }; \ + \ + DEVICE_DT_DEFINE(index, mram_renesas_ra_init, NULL, &mram_renesas_ra_data_##index, \ + &mram_renesas_ra_config_##index, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, \ + &mram_renesas_ra_api); + +DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(0), MRAM_RENESAS_RA_INIT); + +DEVICE_DT_DEFINE(DT_DRV_INST(0), mram_renesas_ra_controller_init, NULL, &mram_controller_data, NULL, + PRE_KERNEL_1, CONFIG_FLASH_INIT_PRIORITY, NULL); diff --git a/dts/bindings/flash_controller/renesas,ra-mram-controller.yaml b/dts/bindings/flash_controller/renesas,ra-mram-controller.yaml new file mode 100644 index 0000000000000..201fe2b0a8b1a --- /dev/null +++ b/dts/bindings/flash_controller/renesas,ra-mram-controller.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA flash MRAM controller + +compatible: "renesas,ra-mram-controller" + +include: flash-controller.yaml diff --git a/dts/bindings/mtd/renesas,ra-nv-mram.yaml b/dts/bindings/mtd/renesas,ra-nv-mram.yaml new file mode 100644 index 0000000000000..35a7b60eb2317 --- /dev/null +++ b/dts/bindings/mtd/renesas,ra-nv-mram.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: MRAM memory binding of Renesas RA family + +include: [soc-nv-flash.yaml] + +compatible: "renesas,ra-nv-mram" + +properties: + reg: + required: true diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 67d944695cf29..4ba6ca802e546 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -65,6 +65,11 @@ config USE_RA_FSP_SCE help Enable RA FSP SCE driver +config USE_RA_FSP_MRAM + bool + help + Enable RA FSP MRAM driver + if USE_RA_FSP_SCE config HAS_RENESAS_RA_RSIP_E51A From c087e3398113d22d5bb7a902225c9382a7beaf39 Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Mon, 29 Sep 2025 10:10:40 +0000 Subject: [PATCH 2/5] dts: arm: renesas: ra: Add support MRAM node on SoC dts layer - Add support MRAM node on Renesas SoC dts layer for RA8P1, RA8T2 - Move the MRAM and SRAM resource defination to SoC dts layer Signed-off-by: Khoa Nguyen --- boards/renesas/ek_ra8p1/ek_ra8p1.dtsi | 22 ------------------ boards/renesas/mck_ra8t2/mck_ra8t2.dtsi | 7 ------ dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi | 27 +++++++++++++++++++++-- dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi | 11 +++++++++ dts/arm/renesas/ra/ra8/ra8x2.dtsi | 4 +++- 5 files changed, 39 insertions(+), 32 deletions(-) diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi b/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi index 864830fe7e9f6..656e4469d40c3 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi +++ b/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi @@ -113,28 +113,6 @@ }; }; -&flash { - flash0: flash@2000000 { - compatible = "soc-nv-flash"; - reg = <0x2000000 0x80000>; - }; - - flash1: flash@2080000 { - compatible = "soc-nv-flash"; - reg = <0x2080000 0x80000>; - }; -}; - -&sram { - sram0: sram@22000000 { - reg = <0x22000000 0xea000>; - }; - - sram1: sram@220ea000 { - reg = <0x220ea000 0xea000>; - }; -}; - &sciclk { clocks = <&pll2r>; div = <4>; diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi b/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi index 5b2e2c794aedf..81991345c1835 100644 --- a/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi +++ b/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi @@ -88,13 +88,6 @@ }; }; -&flash { - flash0: flash@2000000 { - compatible = "soc-nv-flash"; - reg = <0x2000000 DT_SIZE_K(1024)>; - }; -}; - &sciclk { status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi b/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi index 9bf599ae55018..80b50662bae1f 100644 --- a/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi +++ b/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi @@ -9,9 +9,32 @@ / { soc { - sram: memory@22000000 { + mram-controller@4013c000 { + code_mram_cm85: mram@2000000 { + compatible = "renesas,ra-nv-mram"; + reg = <0x2000000 DT_SIZE_K(768)>; + write-block-size = <1>; + erase-block-size = <32>; + }; + + code_mram_cm33: mram@20c0000 { + compatible = "renesas,ra-nv-mram"; + reg = <0x20c0000 DT_SIZE_K(256)>; + write-block-size = <1>; + erase-block-size = <32>; + }; + }; + + sram0: memory@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(1404)>; + #address-cells = <1>; + #size-cells = <1>; + }; + + sram1: memory@2215f000 { compatible = "mmio-sram"; - reg = <0x22000000 0x1d4000>; + reg = <0x2215f000 DT_SIZE_K(468)>; #address-cells = <1>; #size-cells = <1>; }; diff --git a/dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi b/dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi index 41fe9b850ec09..2d1c816d31a4f 100644 --- a/dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi +++ b/dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi @@ -8,9 +8,20 @@ / { soc { + mram-controller@4013c000 { + code_mram_cm85: mram@2000000 { + compatible = "renesas,ra-nv-mram"; + reg = <0x2000000 DT_SIZE_M(1)>; + write-block-size = <1>; + erase-block-size = <32>; + }; + }; + sram0: memory@22000000 { compatible = "mmio-sram"; reg = <0x22000000 DT_SIZE_K(1664)>; + #address-cells = <1>; + #size-cells = <1>; }; }; }; diff --git a/dts/arm/renesas/ra/ra8/ra8x2.dtsi b/dts/arm/renesas/ra/ra8/ra8x2.dtsi index 824abc36de1d1..4cd7145f9e1f3 100644 --- a/dts/arm/renesas/ra/ra8/ra8x2.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x2.dtsi @@ -73,10 +73,12 @@ status = "okay"; }; - flash: flash-controller@4013c000 { + mram: mram-controller@4013c000 { + compatible = "renesas,ra-mram-controller"; reg = <0x4013c000 0x4000>; #address-cells = <1>; #size-cells = <1>; + status = "okay"; }; ioport0: gpio@40400000 { From 82ef37a495cc981ca43bffb74ba17bd37c20664d Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Mon, 29 Sep 2025 10:15:41 +0000 Subject: [PATCH 3/5] boards: renesas: Update zephyr,flash to MRAM label Update zephyr,flash to MRAM label for ek_ra8p1 and mck_ra8t2 Signed-off-by: Khoa Nguyen --- boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts | 2 +- boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts | 2 +- boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts index acc440c91acca..2a3ef5e9a1a6e 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts @@ -14,7 +14,7 @@ chosen { zephyr,sram = &sram1; - zephyr,flash = &flash1; + zephyr,flash = &code_mram_cm33; zephyr,console = &uart9; zephyr,shell-uart = &uart9; }; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts index 065a2d492be0b..8b2508aab3101 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts @@ -15,7 +15,7 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &flash0; + zephyr,flash = &code_mram_cm85; zephyr,console = &uart8; zephyr,shell-uart = &uart8; }; diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts index 89f4e47c4934a..0452cd712d686 100644 --- a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts +++ b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts @@ -14,7 +14,7 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &flash0; + zephyr,flash = &code_mram_cm85; zephyr,console = &uart9; zephyr,shell-uart = &uart9; }; From 79ceb8bee536d34481f94d91a9f3746444c94e95 Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Mon, 29 Sep 2025 10:16:44 +0000 Subject: [PATCH 4/5] tests: drivers: flash: Add support flash/common to test MRAM Add support test app `flash/common` to test MRAM on Renesas ek_ra8p1, mck_ra8t2 Signed-off-by: Khoa Nguyen --- .../boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay | 17 +++++++++++++++++ .../boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay | 17 +++++++++++++++++ .../boards/mck_ra8t2_r7ka8t2lfecac_cm85.overlay | 17 +++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay create mode 100644 tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay create mode 100644 tests/drivers/flash/common/boards/mck_ra8t2_r7ka8t2lfecac_cm85.overlay diff --git a/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay b/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay new file mode 100644 index 0000000000000..00535b53a46e2 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&code_mram_cm33 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@48000 { + label = "storage"; + reg = <0x48000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay new file mode 100644 index 0000000000000..b4956f06463dc --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&code_mram_cm85 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@98000 { + label = "storage"; + reg = <0x98000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/tests/drivers/flash/common/boards/mck_ra8t2_r7ka8t2lfecac_cm85.overlay b/tests/drivers/flash/common/boards/mck_ra8t2_r7ka8t2lfecac_cm85.overlay new file mode 100644 index 0000000000000..b4956f06463dc --- /dev/null +++ b/tests/drivers/flash/common/boards/mck_ra8t2_r7ka8t2lfecac_cm85.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&code_mram_cm85 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@98000 { + label = "storage"; + reg = <0x98000 DT_SIZE_K(32)>; + }; + }; +}; From 8df36ad49d969be1dfb6b798065edec6f5377b46 Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Tue, 30 Sep 2025 02:51:12 +0000 Subject: [PATCH 5/5] samples: subsys: ipc: Update sram label for Renesas devices Update sram label for Renesas devices Signed-off-by: Khoa Nguyen --- .../ek_ra8p1_r7ka8p1kflcac_cm85.overlay | 38 +++++++++---------- .../ek_ra8p1_r7ka8p1kflcac_cm33.overlay | 38 +++++++++---------- .../ek_ra8p1_r7ka8p1kflcac_cm85.overlay | 38 +++++++++---------- .../ek_ra8p1_r7ka8p1kflcac_cm33.overlay | 38 +++++++++---------- .../ek_ra8p1_r7ka8p1kflcac_cm85.overlay | 26 ++++++------- .../ek_ra8p1_r7ka8p1kflcac_cm33.overlay | 26 ++++++------- 6 files changed, 100 insertions(+), 104 deletions(-) diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay index 6e2656911ffaa..f4fa6d84c025f 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -18,30 +18,30 @@ status = "okay"; }; }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: memory@22000000 { - reg = <0x22000000 0xe9800>; - }; + soc { + /* Redefine sram regions for CPU0 */ + sram0: memory@22000000 { + reg = <0x22000000 0xe9800>; + }; - /* Redefine sram regions for CPU1 */ - sram1: memory@220e9800 { - reg = <0x220e9800 0xe9800>; - }; + /* Redefine sram regions for CPU1 */ + sram1: memory@220e9800 { + reg = <0x220e9800 0xe9800>; + }; - /* Define shared memory regions for IPC */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + /* Define shared memory regions for IPC */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; - sram_rx: memory@221d3000 { - reg = <0x221d3000 0x800>; - }; + sram_rx: memory@221d3000 { + reg = <0x221d3000 0x800>; + }; - sram_tx: memory@221d3800 { - reg = <0x221d3800 0x800>; + sram_tx: memory@221d3800 { + reg = <0x221d3800 0x800>; + }; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay index 3a080c945a845..0ea1a787b8d98 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay @@ -18,30 +18,30 @@ status = "okay"; }; }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: memory@22000000 { - reg = <0x22000000 0xe9800>; - }; + soc { + /* Redefine sram regions for CPU0 */ + sram0: memory@22000000 { + reg = <0x22000000 0xe9800>; + }; - /* Redefine sram regions for CPU1 */ - sram1: memory@220e9800 { - reg = <0x220e9800 0xe9800>; - }; + /* Redefine sram regions for CPU1 */ + sram1: memory@220e9800 { + reg = <0x220e9800 0xe9800>; + }; - /* Define shared memory regions for IPC */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + /* Define shared memory regions for IPC */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; - sram_tx: memory@221d3000 { - reg = <0x221d3000 0x800>; - }; + sram_tx: memory@221d3000 { + reg = <0x221d3000 0x800>; + }; - sram_rx: memory@221d3800 { - reg = <0x221d3800 0x800>; + sram_rx: memory@221d3800 { + reg = <0x221d3800 0x800>; + }; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay index aa5f1209fc2d3..a2cf4ffec6bf4 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -30,30 +30,30 @@ status = "okay"; }; }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: memory@22000000 { - reg = <0x22000000 0xe2000>; - }; + soc { + /* Redefine sram regions for CPU0 */ + sram0: memory@22000000 { + reg = <0x22000000 0xe2000>; + }; - /* Redefine sram regions for CPU1 */ - sram1: memory@220e2000 { - reg = <0x220e2000 0xe2000>; - }; + /* Redefine sram regions for CPU1 */ + sram1: memory@220e2000 { + reg = <0x220e2000 0xe2000>; + }; - /* Define shared memory regions for IPC */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + /* Define shared memory regions for IPC */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; - sram_ipc0: memory@221c4000 { - reg = <0x221c4000 0x8000>; - }; + sram_ipc0: memory@221c4000 { + reg = <0x221c4000 0x8000>; + }; - sram_ipc1: memory@221cc000 { - reg = <0x221cc000 0x8000>; + sram_ipc1: memory@221cc000 { + reg = <0x221cc000 0x8000>; + }; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay index 9259db35c88bc..bd74e0ba078b7 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay @@ -30,30 +30,30 @@ status = "okay"; }; }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: memory@22000000 { - reg = <0x22000000 0xe2000>; - }; + soc { + /* Redefine sram regions for CPU0 */ + sram0: memory@22000000 { + reg = <0x22000000 0xe2000>; + }; - /* Redefine sram regions for CPU1 */ - sram1: memory@220e2000 { - reg = <0x220e2000 0xe2000>; - }; + /* Redefine sram regions for CPU1 */ + sram1: memory@220e2000 { + reg = <0x220e2000 0xe2000>; + }; - /* Define shared memory regions for IPC */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + /* Define shared memory regions for IPC */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; - sram_ipc0: memory@221c4000 { - reg = <0x221c4000 0x8000>; - }; + sram_ipc0: memory@221c4000 { + reg = <0x221c4000 0x8000>; + }; - sram_ipc1: memory@221cc000 { - reg = <0x221cc000 0x8000>; + sram_ipc1: memory@221cc000 { + reg = <0x221cc000 0x8000>; + }; }; }; }; diff --git a/samples/subsys/ipc/openamp/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/samples/subsys/ipc/openamp/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay index a4eb553d97e13..38ab5b243e7ee 100644 --- a/samples/subsys/ipc/openamp/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay +++ b/samples/subsys/ipc/openamp/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -23,23 +23,21 @@ mbox-names = "tx", "rx"; status = "okay"; }; - }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: sram@22000000 { - reg = <0x22000000 0xe6000>; - }; + /* Redefine sram regions for CPU0 */ + sram0: sram@22000000 { + reg = <0x22000000 0xe6000>; + }; - /* Redefine sram regions for CPU1 */ - sram1: sram@220e6000 { - reg = <0x220e6000 0xe6000>; - }; + /* Redefine sram regions for CPU1 */ + sram1: sram@220e6000 { + reg = <0x220e6000 0xe6000>; + }; - /* Define shared memory regions for IPC */ - sram_shm: sram@221cc000 { - reg = <0x221cc000 0x8000>; + /* Define shared memory regions for IPC */ + sram_shm: sram@221cc000 { + reg = <0x221cc000 0x8000>; + }; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay b/samples/subsys/ipc/openamp/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay index 8b43265bd7a53..397c0283af722 100644 --- a/samples/subsys/ipc/openamp/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/ek_ra8p1_r7ka8p1kflcac_cm33.overlay @@ -23,23 +23,21 @@ mbox-names = "rx", "tx"; status = "okay"; }; - }; -}; -&sram { - /* Redefine sram regions for CPU0 */ - sram0: sram@22000000 { - reg = <0x22000000 0xe6000>; - }; + /* Redefine sram regions for CPU0 */ + sram0: sram@22000000 { + reg = <0x22000000 0xe6000>; + }; - /* Redefine sram regions for CPU1 */ - sram1: sram@220e6000 { - reg = <0x220e6000 0xe6000>; - }; + /* Redefine sram regions for CPU1 */ + sram1: sram@220e6000 { + reg = <0x220e6000 0xe6000>; + }; - /* Define shared memory regions for IPC */ - sram_shm: sram@221cc000 { - reg = <0x221cc000 0x8000>; + /* Define shared memory regions for IPC */ + sram_shm: sram@221cc000 { + reg = <0x221cc000 0x8000>; + }; }; };