diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml index d155aa70ad168..b0093283639b9 100644 --- a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml @@ -12,6 +12,7 @@ supported: - adc - i2c - counter + - dma testing: ignore_tags: - bluetooth diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml index 79b273a75e30f..616985615d0a9 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml @@ -11,4 +11,5 @@ supported: - adc - i2c - counter + - dma vendor: renesas diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml index a8eaf76442a24..c55ba3ba77968 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml @@ -16,4 +16,5 @@ supported: - adc - i2c - counter + - dma vendor: renesas diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml index b69c99cd18550..1c091bfd3435d 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml @@ -13,4 +13,5 @@ supported: - i2c - counter - mbox + - dma vendor: renesas diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt index 39fe4599ad239..02832fca6ac5a 100644 --- a/drivers/dma/CMakeLists.txt +++ b/drivers/dma/CMakeLists.txt @@ -35,7 +35,8 @@ zephyr_library_sources_ifdef(CONFIG_DMA_MCHP_XEC dma_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_DMA_XMC4XXX dma_xmc4xxx.c) zephyr_library_sources_ifdef(CONFIG_DMA_RPI_PICO dma_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_DMA_RENESAS_RA dma_renesas_ra.c) -zephyr_library_sources_ifdef(CONFIG_DMA_RENESAS_RZ dma_renesas_rz.c) +zephyr_library_sources_ifdef(CONFIG_DMA_RENESAS_RZ_DMAC dma_renesas_rz.c) +zephyr_library_sources_ifdef(CONFIG_DMA_RENESAS_RZ_DMAC_B dma_renesas_rz.c) zephyr_library_sources_ifdef(CONFIG_MCUX_PXP dma_mcux_pxp.c) zephyr_library_sources_ifdef(CONFIG_DMA_MAX32 dma_max32.c) zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_SMARTDMA dma_mcux_smartdma.c) diff --git a/drivers/dma/Kconfig.renesas_rz b/drivers/dma/Kconfig.renesas_rz index fd40f348ace6b..c5a15b2628b4a 100644 --- a/drivers/dma/Kconfig.renesas_rz +++ b/drivers/dma/Kconfig.renesas_rz @@ -1,10 +1,18 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -config DMA_RENESAS_RZ +config DMA_RENESAS_RZ_DMAC bool "Renesas RZ DMAC" default y - depends on DT_HAS_RENESAS_RZ_DMA_ENABLED - select USE_RZ_FSP_DMA + depends on DT_HAS_RENESAS_RZ_DMAC_ENABLED + select USE_RZ_FSP_DMAC help - Enable Renesas RZ DMA Driver. + Enable Renesas RZ DMAC Driver. + +config DMA_RENESAS_RZ_DMAC_B + bool "Renesas RZ DMAC_B" + default y + depends on DT_HAS_RENESAS_RZ_DMAC_B_ENABLED + select USE_RZ_FSP_DMAC_B + help + Enable Renesas RZ DMAC_B Driver. diff --git a/drivers/dma/dma_renesas_rz.c b/drivers/dma/dma_renesas_rz.c index 258561ae95edf..020f0de9306e6 100644 --- a/drivers/dma/dma_renesas_rz.c +++ b/drivers/dma/dma_renesas_rz.c @@ -1,19 +1,69 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT renesas_rz_dma +#define DT_DRV_COMPAT renesas_rz_dmac_b #include -#include "r_dmac_b.h" #include #include "dma_renesas_rz.h" -LOG_MODULE_REGISTER(renesas_rz_dma); -/* FSP DMAC handler should be called within DMA ISR */ -void dmac_b_int_isr(void); -void dmac_b_err_isr(void); +#ifdef CONFIG_CPU_CORTEX_A +#include +#endif /* CONFIG_CPU_CORTEX_A */ + +#ifdef CONFIG_USE_RZ_FSP_DMAC_B +#include "r_dmac_b.h" + +static const transfer_api_t *const rz_g_transfer_on_dma = &g_transfer_on_dmac_b; +#define dma_instance_ctrl_t dmac_b_instance_ctrl_t +#define dma_extended_cfg_t dmac_b_extended_cfg_t +#define dma_callback_args_t dmac_b_callback_args_t +#define dma_extended_info_t dmac_b_extended_info_t + +void dmac_b_int_isr(void *irq); +void dmac_b_err_isr(void *irq); +#define RZ_DMA_INT_ISR(irq) dmac_b_int_isr((void *)irq) +#define RZ_DMA_ERR_ISR(irq) dmac_b_err_isr((void *)irq) + +#else /* CONFIG_USE_RZ_FSP_DMAC */ +#include "r_dmac.h" + +static const transfer_api_t *const rz_g_transfer_on_dma = &g_transfer_on_dmac; +#define dma_instance_ctrl_t dmac_instance_ctrl_t +#define dma_extended_cfg_t dmac_extended_cfg_t + +#ifdef CONFIG_CPU_CORTEX_A +#define dma_callback_args_t dmac_callback_args_t +#define dma_extended_info_t dmac_extended_info_t +void dmac_err_isr(void *irq); +#define RZ_DMA_ERR_ISR(irq) dmac_err_isr((void *)irq) +#else /* CONFIG_CPU_AARCH32_CORTEX_R */ +#define dma_callback_args_t transfer_callback_args_t + +#define RZ_MASTER_MPU_STADD_DISABLE_RW_PROTECTION (0x00000000) +#define RZ_MASTER_MPU_ENDADD_DISABLE_RW_PROTECTION (0x00000C00) +#endif /* CONFIG_CPU_CORTEX_A */ + +void dmac_int_isr(void *irq); +#define RZ_DMA_INT_ISR(irq) dmac_int_isr((void *)irq) + +#endif /* CONFIG_USE_RZ_FSP_DMAC_B */ + +#define RZ_DMA_CHANNEL_SCHEDULING_FIXED 0 +#define RZ_DMA_CHANNEL_SCHEDULING_ROUND_ROBIN 1 +#define RZ_DMA_MODE_SELECT_REGISTER 0 +#define RZ_DMA_MODE_SELECT_LINK 1 +#define RZ_DMA_ACK_MODE_MASK_DACK_OUTPUT 4 + +#define RZ_DMA_REQUEST_DIRECTION_SOURCE_MODULE 0 +#define RZ_DMA_REQUEST_DIRECTION_DESTINATION_MODULE 1 + +#define RZ_DMA_GRP_CH_CHCTRL_SETSUS_Msk (0x100UL) +#define RZ_DMA_GRP_CH_CHCTRL_CLRSUS_Msk (0x200UL) + +LOG_MODULE_REGISTER(renesas_rz_dma); struct dmac_cb_ctx { const struct device *dmac_dev; @@ -48,9 +98,18 @@ struct dma_renesas_rz_data { /* Dma context should be the first in data structure */ struct dma_context ctx; struct dma_channel_data *channels; + + uint32_t curr_channel; +#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) +#ifdef CONFIG_DMA_64BIT + uint64_t err_irq; +#else /* !CONFIG_DMA_64BIT */ + uint32_t err_irq; +#endif /* CONFIG_DMA_64BIT */ +#endif /* defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) */ }; -static void dmac_rz_cb_handler(dmac_b_callback_args_t *args) +static void dma_rz_cb_handler(dma_callback_args_t *args) { struct dmac_cb_ctx *cb_ctx = (struct dmac_cb_ctx *)args->p_context; uint32_t channel = cb_ctx->channel; @@ -60,7 +119,7 @@ static void dmac_rz_cb_handler(dmac_b_callback_args_t *args) void *user_data = data->channels[channel].user_data; if (user_cb) { - user_cb(dev, user_data, channel, args->event); + user_cb(dev, user_data, channel, DMA_STATUS_COMPLETE); } } @@ -97,13 +156,13 @@ static inline int dma_channel_config_check_parameters(const struct device *dev, } if (cfg->source_chaining_en || cfg->dest_chaining_en) { - LOG_ERR("%d:Channel Chainning is not supported.", __LINE__); + LOG_ERR("%d:Channel chaining is not supported.", __LINE__); return -ENOTSUP; } if (cfg->head_block->dest_scatter_count || cfg->head_block->source_gather_count || cfg->head_block->source_gather_interval || cfg->head_block->dest_scatter_interval) { - LOG_ERR("%d: Scater and gather are not supported.", __LINE__); + LOG_ERR("%d: Scatter and gather are not supported.", __LINE__); return -ENOTSUP; } @@ -127,15 +186,6 @@ static int dma_channel_set_size(uint32_t size) case 8: transfer_size = TRANSFER_SIZE_8_BYTE; break; - case 32: - transfer_size = TRANSFER_SIZE_32_BYTE; - break; - case 64: - transfer_size = TRANSFER_SIZE_64_BYTE; - break; - case 128: - transfer_size = TRANSFER_SIZE_128_BYTE; - break; default: LOG_ERR("%d: Unsupported data width.", __LINE__); return -ENOTSUP; @@ -147,60 +197,128 @@ static int dma_channel_set_size(uint32_t size) static inline int dma_channel_config_save_parameters(const struct device *dev, uint32_t channel, struct dma_config *cfg) { - const struct dma_renesas_rz_config *config = dev->config; struct dma_renesas_rz_data *data = dev->data; transfer_info_t *p_info = data->channels[channel].fsp_cfg.p_info; - dmac_b_extended_cfg_t *p_extend = - (dmac_b_extended_cfg_t *)data->channels[channel].fsp_cfg.p_extend; + dma_extended_cfg_t *p_extend = + (dma_extended_cfg_t *)data->channels[channel].fsp_cfg.p_extend; + transfer_addr_mode_t src_transfer_addr_mode; + transfer_addr_mode_t dest_transfer_addr_mode; - memset(p_info, 0, sizeof(*p_info)); - memset(p_extend, 0, sizeof(*p_extend)); + transfer_mode_t transfer_mode; + bool activation_with_software_trigger; /* Save transfer properties required by FSP */ switch (cfg->head_block->dest_addr_adj) { case DMA_ADDR_ADJ_NO_CHANGE: - p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + dest_transfer_addr_mode = TRANSFER_ADDR_MODE_FIXED; break; case DMA_ADDR_ADJ_INCREMENT: - p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + dest_transfer_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; break; default: - LOG_ERR("%d, Unsupported destination address adjustemnt.", __LINE__); + LOG_ERR("%d, Unsupported destination address adjustment.", __LINE__); return -ENOTSUP; } switch (cfg->head_block->source_addr_adj) { case DMA_ADDR_ADJ_NO_CHANGE: - p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + src_transfer_addr_mode = TRANSFER_ADDR_MODE_FIXED; break; case DMA_ADDR_ADJ_INCREMENT: - p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + src_transfer_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + break; + default: + LOG_ERR("%d, Unsupported source address adjustment.", __LINE__); + return -ENOTSUP; + } + + switch (cfg->channel_direction) { + case MEMORY_TO_MEMORY: + transfer_mode = TRANSFER_MODE_BLOCK; + p_extend->activation_request_source_select = + RZ_DMA_REQUEST_DIRECTION_DESTINATION_MODULE; + activation_with_software_trigger = true; + break; + case PERIPHERAL_TO_MEMORY: + transfer_mode = TRANSFER_MODE_NORMAL; + p_extend->activation_request_source_select = + RZ_DMA_REQUEST_DIRECTION_DESTINATION_MODULE; + activation_with_software_trigger = false; + break; + case MEMORY_TO_PERIPHERAL: + transfer_mode = TRANSFER_MODE_NORMAL; + p_extend->activation_request_source_select = RZ_DMA_REQUEST_DIRECTION_SOURCE_MODULE; + activation_with_software_trigger = false; break; default: - LOG_ERR("%d, Unsupported source address adjustemnt.", __LINE__); + LOG_ERR("%d: Unsupported direction mode.", __LINE__); + return -ENOTSUP; + } + +#ifdef CONFIG_CPU_CORTEX_A + dma_extended_info_t *p_extend_info = (dma_extended_info_t *)p_info->p_extend_info; + + p_extend->continuous_setting = DMAC_CONTINUOUS_SETTING_TRANSFER_NEXT0_ONCE; + + p_extend->detection_mode = DMAC_DETECTION_RISING_EDGE; + + if (cfg->head_block->block_size > UINT16_MAX) { + LOG_ERR("Larger than max block size"); return -ENOTSUP; } + /* Convert data size following FSP convention */ + p_extend_info->src_size = dma_channel_set_size(cfg->source_data_size); + p_extend_info->dest_size = dma_channel_set_size(cfg->dest_data_size); + + p_info->transfer_settings_word_b.dest_addr_mode = dest_transfer_addr_mode; + p_info->transfer_settings_word_b.src_addr_mode = src_transfer_addr_mode; + p_info->transfer_settings_word_b.mode = transfer_mode; + + p_extend->activation_source = activation_with_software_trigger + ? DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER + : cfg->dma_slot; + +#else /* CONFIG_CPU_CORTEX_M || CONFIG_CPU_AARCH32_CORTEX_R */ + const struct dma_renesas_rz_config *config = dev->config; + + p_extend->unit = config->unit; + /* Convert data size following FSP convention */ p_info->src_size = dma_channel_set_size(cfg->source_data_size); p_info->dest_size = dma_channel_set_size(cfg->dest_data_size); - /* Save transfer properties required by FSP */ - p_info->p_src = (void const *volatile)cfg->head_block->source_address; - p_info->p_dest = (void *volatile)cfg->head_block->dest_address; - p_info->length = cfg->head_block->block_size; - - /* - * Properties of next 1 registers are assigned default value following FSP because transfer - * continuous is not supported. - */ p_info->p_next1_src = NULL; p_info->p_next1_dest = NULL; p_info->next1_length = 1; + + p_info->dest_addr_mode = dest_transfer_addr_mode; + p_info->src_addr_mode = src_transfer_addr_mode; + p_info->mode = transfer_mode; + +#ifdef CONFIG_CPU_CORTEX_M p_extend->continuous_setting = DMAC_B_CONTINUOUS_SETTING_TRANSFER_ONCE; - /* Save DMAC properties required by FSP */ - p_extend->unit = config->unit; + p_extend->external_detection_mode = DMAC_B_EXTERNAL_DETECTION_NO_DETECTION; + p_extend->internal_detection_mode = DMAC_B_INTERNAL_DETECTION_NO_DETECTION; + + p_extend->activation_source = activation_with_software_trigger + ? DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER + : cfg->dma_slot; + +#else /* CONFIG_CPU_AARCH32_CORTEX_R */ + p_extend->activation_source = + activation_with_software_trigger ? ELC_EVENT_NONE : cfg->dma_slot; +#endif + +#endif + + p_extend->ack_mode = RZ_DMA_ACK_MODE_MASK_DACK_OUTPUT; + /* Save transfer properties required by FSP */ + p_info->p_src = (void const *volatile)cfg->head_block->source_address; + p_info->p_dest = (void *volatile)cfg->head_block->dest_address; + p_info->length = cfg->head_block->block_size; + p_extend->channel = channel; /* Save INTID and priority */ @@ -212,38 +330,9 @@ static inline int dma_channel_config_save_parameters(const struct device *dev, u data->channels[channel].user_data = cfg->user_data; data->channels[channel].cb_ctx.dmac_dev = dev; data->channels[channel].cb_ctx.channel = channel; - p_extend->p_callback = dmac_rz_cb_handler; + p_extend->p_callback = dma_rz_cb_handler; p_extend->p_context = (void *)&data->channels[channel].cb_ctx; - /* Save default value following FSP version */ - p_extend->ack_mode = DMAC_B_ACK_MODE_MASK_DACK_OUTPUT; - p_extend->external_detection_mode = DMAC_B_EXTERNAL_DETECTION_NO_DETECTION; - p_extend->internal_detection_mode = DMAC_B_INTERNAL_DETECTION_NO_DETECTION; - - /* Save properties with respect to a specific case */ - switch (cfg->channel_direction) { - case MEMORY_TO_MEMORY: - p_info->mode = TRANSFER_MODE_BLOCK; - p_extend->activation_request_source_select = - DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE; - p_extend->activation_source = DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER; - break; - case PERIPHERAL_TO_MEMORY: - p_info->mode = TRANSFER_MODE_NORMAL; - p_extend->activation_request_source_select = - DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE; - p_extend->activation_source = cfg->dma_slot; - break; - case MEMORY_TO_PERIPHERAL: - p_info->mode = TRANSFER_MODE_NORMAL; - p_extend->activation_request_source_select = DMAC_B_REQUEST_DIRECTION_SOURCE_MODULE; - p_extend->activation_source = cfg->dma_slot; - break; - default: - LOG_ERR("%d: Unsupported direction mode.", __LINE__); - return -ENOTSUP; - } - data->channels[channel].direction = cfg->channel_direction; /* @@ -251,15 +340,15 @@ static inline int dma_channel_config_save_parameters(const struct device *dev, u * Priority, Round Robin otherwise. */ if (cfg->channel_priority == 0) { - p_extend->channel_scheduling = DMAC_B_CHANNEL_SCHEDULING_FIXED; + p_extend->channel_scheduling = RZ_DMA_CHANNEL_SCHEDULING_FIXED; } else { - p_extend->channel_scheduling = DMAC_B_CHANNEL_SCHEDULING_ROUND_ROBIN; + p_extend->channel_scheduling = RZ_DMA_CHANNEL_SCHEDULING_ROUND_ROBIN; } if (1 < cfg->block_count) { LOG_ERR("%d: Link Mode is not supported.", __LINE__); } else { - p_extend->dmac_mode = DMAC_B_MODE_SELECT_REGISTER; + p_extend->dmac_mode = RZ_DMA_MODE_SELECT_REGISTER; } return 0; @@ -309,16 +398,24 @@ static int dma_renesas_rz_suspend(const struct device *dev, uint32_t channel) return ret; } - dmac_b_instance_ctrl_t *p_ctrl = (dmac_b_instance_ctrl_t *)data->channels[channel].fsp_ctrl; + dma_instance_ctrl_t *p_ctrl = (dma_instance_ctrl_t *)data->channels[channel].fsp_ctrl; - uint8_t group = DMA_PRV_GROUP(channel); - uint8_t prv_channel = DMA_PRV_CHANNEL(channel); +#ifdef CONFIG_CPU_CORTEX_A + /* Set transfer status is suspend */ + p_ctrl->p_reg->CHCTRL = RZ_DMA_GRP_CH_CHCTRL_SETSUS_Msk; + + /* Check whether a transfer is suspended. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CHSTAT_b.SUS, 1); +#else /* CONFIG_CPU_CORTEX_M || CONFIG_CPU_AARCH32_CORTEX_R */ + uint8_t group = RZ_DMA_PRV_GROUP(channel); + uint8_t prv_channel = RZ_DMA_PRV_CHANNEL(channel); /* Set transfer status is suspend */ - p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Msk; + p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL = RZ_DMA_GRP_CH_CHCTRL_SETSUS_Msk; /* Check whether a transfer is suspended. */ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS, 1); +#endif return 0; } @@ -333,10 +430,20 @@ static int dma_renesas_rz_resume(const struct device *dev, uint32_t channel) return ret; } - dmac_b_instance_ctrl_t *p_ctrl = (dmac_b_instance_ctrl_t *)data->channels[channel].fsp_ctrl; + dma_instance_ctrl_t *p_ctrl = (dma_instance_ctrl_t *)data->channels[channel].fsp_ctrl; + +#ifdef CONFIG_CPU_CORTEX_A + /* Check whether a transfer is suspended. */ + if (0 == p_ctrl->p_reg->CHSTAT_b.SUS) { + LOG_ERR("%d: DMA channel not suspend.", channel); + return -EINVAL; + } - uint8_t group = DMA_PRV_GROUP(channel); - uint8_t prv_channel = DMA_PRV_CHANNEL(channel); + /* Restore transfer status from suspend */ + p_ctrl->p_reg->CHCTRL |= RZ_DMA_GRP_CH_CHCTRL_CLRSUS_Msk; +#else /* CONFIG_CPU_CORTEX_M || CONFIG_CPU_AARCH32_CORTEX_R */ + uint8_t group = RZ_DMA_PRV_GROUP(channel); + uint8_t prv_channel = RZ_DMA_PRV_CHANNEL(channel); /* Check whether a transfer is suspended. */ if (0 == p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS) { @@ -345,7 +452,8 @@ static int dma_renesas_rz_resume(const struct device *dev, uint32_t channel) } /* Restore transfer status from suspend */ - p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL |= R_DMAC_B0_GRP_CH_CHCTRL_CLRSUS_Msk; + p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL |= RZ_DMA_GRP_CH_CHCTRL_CLRSUS_Msk; +#endif return 0; } @@ -376,8 +484,7 @@ static int dma_renesas_rz_start(const struct device *dev, uint32_t channel) { const struct dma_renesas_rz_config *config = dev->config; struct dma_renesas_rz_data *data = dev->data; - dmac_b_extended_cfg_t const *p_extend; - + dma_extended_cfg_t const *p_extend; int ret = dma_channel_common_checks(dev, channel); if (ret) { @@ -393,8 +500,21 @@ static int dma_renesas_rz_start(const struct device *dev, uint32_t channel) ret); return -EIO; } + data->curr_channel = channel; + +#ifdef CONFIG_CPU_CORTEX_A + /* Ensure cache coherency before starting DMA */ + transfer_info_t *p_info = data->channels[channel].fsp_cfg.p_info; + + sys_cache_data_flush_range((void *)p_info->p_src, p_info->length); + sys_cache_data_flush_range((void *)p_info->p_dest, p_info->length); +#endif /* CONFIG_CPU_CORTEX_A */ +#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) if (DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER == p_extend->activation_source) { +#else /* CONFIG_CPU_AARCH32_CORTEX_R */ + if (ELC_EVENT_NONE == p_extend->activation_source) { +#endif /* defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) */ ret = config->fsp_api->softwareStart(data->channels[channel].fsp_ctrl, (transfer_start_mode_t)NULL); @@ -407,8 +527,9 @@ static int dma_renesas_rz_start(const struct device *dev, uint32_t channel) return 0; } -static int dma_renesas_rz_config(const struct device *dev, uint32_t channel, - struct dma_config *dma_cfg) + +static int dma_renesas_rz_configure(const struct device *dev, uint32_t channel, + struct dma_config *dma_cfg) { const struct dma_renesas_rz_config *config = dev->config; struct dma_renesas_rz_data *data = dev->data; @@ -433,8 +554,7 @@ static int dma_renesas_rz_config(const struct device *dev, uint32_t channel, channel_cfg = &data->channels[channel]; - /* To avoid assertions we should first close the driver instance if already enabled - */ + /* To avoid assertions we should first close the driver instance if already enabled */ if (data->channels[channel].is_configured) { config->fsp_api->close(channel_cfg->fsp_ctrl); } @@ -448,11 +568,17 @@ static int dma_renesas_rz_config(const struct device *dev, uint32_t channel, } /* Mark that requested channel is configured successfully. */ data->channels[channel].is_configured = true; + return 0; } +#ifdef CONFIG_DMA_64BIT +static int dma_renesas_rz_reload(const struct device *dev, uint32_t channel, uint64_t src, + uint64_t dst, size_t size) +#else /* !CONFIG_DMA_64BIT */ static int dma_renesas_rz_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst, size_t size) +#endif /* CONFIG_DMA_64BIT */ { const struct dma_renesas_rz_config *config = dev->config; struct dma_renesas_rz_data *data = dev->data; @@ -464,7 +590,7 @@ static int dma_renesas_rz_reload(const struct device *dev, uint32_t channel, uin } if (size == 0) { - LOG_ERR("%d: Size must to not equal to 0 %d.", __LINE__, size); + LOG_ERR("%d: Size must to not equal to 0.", __LINE__); return -EINVAL; } @@ -499,7 +625,7 @@ static int dma_renesas_rz_get_attribute(const struct device *dev, uint32_t type, return -ENOSYS; case DMA_ATTR_MAX_BLOCK_COUNT: /* - * this is restricted to 1 because SG and Link Mode configurations are not + * This is restricted to 1 because SG and Link Mode configurations are not * supported */ *val = 1; @@ -507,6 +633,7 @@ static int dma_renesas_rz_get_attribute(const struct device *dev, uint32_t type, default: return -EINVAL; } + return 0; } @@ -519,10 +646,11 @@ static bool dma_renesas_rz_channel_filter(const struct device *dev, int channel, if (channel >= config->num_channels) { LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel); - return -EINVAL; + return false; } irq_enable(data->channels[channel].irq); + /* All DMA channels support triggered by periodic sources so always return true */ return true; } @@ -535,6 +663,7 @@ static void dma_renesas_rz_channel_release(const struct device *dev, uint32_t ch if (channel >= config->num_channels) { LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel); + return; } irq_disable(data->channels[channel].irq); @@ -548,7 +677,7 @@ static void dma_renesas_rz_channel_release(const struct device *dev, uint32_t ch static DEVICE_API(dma, dma_api) = { .reload = dma_renesas_rz_reload, - .config = dma_renesas_rz_config, + .config = dma_renesas_rz_configure, .start = dma_renesas_rz_start, .stop = dma_renesas_rz_stop, .suspend = dma_renesas_rz_suspend, @@ -565,61 +694,103 @@ static int renesas_rz_dma_init(const struct device *dev) config->irq_configure(); +#ifdef CONFIG_CPU_AARCH32_CORTEX_R + uint8_t region_num = BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE == 1 ? 8 : 16; + + /* Disable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM); + + if (config->unit == 0) { + for (uint8_t i = 0; i < region_num; i++) { + R_MPU0->RGN[i].STADD = RZ_MASTER_MPU_STADD_DISABLE_RW_PROTECTION; + R_MPU0->RGN[i].ENDADD = RZ_MASTER_MPU_ENDADD_DISABLE_RW_PROTECTION; + } + } + if (config->unit == 1) { + for (uint8_t i = 0; i < region_num; i++) { + R_MPU1->RGN[i].STADD = RZ_MASTER_MPU_STADD_DISABLE_RW_PROTECTION; + R_MPU1->RGN[i].ENDADD = RZ_MASTER_MPU_ENDADD_DISABLE_RW_PROTECTION; + } + } + + /* Enable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM); +#endif /* CONFIG_CPU_AARCH32_CORTEX_R */ + return 0; } -static void dmac_err_isr(const void *arg) +static void rz_dma_int_isr(const struct device *dev) { - ARG_UNUSED(arg); + struct dma_renesas_rz_data *data = dev->data; + dma_extended_cfg_t *p_extend = + (dma_extended_cfg_t *)data->channels[data->curr_channel].fsp_cfg.p_extend; + +#ifdef CONFIG_CPU_CORTEX_A + transfer_info_t *p_info = data->channels[data->curr_channel].fsp_cfg.p_info; - /* Call FSP DMAC ERR ISR */ - dmac_b_err_isr(); + sys_cache_data_invd_range((void *)p_info->p_dest, p_info->length); +#endif /* CONFIG_CPU_CORTEX_A */ + + RZ_DMA_INT_ISR(p_extend->dmac_int_irq); } -static void dmac_irq_isr(const void *arg) +#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) +static void rz_dma_err_isr(const struct device *dev) { - ARG_UNUSED(arg); + struct dma_renesas_rz_data *data = dev->data; - /* Call FSP DMAC ISR */ - dmac_b_int_isr(); + RZ_DMA_ERR_ISR(data->err_irq); } -#define IRQ_ERR_CONFIGURE(inst, name) \ +#define RZ_DMA_DATA_STRUCT_GET_ERR_IRQ(inst, err_name) \ + .err_irq = DT_INST_IRQ_BY_NAME(inst, err_name, irq), +#else /* CONFIG_CPU_AARCH32_CORTEX_R */ +#define RZ_DMA_DATA_STRUCT_GET_ERR_IRQ(inst, err_name) +#endif /* defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) */ + +#define RZ_DMA_IRQ_ERR_CONFIGURE(inst, name) \ IRQ_CONNECT( \ DT_INST_IRQ_BY_NAME(inst, name, irq), DT_INST_IRQ_BY_NAME(inst, name, priority), \ - dmac_err_isr, DEVICE_DT_INST_GET(inst), \ - COND_CODE_1(DT_IRQ_HAS_CELL_AT_NAME(DT_DRV_INST(inst), name, flags), \ + rz_dma_err_isr, DEVICE_DT_INST_GET(inst), \ + COND_CODE_1(DT_IRQ_HAS_CELL_AT_NAME(DT_DRV_INST(inst), name, flags), \ (DT_INST_IRQ_BY_NAME(inst, name, flags)), (0))); \ irq_enable(DT_INST_IRQ_BY_NAME(inst, name, irq)); -#define IRQ_CONFIGURE(n, inst) \ +#define RZ_DMA_IRQ_CONFIGURE(n, inst) \ IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, n, irq), DT_INST_IRQ_BY_IDX(inst, n, priority), \ - dmac_irq_isr, DEVICE_DT_INST_GET(inst), \ + rz_dma_int_isr, DEVICE_DT_INST_GET(inst), \ COND_CODE_1(DT_IRQ_HAS_CELL_AT_IDX(DT_DRV_INST(inst), n, flags), \ (DT_INST_IRQ_BY_IDX(inst, n, flags)), (0))); -#define CONFIGURE_ALL_IRQS(inst, n) LISTIFY(n, IRQ_CONFIGURE, (), inst) +#define RZ_DMA_CONFIGURE_ALL_IRQS(inst, n) LISTIFY(n, RZ_DMA_IRQ_CONFIGURE, (), inst) + +#define RZ_DMA_GET_UNIT(inst) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, dma_unit), \ + (DT_INST_PROP(inst, dma_unit)), (0)) #define DMA_RZ_INIT(inst) \ static void dma_rz_##inst##_irq_configure(void) \ { \ - CONFIGURE_ALL_IRQS(inst, DT_INST_PROP(inst, dma_channels)); \ - COND_CODE_1(DT_INST_IRQ_HAS_NAME(inst, err1), \ - (IRQ_ERR_CONFIGURE(inst, err1)), ()) \ + RZ_DMA_CONFIGURE_ALL_IRQS(inst, DT_INST_PROP(inst, dma_channels)); \ + COND_CODE_1(DT_INST_IRQ_HAS_NAME(inst, err1), \ + (RZ_DMA_IRQ_ERR_CONFIGURE(inst, err1)), ()) \ } \ \ static const struct dma_renesas_rz_config dma_renesas_rz_config_##inst = { \ - .unit = inst, \ + .unit = RZ_DMA_GET_UNIT(inst), \ .num_channels = DT_INST_PROP(inst, dma_channels), \ .irq_configure = dma_rz_##inst##_irq_configure, \ - .fsp_api = &g_transfer_on_dmac_b}; \ + .fsp_api = rz_g_transfer_on_dma}; \ \ - static dmac_b_instance_ctrl_t g_transfer_ctrl[DT_INST_PROP(inst, dma_channels)]; \ - static transfer_info_t g_transfer_info[DT_INST_PROP(inst, dma_channels)]; \ - static dmac_b_extended_cfg_t g_transfer_extend[DT_INST_PROP(inst, dma_channels)]; \ + static dma_instance_ctrl_t g_transfer_ctrl[DT_INST_PROP(inst, dma_channels)]; \ + RZ_DMA_EXTERN_INFO_DECLARATION(DT_INST_PROP(inst, dma_channels)); \ + static transfer_info_t g_transfer_info[DT_INST_PROP(inst, dma_channels)] = \ + RZ_DMA_TRANSFER_INFO_ARRAY(inst); \ + static dma_extended_cfg_t g_transfer_extend[DT_INST_PROP(inst, dma_channels)]; \ static struct dma_channel_data \ dma_rz_##inst##_channels[DT_INST_PROP(inst, dma_channels)] = \ - DMA_CHANNEL_ARRAY(inst); \ + RZ_DMA_CHANNEL_DATA_ARRAY(inst); \ \ ATOMIC_DEFINE(dma_rz_atomic##inst, DT_INST_PROP(inst, dma_channels)); \ \ @@ -630,10 +801,16 @@ static void dmac_irq_isr(const void *arg) .atomic = dma_rz_atomic##inst, \ .dma_channels = DT_INST_PROP(inst, dma_channels), \ }, \ - .channels = dma_rz_##inst##_channels}; \ + .channels = dma_rz_##inst##_channels, \ + RZ_DMA_DATA_STRUCT_GET_ERR_IRQ(inst, err1)}; \ \ DEVICE_DT_INST_DEFINE(inst, renesas_rz_dma_init, NULL, &dma_renesas_rz_data_##inst, \ &dma_renesas_rz_config_##inst, PRE_KERNEL_1, \ CONFIG_DMA_INIT_PRIORITY, &dma_api); DT_INST_FOREACH_STATUS_OKAY(DMA_RZ_INIT); + +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT renesas_rz_dmac + +DT_INST_FOREACH_STATUS_OKAY(DMA_RZ_INIT); diff --git a/drivers/dma/dma_renesas_rz.h b/drivers/dma/dma_renesas_rz.h index 30a9fee135f6b..f7eac74d7ade9 100644 --- a/drivers/dma/dma_renesas_rz.h +++ b/drivers/dma/dma_renesas_rz.h @@ -1,13 +1,13 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include -/* used to store interrupt and priority for channels */ -#define DMA_CHANNEL_DECLARE(n, inst) \ +/* Used to store interrupt and priority for channels */ +#define RZ_DMA_CHANNEL_DECLARE(n, inst) \ { \ .fsp_ctrl = (transfer_ctrl_t *)&g_transfer_ctrl[n], \ .fsp_cfg = \ @@ -20,8 +20,34 @@ } /* Generate an array of DMA channel data structures */ -#define DMA_CHANNEL_ARRAY(inst) \ - {LISTIFY(DT_INST_PROP(inst, dma_channels), DMA_CHANNEL_DECLARE, (,), inst) } +#define RZ_DMA_CHANNEL_DATA_ARRAY(inst) \ + {LISTIFY(DT_INST_PROP(inst, dma_channels), RZ_DMA_CHANNEL_DECLARE, (,), inst)} -#define DMA_PRV_CHANNEL(channel) (channel % 8) -#define DMA_PRV_GROUP(channel) (channel / 8) +#ifdef CONFIG_CPU_CORTEX_A +#define RZ_DMA_EXTERN_INFO_DECLARATION(size) static dma_extended_info_t g_dma_extended_info[size]; + +#define RZ_DMA_EXTEND_INFO_DECLARE(n, inst) \ + { \ + .p_extend_info = &g_dma_extended_info[n], \ + } + +#define RZ_DMA_TRANSFER_INFO_ARRAY(inst) \ + {LISTIFY(DT_INST_PROP(inst, dma_channels), RZ_DMA_EXTEND_INFO_DECLARE, (,), inst)} + +#else /* CONFIG_CPU_CORTEX_M || CONFIG_CPU_AARCH32_CORTEX_R */ +#define RZ_DMA_EXTERN_INFO_DECLARATION(size) + +#define RZ_DMA_TRANSFER_INFO_ARRAY(inst) \ + { \ + } +#endif /* CONFIG_CPU_CORTEX_A */ + +#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) +#define RZ_DMA_DATA_STRUCT_GET_ERR_IRQ(inst, err_name) \ + .err_irq = DT_INST_IRQ_BY_NAME(inst, err_name, irq), +#else /* CONFIG_CPU_AARCH32_CORTEX_R */ +#define RZ_DMA_DATA_STRUCT_GET_ERR_IRQ(inst, err_name) +#endif /* defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_A) */ + +#define RZ_DMA_PRV_CHANNEL(channel) (channel % 8) +#define RZ_DMA_PRV_GROUP(channel) (channel / 8) diff --git a/drivers/spi/Kconfig.renesas_rz b/drivers/spi/Kconfig.renesas_rz index d379e691767da..c24607e25660d 100644 --- a/drivers/spi/Kconfig.renesas_rz +++ b/drivers/spi/Kconfig.renesas_rz @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config SPI_RENESAS_RZ_RSPI @@ -19,7 +19,7 @@ config SPI_RENESAS_RZ_RSPI_INTERRUPT config SPI_RENESAS_RZ_RSPI_DMAC bool "RZ SPI DMA Support" - select USE_RZ_FSP_DMA + select USE_RZ_FSP_DMAC_B help Enable the SPI DMA mode for SPI instances diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi index d8f9b10885bbf..e4ffcb3cedae8 100644 --- a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi +++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi @@ -1,6 +1,6 @@ /* * Copyright (c) 2024 EPAM Systems - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * SPDX-License-Identifier: Apache-2.0 */ @@ -406,7 +406,7 @@ }; dma0: dma@41800000 { /* Secure DMA */ - compatible = "renesas,rz-dma"; + compatible = "renesas,rz-dmac-b"; reg = <0x41800000 0x800>, <0x41810000 0x20>; reg-names = "reg_main", "ext"; interrupts = <95 1>, <96 1>, <97 1>, <98 1>, @@ -419,9 +419,29 @@ "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "err1"; + dma-unit = <0>; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; + + dma1: dma@41820000 { /* Secure DMA */ + compatible = "renesas,rz-dmac-b"; + reg = <0x41820000 0x800>, <0x41830000 0x20>; + reg-names = "reg_main", "ext"; + interrupts = <112 1>, <113 1>, <114 1>, <115 1>, + <116 1>, <117 1>, <118 1>, <119 1>, + <120 1>, <121 1>, <122 1>, <123 1>, + <124 1>, <125 1>, <126 1>, <127 1>, + <111 1>; /* DMAERR1 */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "err1"; + dma-unit = <1>; dma-channels = <16>; #dma-cells = <2>; - dma-buf-addr-alignment = <4>; status = "disabled"; }; diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi index b34ab06eeda88..f44726990f66f 100644 --- a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi +++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi @@ -1144,5 +1144,43 @@ status = "disabled"; }; }; + + dma0: dma@80080000 { + compatible = "renesas,rz-dmac"; + reg = <0x80080000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + dma-unit = <0>; + dma-channels = <8>; + #dma-cells = <2>; + status = "disabled"; + }; + + dma1: dma@80081000 { + compatible = "renesas,rz-dmac"; + reg = <0x80081000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + dma-unit = <1>; + dma-channels = <8>; + #dma-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi index 0f2579ff60dcc..b62e65cdde3b1 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi @@ -1143,5 +1143,63 @@ status = "disabled"; }; }; + + dma0: dma@80080000 { + compatible = "renesas,rz-dmac"; + reg = <0x80080000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + dma-unit = <0>; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; + + dma1: dma@80081000 { + compatible = "renesas,rz-dmac"; + reg = <0x80081000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + dma-unit = <1>; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index d639f640d60a7..56a1dfe5398ae 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -940,6 +940,46 @@ status = "disabled"; }; }; + + dma0: dma@41800000 { /* Secure DMA */ + compatible = "renesas,rz-dmac-b"; + reg = <0x41800000 0x800>, <0x41810000 0x20>; + reg-names = "reg_main", "ext"; + interrupts = <108 1>, <109 1>, <110 1>, <111 1>, + <112 1>, <113 1>, <114 1>, <115 1>, + <116 1>, <117 1>, <118 1>, <119 1>, + <120 1>, <121 1>, <122 1>, <123 1>, + <124 1>; /* DMAERR */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "err1"; + dma-unit = <0>; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; + + dma1: dma@41820000 { /* Secure DMA */ + compatible = "renesas,rz-dmac-b"; + reg = <0x41820000 0x800>, <0x41830000 0x20>; + reg-names = "reg_main", "ext"; + interrupts = <125 1>, <126 1>, <127 1>, <128 1>, + <129 1>, <130 1>, <131 1>, <132 1>, + <133 1>, <134 1>, <135 1>, <136 1>, + <137 1>, <138 1>, <139 1>, <140 1>, + <141 1>; /* DMAERR */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "err1"; + dma-unit = <1>; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index cc1b5f875a9a5..710c07cb7fc90 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -703,5 +703,36 @@ status = "disabled"; }; }; + + dma0: dma@11820000 { + compatible = "renesas,rz-dmac"; + reg = <0x11820000 0x800>, <0x11830000 0x20>; + reg-names = "reg_main", "ext"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "err1"; + dma-channels = <16>; + #dma-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/dts/bindings/dma/renesas,rz-dma.yaml b/dts/bindings/dma/renesas,rz-dmac-b.yaml similarity index 85% rename from dts/bindings/dma/renesas,rz-dma.yaml rename to dts/bindings/dma/renesas,rz-dmac-b.yaml index e991e5417ab4b..51cd90e9e63b9 100644 --- a/dts/bindings/dma/renesas,rz-dma.yaml +++ b/dts/bindings/dma/renesas,rz-dmac-b.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 description: | @@ -17,7 +17,7 @@ description: | dma-names = "rx", "tx"; }; -compatible: "renesas,rz-dma" +compatible: "renesas,rz-dmac-b" include: [dma-controller.yaml, pinctrl-device.yaml] @@ -34,7 +34,8 @@ properties: "#dma-cells": const: 2 - dma-buf-addr-alignment: + dma-unit: + type: int required: true dma-cells: diff --git a/dts/bindings/dma/renesas,rz-dmac.yaml b/dts/bindings/dma/renesas,rz-dmac.yaml new file mode 100644 index 0000000000000..e0f1cdf72dafe --- /dev/null +++ b/dts/bindings/dma/renesas,rz-dmac.yaml @@ -0,0 +1,42 @@ +# Copyright (c) 2024-2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + RZ DMA controller + + channel: Select channel for data transmitting + + config: A 32bit mask specifying the DMA channel configuration + + Example of devicetree configuration + + &ssi0 { + status = "okay"; + + dmas = <&dma0 0 RZ_DMA_PERIPH_TO_MEM>, <&dma0 5 RZ_DMA_MEM_TO_PERIPH> + dma-names = "rx", "tx"; + }; + +compatible: "renesas,rz-dmac" + +include: [dma-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + dma-channels: + required: true + + "#dma-cells": + const: 2 + + dma-unit: + type: int + +dma-cells: + - channel + - config diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 2ce3656a0e0c2..f27a7c69e8b62 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -287,10 +287,15 @@ config USE_RZ_FSP_EXT_IRQ help Enable RZ FSP External IRQ driver -config USE_RZ_FSP_DMA +config USE_RZ_FSP_DMAC bool help - Enable RZ FSP DMA driver + Enable RZ FSP DMAC driver + +config USE_RZ_FSP_DMAC_B + bool + help + Enable RZ FSP DMAC_B driver config USE_RZ_FSP_MHU bool diff --git a/tests/drivers/dma/chan_blen_transfer/boards/rzn2l_rsk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/rzn2l_rsk.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/rzn2l_rsk.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/dma/chan_blen_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.conf b/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.conf new file mode 100644 index 0000000000000..8688d91758f24 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.conf @@ -0,0 +1 @@ +CONFIG_DMA_64BIT=y diff --git a/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.overlay b/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rza3ul_smarc.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/rzn2l_rsk.overlay b/tests/drivers/dma/loop_transfer/boards/rzn2l_rsk.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rzn2l_rsk.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/dma/loop_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay new file mode 100644 index 0000000000000..0330e5a2cce81 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 { }; diff --git a/west.yml b/west.yml index 035976239cb90..423988574edb1 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: d8ee5f18e95b9f4616a481be65e2c9ee0af1779f + revision: pull/146/head groups: - hal - name: hal_rpi_pico