diff --git a/boards/renesas/rza3ul_smarc/Kconfig.defconfig b/boards/renesas/rza3ul_smarc/Kconfig.defconfig new file mode 100644 index 0000000000000..8df5fc7719245 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config FLASH_LOAD_OFFSET + default $(dt_nodelabel_reg_addr_hex,header) diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts index 1306607129947..7323a7bd66ecb 100644 --- a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts @@ -18,7 +18,7 @@ chosen { zephyr,sram = &ddr; - zephyr,flash = &spi_flash; + zephyr,flash = &at25ql128a; zephyr,console = &scif0; zephyr,shell-uart = &scif0; zephyr,code-partition = &slot0_partition; @@ -36,28 +36,6 @@ zephyr,memory-region = "SRAM"; }; - spi_flash: memory@20020000 { - compatible = "mmio-sram"; - reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - header: partition@0 { - label = "header"; - reg = <0x00000000 0x200>; - read-only; - }; - - slot0_partition: partition@200 { - label = "image-0"; - reg = <0x00000200 (DT_SIZE_M(16) - 0x20200)>; - read-only; - }; - }; - }; }; &scif0 { @@ -76,3 +54,38 @@ pinctrl-names = "default"; status = "okay"; }; + +&spibsc { + status = "okay"; + + at25ql128a: qspi-nor-flash@20000000 { + compatible = "renesas,rz-qspi-spibsc"; + reg = <0x20000000 DT_SIZE_M(16)>; /* 128 Mbits */ + write-block-size = <1>; + erase-block-size = <4096>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + reserved: partition@0 { + reg = <0x00000000 0x20000>; + read-only; + }; + + header: partition@20000 { + label = "header"; + reg = <0x00020000 0x200>; + read-only; + }; + + slot0_partition: partition@20200 { + label = "image-0"; + reg = <0x00020200 (DT_SIZE_M(16) - 0x20200)>; + read-only; + }; + }; + }; +}; diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi index 2b338491a4bb3..2aa6728c77f0c 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi @@ -48,4 +48,18 @@ ; /* SDA */ }; }; + + /omit-if-no-ref/ xspi0_default: xspi0_default { + xspi0-pinmux { + pinmux = , /* XSPI0_CKP */ + , /* XSPI0_CKN */ + , /* XSPI0_CS0 */ + , /* XSPI0_IO0 */ + , /* XSPI0_IO1 */ + , /* XSPI0_IO2 */ + , /* XSPI0_IO3 */ + , /* XSPI0_RESET0 */ + ; /* XSPI0_RSTO0 */ + }; + }; }; diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts index bc733ef5c4558..7d457d8ea9c23 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts @@ -14,7 +14,7 @@ chosen { zephyr,sram = &atcm; - zephyr,flash = &xspi0_cs0; + zephyr,flash = &mx25u51245g; zephyr,code-partition = &slot0_partition; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -123,3 +123,17 @@ pinctrl-names = "default"; status = "okay"; }; + +&xspi0 { + pinctrl-0 = <&xspi0_default>; + pinctrl-names = "default"; + status = "okay"; + + mx25u51245g: qspi-nor-flash@60000000 { + compatible = "renesas,rz-qspi-xspi"; + reg = <0x60000000 DT_SIZE_M(64)>; /* 512 Mbits */ + write-block-size = <1>; + erase-block-size = <4096>; + status = "okay"; + }; +}; diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi index 9b48e978a3cce..079e524948559 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi @@ -40,4 +40,19 @@ ; /* SDA */ }; }; + + /omit-if-no-ref/ xspi0_default: xspi0_default { + xspi0-pinmux { + pinmux = , /* XSPI0_CKP */ + , /* XSPI0_CKN */ + , /* XSPI0_CS0 */ + , /* XSPI0_IO0 */ + , /* XSPI0_IO1 */ + , /* XSPI0_IO2 */ + , /* XSPI0_IO3 */ + , /* XSPI0_RESET0 */ + ; /* XSPI0_RSTO0 */ + }; + }; + }; diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts index 97ef74bbbe670..6a0334cebd91d 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts @@ -16,7 +16,7 @@ chosen { zephyr,sram = &cpu0_atcm; - zephyr,flash = &xspi0_cs0; + zephyr,flash = &mx25u51245g; zephyr,code-partition = &slot0_partition; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -120,3 +120,17 @@ &adc1 { status = "okay"; }; + +&xspi0 { + pinctrl-0 = <&xspi0_default>; + pinctrl-names = "default"; + status = "okay"; + + mx25u51245g: qspi-nor-flash@60000000 { + compatible = "renesas,rz-qspi-xspi"; + reg = <0x60000000 DT_SIZE_M(64)>; /* 512 Mbits */ + write-block-size = <1>; + erase-block-size = <4096>; + status = "okay"; + }; +}; diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 2ff0f66a59084..9952e1fd7ae6d 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -42,6 +42,8 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_NPCX_FIU_NOR flash_npcx_fiu_nor.c) zephyr_library_sources_ifdef(CONFIG_FLASH_NPCX_FIU_QSPI flash_npcx_fiu_qspi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RA_OSPI_B flash_renesas_ra_ospi_b.c) zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RA_QSPI flash_renesas_ra_qspi.c) +zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC flash_renesas_rz_qspi.c) +zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI flash_renesas_rz_qspi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_RPI_PICO flash_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_OSPI flash_stm32_ospi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_QSPI flash_stm32_qspi.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 17db3c45eeb4c..066a185a977b7 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -198,6 +198,7 @@ source "drivers/flash/Kconfig.renesas_ra" source "drivers/flash/Kconfig.renesas_ra_ospi" source "drivers/flash/Kconfig.renesas_ra_qspi" source "drivers/flash/Kconfig.renesas_rx" +source "drivers/flash/Kconfig.renesas_rz_qspi" source "drivers/flash/Kconfig.rpi_pico" source "drivers/flash/Kconfig.rts5912" source "drivers/flash/Kconfig.rv32m1" diff --git a/drivers/flash/Kconfig.renesas_rz_qspi b/drivers/flash/Kconfig.renesas_rz_qspi new file mode 100644 index 0000000000000..367cb00b76a18 --- /dev/null +++ b/drivers/flash/Kconfig.renesas_rz_qspi @@ -0,0 +1,37 @@ +# Renesas RZ Family + +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config FLASH_RENESAS_RZ_QSPI_XSPI + bool "Renesas RZ Quad-SPI driver" + default y + depends on DT_HAS_RENESAS_RZ_QSPI_XSPI_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_EXPLICIT_ERASE + select USE_RZ_FSP_QSPI + select FLASH_JESD216 + select PINCTRL + help + Enable Quad-SPI XSPI Nor flash driver for RZ series + +config FLASH_RENESAS_RZ_QSPI_SPIBSC + bool "Renesas RZ Quad-SPI driver" + default y + depends on DT_HAS_RENESAS_RZ_QSPI_SPIBSC_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_EXPLICIT_ERASE + select USE_RZ_FSP_QSPI + select FLASH_JESD216 + select PINCTRL + help + Enable Quad-SPI SPIBSC Nor flash driver for RZ series + +config FLASH_RENESAS_RZ_MIRROR_OFFSET + hex + default 0x0 if SOC_SERIES_RZA3UL + default 0x20000000 if SOC_SERIES_RZT2M || SOC_SERIES_RZN2L + help + Offset of mirror area in flash memory diff --git a/drivers/flash/flash_renesas_rz_qspi.c b/drivers/flash/flash_renesas_rz_qspi.c new file mode 100644 index 0000000000000..4dba628f5bb80 --- /dev/null +++ b/drivers/flash/flash_renesas_rz_qspi.c @@ -0,0 +1,604 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "spi_nor.h" +#include "r_spi_flash_api.h" + +#if defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) +#include "r_spibsc.h" +#else +#include "r_xspi_qspi.h" +#endif + +LOG_MODULE_REGISTER(renesas_rz_qspi, CONFIG_FLASH_LOG_LEVEL); + +#define QSPI_DEFAULT_SR (0x40) +#define QSPI_UPDATE_CR (0xC0) /* Configuration register (DC0=1, DC1=1 (Dummy cycle = 10)) */ +#define QSPI_DATA_CR_UPDATE (QSPI_UPDATE_CR << 8 | QSPI_DEFAULT_SR) + +#define FLASH_RZ_BASE_ADDRESS (CONFIG_FLASH_BASE_ADDRESS - CONFIG_FLASH_RENESAS_RZ_MIRROR_OFFSET) + +/* QSPI COMMANDS */ +#define QSPI_CMD_RDSFDP (0x5A) /* Read SFDP */ + +/* XIP (Execute In Place) mode */ +#define QSPI_CMD_XIP_ENTER (0xA5) /* XIP Enter command */ +#define QSPI_CMD_XIP_EXIT (0xFF) /* XIP Exit command */ + +#define QSPI_CMD_QUAD_PAGE_PROGRAM (0x33) + +/* One byte data transfer */ +#define DATA_LENGTH_DEFAULT_BYTE (0U) +#define ONE_BYTE (1U) +#define TWO_BYTE (2U) +#define THREE_BYTE (3U) +#define FOUR_BYTE (4U) + +/* Default erase value */ +#define QSPI_ERASE_VALUE (0xFF) + +/* Maximum memory buffer size of write operation in memory-map mode */ +#if defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) +#define QSPI_MAX_BUFFER_SIZE 256U +#else +#define QSPI_MAX_BUFFER_SIZE 64U +#endif + +struct flash_renesas_rz_data { + spi_flash_ctrl_t *fsp_ctrl; + spi_flash_cfg_t *fsp_cfg; + + struct k_sem sem; +}; + +struct flash_renesas_rz_config { + const struct pinctrl_dev_config *pin_cfg; + const spi_flash_api_t *fsp_api; + + uint32_t erase_block_size; + uint32_t flash_size; + struct flash_parameters flash_param; +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + struct flash_pages_layout layout; +#endif +}; + +static const spi_flash_erase_command_t g_erase_command_list[4] = { + {.command = SPI_NOR_CMD_SE, .size = SPI_NOR_SECTOR_SIZE}, + {.command = SPI_NOR_CMD_BE_32K, .size = SPI_NOR_BLOCK_32K_SIZE}, + {.command = SPI_NOR_CMD_BE, .size = SPI_NOR_BLOCK_SIZE}, + {.command = SPI_NOR_CMD_CE, .size = SPI_FLASH_ERASE_SIZE_CHIP_ERASE}, +}; + +static void acquire_device(const struct device *dev) +{ + struct flash_renesas_rz_data *dev_data = dev->data; + + k_sem_take(&dev_data->sem, K_FOREVER); +} + +static void release_device(const struct device *dev) +{ + struct flash_renesas_rz_data *dev_data = dev->data; + + k_sem_give(&dev_data->sem); +} +static int qspi_wait_until_ready(const struct device *dev) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *data = dev->data; + spi_flash_status_t status = {.write_in_progress = true}; + uint32_t timeout = UINT32_MAX; + fsp_err_t err = 0; + + while ((status.write_in_progress) && (timeout > 0)) { + err = config->fsp_api->statusGet(data->fsp_ctrl, &status); + if (FSP_SUCCESS != (fsp_err_t)err) { + LOG_ERR("Status get failed"); + return -EIO; + } + timeout--; + } + + return 0; +} + +#if CONFIG_FLASH_PAGE_LAYOUT +void flash_renesas_rz_page_layout(const struct device *dev, + const struct flash_pages_layout **layout, size_t *layout_size) +{ + const struct flash_renesas_rz_config *config = dev->config; + + *layout = &config->layout; + *layout_size = 1; +} +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +#if defined(CONFIG_FLASH_JESD216_API) +static int qspi_flash_rz_read_jedec_id(const struct device *dev, uint8_t *id) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *data = dev->data; + int ret = 0; + + if (id == NULL) { + return -EINVAL; + } + + spi_flash_direct_transfer_t trans = {.command = SPI_NOR_CMD_RDID, + .address = 0, + .data = 0, + .command_length = 1U, + .address_length = 0U, + .data_length = THREE_BYTE, + .dummy_cycles = 0U}; + + acquire_device(dev); + ret = config->fsp_api->directTransfer(data->fsp_ctrl, &trans, + SPI_FLASH_DIRECT_TRANSFER_DIR_READ); + if (FSP_SUCCESS != (fsp_err_t)ret) { + LOG_ERR("Failed to read device id"); + release_device(dev); + return -EIO; + } + + /* Get flash device ID */ + memcpy(id, &trans.data, sizeof(trans.data)); + release_device(dev); + + return ret; +} + +static int qspi_flash_renesas_rz_sfdp_read(const struct device *dev, off_t addr, void *data, + size_t len) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *dev_data = dev->data; + int ret = 0; + size_t size; + + spi_flash_direct_transfer_t trans = {.command = QSPI_CMD_RDSFDP, + .address = addr, + .data = 0, + .command_length = 1U, + .address_length = 3U, + .data_length = FOUR_BYTE, + .dummy_cycles = SPI_NOR_DUMMY_RD}; + + acquire_device(dev); + while (len > 0) { + size = MIN(len, trans.data_length); + trans.address = addr; + trans.data_length = size; + + ret = config->fsp_api->directTransfer(dev_data->fsp_ctrl, &trans, + SPI_FLASH_DIRECT_TRANSFER_DIR_READ); + + if (FSP_SUCCESS != (fsp_err_t)ret) { + LOG_ERR("Failed to read SFDP id"); + release_device(dev); + return -EIO; + } + + memcpy(data, &trans.data, size); + + len -= size; + addr += size; + data = (uint8_t *)data + size; + } + + release_device(dev); + return ret; +} +#endif + +static bool qspi_flash_rz_valid(uint32_t area_size, off_t offset, size_t len) +{ + if ((offset < 0) || (offset >= area_size) || ((area_size - offset) < len)) { + return false; + } + + return true; +} + +static int qspi_flash_rz_erase(const struct device *dev, off_t offset, size_t len) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *data = dev->data; + int err = 0; + struct flash_pages_info page_info_start, page_info_end; + uint32_t erase_size; + int rc; + + if (!len) { + return 0; + } + + if (!qspi_flash_rz_valid(config->flash_size, offset, len)) { + LOG_ERR("The offset 0x%lx is invalid", (long)offset); + return -EINVAL; + } + + if (0 != (len % config->erase_block_size)) { + LOG_ERR("The size %zu is not align with block size (%u)", len, + config->erase_block_size); + return -EINVAL; + } + + rc = flash_get_page_info_by_offs(dev, offset, &page_info_start); + if ((rc != 0) || (offset != page_info_start.start_offset)) { + LOG_ERR("The offset 0x%lx is not aligned with the starting sector", (long)offset); + return -EINVAL; + } + + rc = flash_get_page_info_by_offs(dev, (offset + len), &page_info_end); + if ((rc != 0) || ((offset + len) != page_info_end.start_offset)) { + LOG_ERR("The size %zu is not aligned with the ending sector", len); + return -EINVAL; + } + + acquire_device(dev); + while (len > 0) { + if (len < SPI_NOR_BLOCK_32K_SIZE) { + erase_size = SPI_NOR_SECTOR_SIZE; + } else if (len < SPI_NOR_BLOCK_SIZE) { + erase_size = SPI_NOR_BLOCK_32K_SIZE; + } else { + erase_size = SPI_NOR_BLOCK_SIZE; + } + + uint8_t *dest = (uint8_t *)FLASH_RZ_BASE_ADDRESS; + + dest += (size_t)offset; + err = config->fsp_api->erase(data->fsp_ctrl, dest, erase_size); + if (FSP_SUCCESS != (fsp_err_t)err) { + LOG_ERR("Erase failed"); + err = -EIO; + break; + } + + err = qspi_wait_until_ready(dev); + if (err) { + LOG_ERR("Failed to get status for QSPI operation"); + err = -EIO; + break; + } + + offset += erase_size; + len -= erase_size; + +#if defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) + spibsc_instance_ctrl_t *p_ctrl = (spibsc_instance_ctrl_t *)data->fsp_ctrl; + + /* Invalidating SPIBSC cache */ + p_ctrl->p_reg->DRCR_b.RCF = 1; + sys_cache_data_invd_range((void *)dest, erase_size); +#endif + } + release_device(dev); + + return err; +} + +static int qspi_flash_rz_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + + const struct flash_renesas_rz_config *config = dev->config; + + if (!len) { + return 0; + } + + if (!data) { + return -EINVAL; + } + + if (!qspi_flash_rz_valid(config->flash_size, offset, len)) { + return -EINVAL; + } + + acquire_device(dev); + + uint8_t *dest = (uint8_t *)FLASH_RZ_BASE_ADDRESS; + + dest += (size_t)offset; + memcpy(data, dest, len); + release_device(dev); + + return 0; +} + +static int qspi_flash_rz_write(const struct device *dev, off_t offset, const void *data, size_t len) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *dev_data = dev->data; + int err = 0; + uint32_t remaining_bytes = len; + uint32_t size = (uint32_t)len; + + if (!len) { + return 0; + } + + if (!data) { + return -EINVAL; + } + + if (!qspi_flash_rz_valid(config->flash_size, offset, len)) { + return -EINVAL; + } + + acquire_device(dev); + while (remaining_bytes > 0) { + size = MIN(remaining_bytes, QSPI_MAX_BUFFER_SIZE); + uint8_t *dest = (uint8_t *)FLASH_RZ_BASE_ADDRESS; + + dest += (size_t)offset; + err = config->fsp_api->write(dev_data->fsp_ctrl, (const uint8_t *)data, dest, size); + if (FSP_SUCCESS != (fsp_err_t)err) { + LOG_ERR("Flash write failed"); + err = -EIO; + break; + } + + err = qspi_wait_until_ready(dev); + if (err) { + LOG_ERR("Failed to get status for QSPI operation"); + err = -EIO; + break; + } + + remaining_bytes -= size; + offset += size; + data = (const uint8_t *)data + size; + +#if defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) + spibsc_instance_ctrl_t *p_ctrl = (spibsc_instance_ctrl_t *)dev_data->fsp_ctrl; + + /* Invalidating SPIBSC cache */ + p_ctrl->p_reg->DRCR_b.RCF = 1; + sys_cache_data_invd_range((void *)dest, size); +#endif + } + release_device(dev); + return err; +} + +static int qspi_flash_rz_get_size(const struct device *dev, uint64_t *size) +{ + const struct flash_renesas_rz_config *config = dev->config; + + *size = (uint64_t)config->flash_size; + + return 0; +} + +static const struct flash_parameters *qspi_flash_rz_get_parameters(const struct device *dev) +{ + const struct flash_renesas_rz_config *config = dev->config; + + return &config->flash_param; +} + +#if CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI +static int spi_flash_direct_write(const struct device *dev, uint8_t command, uint32_t tx_data, + uint8_t data_length) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *data = dev->data; + int ret; + + spi_flash_direct_transfer_t trans = {.command = command, + .address = 0U, + .data = tx_data, + .command_length = 1U, + .address_length = 0U, + .data_length = data_length, + .dummy_cycles = 0U}; + + ret = config->fsp_api->directTransfer(data->fsp_ctrl, &trans, + SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE); + if (FSP_SUCCESS != (fsp_err_t)ret) { + LOG_ERR("Failed to write command"); + return -EIO; + }; + + return ret; +} +#endif + +static int flash_renesas_rz_init(const struct device *dev) +{ + const struct flash_renesas_rz_config *config = dev->config; + struct flash_renesas_rz_data *data = dev->data; + int ret = 0; + +#if CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI + ret = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT); + if (ret) { + LOG_ERR("Failed to configure pins for QSPI with code: %d", ret); + return -EIO; + } +#endif + k_sem_init(&data->sem, 1, 1); + + ret = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); + if (FSP_SUCCESS != (fsp_err_t)ret) { + LOG_ERR("Open failed"); + return -EIO; + } + +#if CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI + /* Write Enable Command */ + ret = spi_flash_direct_write(dev, data->fsp_cfg->write_enable_command, 0U, + DATA_LENGTH_DEFAULT_BYTE); + if (ret) { + return ret; + } + + /* Write Status Command */ + ret = spi_flash_direct_write(dev, SPI_NOR_CMD_WRSR, QSPI_DATA_CR_UPDATE, TWO_BYTE); + if (ret) { + return ret; + } +#endif + return ret; +} + +static DEVICE_API(flash, flash_renesas_rz_qspi_driver_api) = { + .erase = qspi_flash_rz_erase, + .write = qspi_flash_rz_write, + .read = qspi_flash_rz_read, + .get_parameters = qspi_flash_rz_get_parameters, + .get_size = qspi_flash_rz_get_size, +#ifdef CONFIG_FLASH_PAGE_LAYOUT + .page_layout = flash_renesas_rz_page_layout, +#endif +#if defined(CONFIG_FLASH_JESD216_API) + .sfdp_read = qspi_flash_renesas_rz_sfdp_read, + .read_jedec_id = qspi_flash_rz_read_jedec_id, +#endif +}; + +#define DT_DRV_COMPAT renesas_rz_qspi_xspi + +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) +#define FLASH_RENESAS_RZ_QSPI_XSPI_DEFINE(n) \ + PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \ + static xspi_qspi_timing_setting_t g_qspi##n##_timing_settings = { \ + .command_to_command_interval = XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_2, \ + .cs_pullup_lag = XSPI_QSPI_CS_PULLUP_CLOCKS_1, \ + .cs_pulldown_lead = XSPI_QSPI_CS_PULLDOWN_CLOCKS_1}; \ + static xspi_qspi_address_space_t g_qspi##n##_address_space_settings = { \ + .unit0_cs0_end_address = XSPI_QSPI_CFG_UNIT_0_CS_0_END_ADDRESS, \ + .unit0_cs1_start_address = XSPI_QSPI_CFG_UNIT_0_CS_1_START_ADDRESS, \ + .unit0_cs1_end_address = XSPI_QSPI_CFG_UNIT_0_CS_1_END_ADDRESS, \ + .unit1_cs0_end_address = XSPI_QSPI_CFG_UNIT_1_CS_0_END_ADDRESS, \ + .unit1_cs1_start_address = XSPI_QSPI_CFG_UNIT_1_CS_1_START_ADDRESS, \ + .unit1_cs1_end_address = XSPI_QSPI_CFG_UNIT_1_CS_1_END_ADDRESS, \ + }; \ + static const xspi_qspi_extended_cfg_t g_qspi##n##_extended_cfg = { \ + .unit = n, \ + .chip_select = XSPI_QSPI_CHIP_SELECT_##n, \ + .memory_size = XSPI_QSPI_MEMORY_SIZE_64MB, \ + .p_timing_settings = &g_qspi##n##_timing_settings, \ + .prefetch_en = \ + (xspi_qspi_prefetch_function_t)XSPI_QSPI_CFG_UNIT_##n##_PREFETCH_FUNCTION, \ + .p_address_space = &g_qspi##n##_address_space_settings, \ + }; \ + static spi_flash_cfg_t g_qspi##n##_cfg = { \ + .spi_protocol = SPI_FLASH_PROTOCOL_1S_1S_1S, \ + .read_mode = SPI_FLASH_READ_MODE_FAST_READ, \ + .address_bytes = SPI_FLASH_ADDRESS_BYTES_3, \ + .dummy_clocks = SPI_FLASH_DUMMY_CLOCKS_10, \ + .read_command = SPI_NOR_CMD_READ_FAST, \ + .page_program_command = SPI_NOR_CMD_PP, \ + .page_program_address_lines = SPI_FLASH_DATA_LINES_4, \ + .page_size_bytes = SPI_NOR_PAGE_SIZE, \ + .write_enable_command = SPI_NOR_CMD_WREN, \ + .status_command = SPI_NOR_CMD_RDSR, \ + .write_status_bit = 0, \ + .xip_enter_command = QSPI_CMD_XIP_ENTER, \ + .xip_exit_command = QSPI_CMD_XIP_EXIT, \ + .p_erase_command_list = &g_erase_command_list[0], \ + .erase_command_list_length = ARRAY_SIZE(g_erase_command_list), \ + .p_extend = &g_qspi##n##_extended_cfg, \ + }; \ + static xspi_qspi_instance_ctrl_t g_qspi##n##_ctrl; \ + static struct flash_renesas_rz_data flash_renesas_rz_data_##n = { \ + .fsp_ctrl = &g_qspi##n##_ctrl, \ + .fsp_cfg = &g_qspi##n##_cfg, \ + }; \ + static const struct flash_renesas_rz_config flash_renesas_rz_config_##n = { \ + .pin_cfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \ + .fsp_api = &g_spi_flash_on_xspi_qspi, \ + .flash_size = DT_INST_REG_SIZE(n), \ + .erase_block_size = DT_INST_PROP_OR(n, erase_block_size, 4096), \ + .flash_param = \ + { \ + .write_block_size = DT_INST_PROP(n, write_block_size), \ + .erase_value = QSPI_ERASE_VALUE, \ + }, \ + IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \ + (.layout = { \ + .pages_count = \ + DT_INST_REG_SIZE(n) / DT_INST_PROP_OR(n, erase_block_size, 4096), \ + .pages_size = DT_INST_PROP_OR(n, erase_block_size, 4096), \ + },))}; \ + DEVICE_DT_INST_DEFINE(n, flash_renesas_rz_init, NULL, &flash_renesas_rz_data_##n, \ + &flash_renesas_rz_config_##n, POST_KERNEL, \ + CONFIG_FLASH_INIT_PRIORITY, &flash_renesas_rz_qspi_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(FLASH_RENESAS_RZ_QSPI_XSPI_DEFINE) +#endif + +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT renesas_rz_qspi_spibsc + +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) +#define FLASH_RENESAS_RZ_QSPI_SPIBSC_DEFINE(n) \ + static const spibsc_extended_cfg_t g_qspi##n##_extended_cfg = { \ + .delay = \ + { \ + .slch = 0, \ + .clsh = 0, \ + .shsl = 6, \ + }, \ + .io_fix_mask = (0u << 2) | (1u << 3), \ + .io_fix_value = (1u << 2) | (1u << 3), \ + }; \ + static spi_flash_cfg_t g_qspi##n##_cfg = { \ + .spi_protocol = SPI_FLASH_PROTOCOL_EXTENDED_SPI, \ + .read_mode = SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO, \ + .address_bytes = SPI_FLASH_ADDRESS_BYTES_3, \ + .dummy_clocks = SPI_FLASH_DUMMY_CLOCKS_DEFAULT, \ + .read_command = SPI_NOR_CMD_4READ, \ + .page_program_command = QSPI_CMD_QUAD_PAGE_PROGRAM, \ + .page_program_address_lines = SPI_FLASH_DATA_LINES_4, \ + .page_size_bytes = SPI_NOR_PAGE_SIZE, \ + .write_enable_command = SPI_NOR_CMD_WREN, \ + .status_command = SPI_NOR_CMD_RDSR, \ + .write_status_bit = 0, \ + .xip_enter_command = QSPI_CMD_XIP_ENTER, \ + .xip_exit_command = QSPI_CMD_XIP_EXIT, \ + .p_erase_command_list = &g_erase_command_list[0], \ + .erase_command_list_length = ARRAY_SIZE(g_erase_command_list), \ + .p_extend = &g_qspi##n##_extended_cfg, \ + }; \ + static spibsc_instance_ctrl_t g_qspi##n##_ctrl; \ + static struct flash_renesas_rz_data flash_renesas_rz_data_##n = { \ + .fsp_ctrl = &g_qspi##n##_ctrl, \ + .fsp_cfg = &g_qspi##n##_cfg, \ + }; \ + static const struct flash_renesas_rz_config flash_renesas_rz_config_##n = { \ + .pin_cfg = NULL, \ + .fsp_api = &g_spi_flash_on_spibsc, \ + .flash_size = DT_INST_REG_SIZE(n), \ + .erase_block_size = DT_INST_PROP_OR(n, erase_block_size, 4096), \ + .flash_param = \ + { \ + .write_block_size = DT_INST_PROP(n, write_block_size), \ + .erase_value = QSPI_ERASE_VALUE, \ + }, \ + IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \ + (.layout = { \ + .pages_count = \ + DT_INST_REG_SIZE(n) / DT_INST_PROP_OR(n, erase_block_size, 4096), \ + .pages_size = DT_INST_PROP_OR(n, erase_block_size, 4096), \ + },))}; \ + DEVICE_DT_INST_DEFINE(n, flash_renesas_rz_init, NULL, &flash_renesas_rz_data_##n, \ + &flash_renesas_rz_config_##n, POST_KERNEL, \ + CONFIG_FLASH_INIT_PRIORITY, &flash_renesas_rz_qspi_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(FLASH_RENESAS_RZ_QSPI_SPIBSC_DEFINE) +#endif diff --git a/drivers/flash/spi_nor.h b/drivers/flash/spi_nor.h index 459ce8859b2aa..70af588e9524f 100644 --- a/drivers/flash/spi_nor.h +++ b/drivers/flash/spi_nor.h @@ -90,9 +90,10 @@ #define SPI_NOR_OCMD_BULKE 0x609F /* Octa Bulk Erase */ /* Page, sector, and block size are standard, not configurable. */ - #define SPI_NOR_PAGE_SIZE 0x0100U - #define SPI_NOR_SECTOR_SIZE 0x1000U - #define SPI_NOR_BLOCK_SIZE 0x10000U +#define SPI_NOR_PAGE_SIZE 0x0100U +#define SPI_NOR_SECTOR_SIZE 0x1000U +#define SPI_NOR_BLOCK_32K_SIZE 0x8000U +#define SPI_NOR_BLOCK_SIZE 0x10000U /* Flash Auto-polling values */ #define SPI_NOR_WREN_MATCH 0x02 diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi index b34ab06eeda88..042e84ff4da8c 100644 --- a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi +++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi @@ -1144,5 +1144,25 @@ status = "disabled"; }; }; + + xspi0: xspi@80220000 { + compatible = "renesas,rz-xspi"; + reg = <0x80220000 0x1000>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + xspi1: xspi@80221000 { + compatible = "renesas,rz-xspi"; + reg = <0x80221000 0x1000>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi index 0f2579ff60dcc..6fa9a91d7098d 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi @@ -1143,5 +1143,26 @@ status = "disabled"; }; }; + + xspi0: xspi@80220000 { + compatible = "renesas,rz-xspi"; + reg = <0x80220000 0x1000>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + xspi1: xspi@80221000 { + compatible = "renesas,rz-xspi"; + reg = <0x80221000 0x1000>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + }; }; diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index e8a0537838122..7383d60a19373 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -688,5 +688,14 @@ status = "disabled"; }; }; + + spibsc: spibsc@10060000 { + compatible = "renesas,rz-spibsc"; + reg = <0x10060000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + }; }; diff --git a/dts/bindings/flash_controller/renesas,rz-qspi-spibsc.yaml b/dts/bindings/flash_controller/renesas,rz-qspi-spibsc.yaml new file mode 100644 index 0000000000000..2c20187b4bacc --- /dev/null +++ b/dts/bindings/flash_controller/renesas,rz-qspi-spibsc.yaml @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Renesas RZ SPIBSC NOR FLASH supporting the JEDEC CFI interface + + Representation of a serial flash on a quadspi bus: + + at25ql128a: qspi-nor-flash@20000000 { + compatible = "renesas,rz-qspi-spibsc"; + reg = <0x20000000 DT_SIZE_M(16)>; /* 128 Mbits */ + write-block-size = <1>; + erase-block-size = <4096>; + status = "okay"; + }; + +compatible: "renesas,rz-qspi-spibsc" + +include: ["flash-controller.yaml", "jedec,jesd216.yaml"] + +on-bus: qspi + +properties: + reg: + required: true + description: Flash Memory base address and size in bytes + + erase-block-size: + type: int + default: 4096 + description: Address alignment required by flash erase operations + + write-block-size: + type: int + default: 1 + description: Address alignment required by flash write operations diff --git a/dts/bindings/flash_controller/renesas,rz-qspi-xspi.yaml b/dts/bindings/flash_controller/renesas,rz-qspi-xspi.yaml new file mode 100644 index 0000000000000..6cc10e282a843 --- /dev/null +++ b/dts/bindings/flash_controller/renesas,rz-qspi-xspi.yaml @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Renesas RZ XSPI NOR FLASH supporting the JEDEC CFI interface + + Representation of a serial flash on a quadspi bus: + + mx25u51245g: qspi-nor-flash@60000000 { + compatible = "renesas,rz-qspi-xspi"; + reg = <0x60000000 DT_SIZE_M(64)>; /* 512 Mbits */ + write-block-size = <1>; + erase-block-size = <4096>; + status = "okay"; + }; + +compatible: "renesas,rz-qspi-xspi" + +include: ["flash-controller.yaml", "jedec,jesd216.yaml"] + +on-bus: qspi + +properties: + reg: + required: true + description: Flash Memory base address and size in bytes + + erase-block-size: + type: int + default: 4096 + description: Address alignment required by flash erase operations + + write-block-size: + type: int + default: 1 + description: Address alignment required by flash write operations diff --git a/dts/bindings/qspi/renesas,rz-spibsc.yaml b/dts/bindings/qspi/renesas,rz-spibsc.yaml new file mode 100644 index 0000000000000..c3053a0fa9874 --- /dev/null +++ b/dts/bindings/qspi/renesas,rz-spibsc.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ SPIBSC + +compatible: "renesas,rz-spibsc" + +include: [base.yaml, pinctrl-device.yaml] + +bus: qspi + +properties: + reg: + required: true diff --git a/dts/bindings/qspi/renesas,rz-xspi.yaml b/dts/bindings/qspi/renesas,rz-xspi.yaml new file mode 100644 index 0000000000000..27f7e6d9e8acf --- /dev/null +++ b/dts/bindings/qspi/renesas,rz-xspi.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ XSPI + +compatible: "renesas,rz-xspi" + +include: [base.yaml, pinctrl-device.yaml] + +bus: qspi + +properties: + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 2ce3656a0e0c2..b3bd153db6804 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -327,6 +327,11 @@ config USE_RZ_FSP_CMTW help Enable RZ FSP CMTW driver +config USE_RZ_FSP_QSPI + bool + help + Enable RZ FSP QSPI driver + endif config HAS_RENESAS_RX_RDP diff --git a/samples/drivers/jesd216/src/main.c b/samples/drivers/jesd216/src/main.c index 4b6e4cf5c1fcc..6c46b0dd0d7bd 100644 --- a/samples/drivers/jesd216/src/main.c +++ b/samples/drivers/jesd216/src/main.c @@ -34,6 +34,10 @@ #define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_ospi_b_nor) #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_qspi_nor) #define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_qspi_nor) +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_qspi_xspi) +#define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_qspi_xspi) +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_qspi_spibsc) +#define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_rz_qspi_spibsc) #else #error Unsupported flash driver #define FLASH_NODE DT_INVALID_NODE diff --git a/samples/drivers/spi_flash/src/main.c b/samples/drivers/spi_flash/src/main.c index 07adf7739becc..2fd493338420e 100644 --- a/samples/drivers/spi_flash/src/main.c +++ b/samples/drivers/spi_flash/src/main.c @@ -38,7 +38,8 @@ #if defined(CONFIG_FLASH_STM32_OSPI) || defined(CONFIG_FLASH_STM32_QSPI) || \ defined(CONFIG_FLASH_STM32_XSPI) || defined(CONFIG_FLASH_RENESAS_RA_OSPI_B) || \ - defined(CONFIG_FLASH_RENESAS_RA_QSPI) + defined(CONFIG_FLASH_RENESAS_RA_QSPI) || defined(CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI) || \ + defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) #define SPI_FLASH_MULTI_SECTOR_TEST #endif @@ -58,6 +59,10 @@ #define SPI_FLASH_COMPAT renesas_ra_ospi_b_nor #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_qspi_nor) #define SPI_FLASH_COMPAT renesas_ra_qspi_nor +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_qspi_xspi) +#define SPI_FLASH_COMPAT renesas_rz_qspi_xspi +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_qspi_spibsc) +#define SPI_FLASH_COMPAT renesas_rz_qspi_spibsc #else #define SPI_FLASH_COMPAT invalid #endif diff --git a/soc/renesas/rz/rza3ul/mmu_regions.c b/soc/renesas/rz/rza3ul/mmu_regions.c index 3f07572e5804a..20c39e69dd7af 100644 --- a/soc/renesas/rz/rza3ul/mmu_regions.c +++ b/soc/renesas/rz/rza3ul/mmu_regions.c @@ -10,6 +10,10 @@ static const struct arm_mmu_region mmu_regions[] = { MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000, MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE), + MMU_REGION_FLAT_ENTRY("SPI Multi Area", 0x20000000, 0x10000000, + MT_NORMAL | MT_RW | MT_DEFAULT_SECURE_STATE), + MMU_REGION_FLAT_ENTRY("SRAM", 0x00000000, 0x00200000, + MT_NORMAL | MT_RW | MT_DEFAULT_SECURE_STATE), }; const struct arm_mmu_config mmu_config = { diff --git a/soc/renesas/rz/rza3ul/sections.ld b/soc/renesas/rz/rza3ul/sections.ld index bdc29c67e39d2..ad475214f901f 100644 --- a/soc/renesas/rz/rza3ul/sections.ld +++ b/soc/renesas/rz/rza3ul/sections.ld @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,) +SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET,) { QUAD(__start) QUAD(0xFFFFFFFFFFFFFFFF-__start) diff --git a/tests/drivers/flash/common/boards/rza3ul_smarc.conf b/tests/drivers/flash/common/boards/rza3ul_smarc.conf new file mode 100644 index 0000000000000..d8d3631c5d59c --- /dev/null +++ b/tests/drivers/flash/common/boards/rza3ul_smarc.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=16777216 diff --git a/tests/drivers/flash/common/boards/rza3ul_smarc.overlay b/tests/drivers/flash/common/boards/rza3ul_smarc.overlay new file mode 100644 index 0000000000000..a427cde3b5aae --- /dev/null +++ b/tests/drivers/flash/common/boards/rza3ul_smarc.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&at25ql128a { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/rzn2l_rsk.conf b/tests/drivers/flash/common/boards/rzn2l_rsk.conf new file mode 100644 index 0000000000000..349d703d783c2 --- /dev/null +++ b/tests/drivers/flash/common/boards/rzn2l_rsk.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=67108864 diff --git a/tests/drivers/flash/common/boards/rzn2l_rsk.overlay b/tests/drivers/flash/common/boards/rzn2l_rsk.overlay new file mode 100644 index 0000000000000..bc059c7cb3bf9 --- /dev/null +++ b/tests/drivers/flash/common/boards/rzn2l_rsk.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&mx25u51245g { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf b/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf new file mode 100644 index 0000000000000..349d703d783c2 --- /dev/null +++ b/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=67108864 diff --git a/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 0000000000000..bc059c7cb3bf9 --- /dev/null +++ b/tests/drivers/flash/common/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&mx25u51245g { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c index 337876a9e8d76..5be1b3d4c8605 100644 --- a/tests/drivers/flash/common/src/main.c +++ b/tests/drivers/flash/common/src/main.c @@ -22,6 +22,10 @@ #define TEST_AREA_DEV_NODE DT_INST(0, jedec_mspi_nor) #elif defined(CONFIG_FLASH_RENESAS_RA_QSPI) #define TEST_AREA_DEV_NODE DT_INST(0, renesas_ra_qspi_nor) +#elif defined(CONFIG_FLASH_RENESAS_RZ_QSPI_XSPI) +#define TEST_AREA_DEV_NODE DT_INST(0, renesas_rz_qspi_xspi) +#elif defined(CONFIG_FLASH_RENESAS_RZ_QSPI_SPIBSC) +#define TEST_AREA_DEV_NODE DT_INST(0, renesas_rz_qspi_spibsc) #else #define TEST_AREA storage_partition #endif diff --git a/west.yml b/west.yml index 319084e4118ce..2ef07f31874fc 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: d8ee5f18e95b9f4616a481be65e2c9ee0af1779f + revision: pull/149/head groups: - hal - name: hal_rpi_pico