From 3919bdb9d856fee533ed233d3e9068b2f7543899 Mon Sep 17 00:00:00 2001 From: Vit Stanicek Date: Thu, 28 Aug 2025 15:59:39 +0200 Subject: [PATCH 1/4] soc: mcxnx4x: Instantiate MICFIL Add the micfil node to nxp_mcxnx4x_common.dtsi. Signed-off-by: Vit Stanicek --- dts/arm/nxp/nxp_mcxnx4x_common.dtsi | 73 +++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi index 68c1206e2588f..4cba4485c5146 100644 --- a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi @@ -660,6 +660,79 @@ #io-channel-cells = <1>; }; + micfil: micfil@10c000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "nxp,micfil"; + reg = <0x10c000 0x1000>; + + interrupts = <48 0>; + clocks = <&syscon MCUX_MICFIL_CLK>; + quality-mode = <1>; + cic-decimation-rate = <0>; + fifo-watermark = <15>; + sample-rate = <16000>; + + status = "disabled"; + + channel0: micfil-channel@0 { + reg = <0>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel1: micfil-channel@1 { + reg = <1>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel2: micfil-channel@2 { + reg = <2>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel3: micfil-channel@3 { + reg = <3>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel4: micfil-channel@4 { + reg = <4>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel5: micfil-channel@5 { + reg = <5>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel6: micfil-channel@6 { + reg = <6>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + + channel7: micfil-channel@7 { + reg = <7>; + dc-remover-cutoff-freq = <2>; + decimation-filter-gain = <4>; + status = "disabled"; + }; + }; + enet: ethernet@40100000 { compatible = "nxp,enet-qos"; reg = <0x40100000 0x1200>; From 542bfb46b75cb4e6cb34a6746df82b164aaa371b Mon Sep 17 00:00:00 2001 From: Tomas Barak Date: Fri, 3 Oct 2025 09:18:51 +0200 Subject: [PATCH 2/4] board: mcx_n5xx: Enable MICFIL and da7212 codec on mcx_n5xx - add micfil clock initialization to board.c - enable micfil and da7212 codec in mcx_n5xx dts Signed-off-by: Tomas Barak --- boards/nxp/mcx_nx4x_evk/board.c | 14 ++++++++-- boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi | 6 +++++ .../mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi | 26 ++++++++++++++++++- .../nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi | 13 ++++++++++ 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/boards/nxp/mcx_nx4x_evk/board.c b/boards/nxp/mcx_nx4x_evk/board.c index 760812971a3ad..e5b69635a7ec5 100644 --- a/boards/nxp/mcx_nx4x_evk/board.c +++ b/boards/nxp/mcx_nx4x_evk/board.c @@ -136,7 +136,7 @@ void board_early_init_hook(void) CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ); -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil)) /* < Set up PLL1 */ const pll_setup_t pll1_Setup = { .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) | @@ -149,7 +149,7 @@ void board_early_init_hook(void) /* Configure PLL1 to the desired values */ CLOCK_SetPLL1Freq(&pll1_Setup); /* Set PLL1 CLK0 divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U); + CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 2U); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0)) @@ -213,6 +213,7 @@ void board_early_init_hook(void) #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Port0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) @@ -450,6 +451,15 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_Sai1); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil)) + CLOCK_SetClkDiv(kCLOCK_DivMicfilFClk, 1U); + CLOCK_AttachClk(kPLL1_CLK0_to_MICFILF); + CLOCK_EnableClock(kCLOCK_Micfil); + + PORT0->PCR[16] = 0x00001900; + PORT0->PCR[17] = 0x00001900; +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi index 6a439888b8378..fc538ddb4f23b 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi @@ -7,3 +7,9 @@ #include #include "mcx_nx4x_evk.dtsi" #include "mcx_n5xx_evk-pinctrl.dtsi" + +&micfil { + status = "okay"; + pinctrl-0 = <&pinmux_micfil>; + pinctrl-names = "default"; +}; \ No newline at end of file diff --git a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi index 673996184b375..73d9672d03cbf 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi @@ -92,7 +92,8 @@ pinmux_sai1: pinmux_sai1 { group0 { - pinmux = , + pinmux = , + , , , , @@ -104,6 +105,18 @@ }; }; + pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_enet_qos: pinmux_enet_qos { mdio_group { pinmux = , @@ -237,4 +250,15 @@ bias-pull-up; }; }; + + pinmux_micfil: pinmux_micfil { + group0 { + pinmux = , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi index ae3499b0281ea..f4f70c9bfa07a 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi @@ -100,6 +100,19 @@ &flexcomm2_lpi2c2 { status = "okay"; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: da7212@1a { + compatible = "dialog,da7212"; + reg = <0x1a>; + clocks = <&syscon MCUX_SAI1_CLK>; + clock-source = "MCLK"; + clock-names = "mclk"; + }; }; /* From 89451d2c1d2bc41685f83ddbed4b8196dfd12ccf Mon Sep 17 00:00:00 2001 From: Tomas Barak Date: Fri, 3 Oct 2025 09:19:47 +0200 Subject: [PATCH 3/4] board: mcx_nx4x: format board.c - format mcx_nx4x_evk board.c Signed-off-by: Tomas Barak --- boards/nxp/mcx_nx4x_evk/board.c | 52 ++++++++++++++++----------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/boards/nxp/mcx_nx4x_evk/board.c b/boards/nxp/mcx_nx4x_evk/board.c index e5b69635a7ec5..a7b8f5f7cc43e 100644 --- a/boards/nxp/mcx_nx4x_evk/board.c +++ b/boards/nxp/mcx_nx4x_evk/board.c @@ -18,14 +18,16 @@ #define BOARD_USB_PHY_TXCAL45DM (0x07U) usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, }; #endif /* Board xtal frequency in Hz */ -#define BOARD_XTAL0_CLK_HZ 24000000U +#define BOARD_XTAL0_CLK_HZ 24000000U /* Core clock frequency: 150MHz */ -#define CLOCK_INIT_CORE_CLOCK 150000000U +#define CLOCK_INIT_CORE_CLOCK 150000000U /* System clock frequency. */ extern uint32_t SystemCoreClock; @@ -34,21 +36,21 @@ void power_mode_od(void) { /* Set the DCDC VDD regulator to 1.2 V voltage level */ spc_active_mode_dcdc_option_t opt = { - .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, }; SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ spc_active_mode_core_ldo_option_t ldo_opt = { - .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, }; SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt); /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ spc_sram_voltage_config_t cfg = { - .operateVoltage = kSPC_sramOperateAt1P2V, + .operateVoltage = kSPC_sramOperateAt1P2V, .requestVoltageUpdate = true, }; SPC_SetSRAMOperateVoltage(SPC0, &cfg); @@ -115,14 +117,12 @@ void board_early_init_hook(void) #endif /* Set up PLL0 */ - const pll_setup_t pll0Setup = { - .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | - SCG_APLLCTRL_SELP(13U), - .pllndiv = SCG_APLLNDIV_NDIV(8U), - .pllpdiv = SCG_APLLPDIV_PDIV(1U), - .pllmdiv = SCG_APLLMDIV_MDIV(50U), - .pllRate = 150000000U - }; + const pll_setup_t pll0Setup = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | + SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U}; /* Configure PLL0 to the desired values */ CLOCK_SetPLL0Freq(&pll0Setup); /* PLL0 Monitor is disabled */ @@ -136,15 +136,15 @@ void board_early_init_hook(void) CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ); -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || \ + DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil)) /* < Set up PLL1 */ - const pll_setup_t pll1_Setup = { - .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) | - SCG_SPLLCTRL_SELP(1U), - .pllndiv = SCG_SPLLNDIV_NDIV(25U), - .pllpdiv = SCG_SPLLPDIV_PDIV(10U), - .pllmdiv = SCG_SPLLMDIV_MDIV(256U), - .pllRate = 24576000U}; + const pll_setup_t pll1_Setup = {.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) | + SCG_SPLLCTRL_SELP(1U), + .pllndiv = SCG_SPLLNDIV_NDIV(25U), + .pllpdiv = SCG_SPLLPDIV_PDIV(10U), + .pllmdiv = SCG_SPLLMDIV_MDIV(256U), + .pllRate = 24576000U}; /* Configure PLL1 to the desired values */ CLOCK_SetPLL1Freq(&pll1_Setup); @@ -356,8 +356,8 @@ void board_early_init_hook(void) while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) { }; } - SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | - SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SYSCON->AHBCLKCTRLSET[2] |= + SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); /* xtal = 20 ~ 30MHz */ SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT); @@ -367,8 +367,8 @@ void board_early_init_hook(void) break; } } - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | - SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + SYSCON->CLOCK_CTRL |= + SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; CLOCK_EnableClock(kCLOCK_UsbHs); CLOCK_EnableClock(kCLOCK_UsbHsPhy); CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); From 2c9d813a04d0c806b7b2792829039695aba5ec56 Mon Sep 17 00:00:00 2001 From: Tomas Barak Date: Fri, 3 Oct 2025 09:21:31 +0200 Subject: [PATCH 4/4] samples: i2s_codec: enable i2s_codec sample for mcx_n5xx_evk - add mcx_n5xx_evk/mcxn547/cpu0 to sample.yaml - add mcx_n5xx_evk/mcxn547/cpu0 configuration and overlay Signed-off-by: Tomas Barak --- .../boards/mcx_n5xx_evk_mcxn547_cpu0.conf | 14 ++++++++++ .../boards/mcx_n5xx_evk_mcxn547_cpu0.overlay | 26 +++++++++++++++++++ samples/drivers/i2s/i2s_codec/sample.yaml | 1 + 3 files changed, 41 insertions(+) create mode 100644 samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.conf create mode 100644 samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.overlay diff --git a/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.conf b/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.conf new file mode 100644 index 0000000000000..a0a988423c494 --- /dev/null +++ b/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.conf @@ -0,0 +1,14 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_DMA_TCD_QUEUE_SIZE=4 +CONFIG_AUDIO_CODEC_DA7212=y +CONFIG_SAMPLE_FREQ=16000 +CONFIG_I2S_INIT_BUFFERS=1 +CONFIG_USE_CODEC_CLOCK=y +CONFIG_USE_DMIC=y +CONFIG_DMIC_CHANNELS=2 +CONFIG_EXTRA_BLOCKS=10 +CONFIG_SAMPLE_WIDTH=32 +CONFIG_BYTES_PER_SAMPLE=4 diff --git a/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.overlay b/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.overlay new file mode 100644 index 0000000000000..48695caef2f59 --- /dev/null +++ b/samples/drivers/i2s/i2s_codec/boards/mcx_n5xx_evk_mcxn547_cpu0.overlay @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2s-codec-tx = &sai1; + i2s-tx = &sai1; + }; +}; + +&sai1 { + mclk-output; +}; + +dmic_dev: &micfil { + channel0: micfil-channel@0 { + status = "okay"; + }; + + channel1: micfil-channel@1 { + status = "okay"; + }; +}; diff --git a/samples/drivers/i2s/i2s_codec/sample.yaml b/samples/drivers/i2s/i2s_codec/sample.yaml index 1fdc2a97322ea..1c628238a29d5 100644 --- a/samples/drivers/i2s/i2s_codec/sample.yaml +++ b/samples/drivers/i2s/i2s_codec/sample.yaml @@ -10,6 +10,7 @@ tests: - mimxrt1060_evk/mimxrt1062/qspi - mimxrt1180_evk/mimxrt1189/cm33 - mimxrt1180_evk/mimxrt1189/cm7 + - mcx_n5xx_evk/mcxn547/cpu0 harness: console harness_config: type: one_line