From 22c1bbef61fb2b8d7a34d8edb941bf17dd0dc34c Mon Sep 17 00:00:00 2001 From: Firas Sammoura Date: Tue, 7 Oct 2025 16:37:02 +0000 Subject: [PATCH] dt-bindings: riscv: Add fine-grained IO memory PMP attributes Introduce new macros to define bitfields for RISC-V Physical Memory Protection (PMP) attributes, specifically for specifying Read, Write, and Execute permissions for IO memory regions in device tree bindings. The following macros are added: - ATTR_RISCV_TYPE_IO_R: Read access - ATTR_RISCV_TYPE_IO_W: Write access - ATTR_RISCV_TYPE_IO_X: Execute access Corresponding macros for device tree usage are also added: - DT_MEM_RISCV_TYPE_IO_R - DT_MEM_RISCV_TYPE_IO_W - DT_MEM_RISCV_TYPE_IO_X These macros allow device tree source files to precisely describe the intended access permissions for memory-mapped IO regions, enhancing the system's memory protection configuration. Signed-off-by: Firas Sammoura --- .../memory-attr/memory-attr-riscv.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h b/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h index 5aebb111a56a8..9d903a364d894 100644 --- a/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h +++ b/include/zephyr/dt-bindings/memory-attr/memory-attr-riscv.h @@ -18,15 +18,21 @@ #define ATTR_RISCV_TYPE_MAIN BIT(0) #define ATTR_RISCV_TYPE_IO BIT(1) -#define ATTR_RISCV_TYPE_EMPTY BIT(2) -#define ATTR_RISCV_AMO_SWAP BIT(3) -#define ATTR_RISCV_AMO_LOGICAL BIT(4) -#define ATTR_RISCV_AMO_ARITHMETIC BIT(5) -#define ATTR_RISCV_IO_IDEMPOTENT_READ BIT(6) -#define ATTR_RISCV_IO_IDEMPOTENT_WRITE BIT(7) +#define ATTR_RISCV_TYPE_IO_R BIT(2) +#define ATTR_RISCV_TYPE_IO_W BIT(3) +#define ATTR_RISCV_TYPE_IO_X BIT(4) +#define ATTR_RISCV_TYPE_EMPTY BIT(5) +#define ATTR_RISCV_AMO_SWAP BIT(6) +#define ATTR_RISCV_AMO_LOGICAL BIT(7) +#define ATTR_RISCV_AMO_ARITHMETIC BIT(8) +#define ATTR_RISCV_IO_IDEMPOTENT_READ BIT(9) +#define ATTR_RISCV_IO_IDEMPOTENT_WRITE BIT(10) #define DT_MEM_RISCV_TYPE_MAIN DT_MEM_RISCV(ATTR_RISCV_TYPE_MAIN) #define DT_MEM_RISCV_TYPE_IO DT_MEM_RISCV(ATTR_RISCV_TYPE_IO) +#define DT_MEM_RISCV_TYPE_IO_R DT_MEM_RISCV(ATTR_RISCV_TYPE_IO_R) +#define DT_MEM_RISCV_TYPE_IO_W DT_MEM_RISCV(ATTR_RISCV_TYPE_IO_W) +#define DT_MEM_RISCV_TYPE_IO_X DT_MEM_RISCV(ATTR_RISCV_TYPE_IO_X) #define DT_MEM_RISCV_TYPE_EMPTY DT_MEM_RISCV(ATTR_RISCV_TYPE_EMPTY) #define DT_MEM_RISCV_AMO_SWAP DT_MEM_RISCV(ATTR_RISCV_AMO_SWAP) #define DT_MEM_RISCV_AMO_LOGICAL DT_MEM_RISCV(ATTR_RISCV_AMO_LOGICAL)