From fa4a4f36cbc98e804e58df5fee2f1ff91b8c5cba Mon Sep 17 00:00:00 2001 From: Henrik Lindblom Date: Wed, 8 Oct 2025 09:52:14 +0300 Subject: [PATCH] dts: stm32u5: disable otghs-phy by default The clock-reference property is marked as required in the bindings file. Without these changes creating new boards based on stm32u5 either requires explicitly disabling otghs_phy or setting the clock-reference -property. Signed-off-by: Henrik Lindblom --- boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts | 1 + boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts | 1 + boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts | 1 + boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts | 1 + dts/arm/st/u5/stm32u5_usbotg_hs.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts index 559a70fe93c5d..5f3af0171f2dd 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts @@ -85,4 +85,5 @@ zephyr_udc0: &usbotg_hs { &otghs_phy { clock-reference = "SYSCFG_OTG_HS_PHY_CLK_16MHz"; + status = "okay"; }; diff --git a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts index 7f0ee9ea38fa2..b5e73a4f04b51 100644 --- a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts @@ -259,6 +259,7 @@ zephyr_udc0: &usbotg_hs { &otghs_phy { clock-reference = "SYSCFG_OTG_HS_PHY_CLK_16MHz"; + status = "okay"; }; &flash0 { diff --git a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts b/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts index 7bce339137bd9..2f30bba33cdcc 100644 --- a/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts +++ b/boards/st/stm32u5g9j_dk1/stm32u5g9j_dk1.dts @@ -259,6 +259,7 @@ zephyr_udc0: &usbotg_hs { &otghs_phy { clock-reference = "SYSCFG_OTG_HS_PHY_CLK_16MHz"; + status = "okay"; }; &flash0 { diff --git a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts index 4f56a02eaa4dd..f3a9537b84059 100644 --- a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts +++ b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts @@ -298,6 +298,7 @@ zephyr_udc0: &usbotg_hs { &otghs_phy { clock-reference = "SYSCFG_OTG_HS_PHY_CLK_16MHz"; + status = "okay"; }; &flash0 { diff --git a/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi b/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi index c9de83ea72d14..cbfb5fa6e00c2 100644 --- a/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi +++ b/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi @@ -28,5 +28,6 @@ clocks = <&rcc STM32_CLOCK(AHB2, 15)>, <&rcc STM32_SRC_HSE OTGHS_SEL(0)>; #phy-cells = <0>; + status = "disabled"; }; };