From 6db4350ed89c0686684d1904c111c4229d151434 Mon Sep 17 00:00:00 2001
From: Amneesh Singh <amneesh@ti.com>
Date: Thu, 9 Oct 2025 15:29:31 +0530
Subject: [PATCH] soc: ti_k3: am6x: enable cache for R5 cores

Enable cache during soc early init for Cortex-R5F cores in the TI AM6x
series.

Signed-off-by: Amneesh Singh <amneesh@ti.com>
---
 soc/ti/k3/am6x/r5/soc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/soc/ti/k3/am6x/r5/soc.c b/soc/ti/k3/am6x/r5/soc.c
index 3142fdcd96f59..8efb94e478203 100644
--- a/soc/ti/k3/am6x/r5/soc.c
+++ b/soc/ti/k3/am6x/r5/soc.c
@@ -8,6 +8,7 @@
 #include <zephyr/fatal.h>
 
 #include "soc.h"
+#include <zephyr/cache.h>
 #include <common/ctrl_partitions.h>
 
 unsigned int z_soc_irq_get_active(void)
@@ -51,5 +52,10 @@ int z_soc_irq_is_enabled(unsigned int irq)
 
 void soc_early_init_hook(void)
 {
+	sys_cache_data_disable();
+	sys_cache_instr_disable();
+	sys_cache_data_enable();
+	sys_cache_instr_enable();
+
 	k3_unlock_all_ctrl_partitions();
 }