From cf59a9e4a4378983a52c73d52a694d758af18cf1 Mon Sep 17 00:00:00 2001 From: Shan Pen Date: Mon, 25 Aug 2025 21:44:40 +0800 Subject: [PATCH 1/3] dts: stm32: stm32h7rs: Add sdmmc1 and sdmmc2 configuration Provide the soc configuration for sdmmc1 and sdmmc2 controllers. This includes registers address, clocks, resets and interrupt line details. Signed-off-by: Shan Pen --- dts/arm/st/h7rs/stm32h7rs.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index 24d5a7925aace..7979c14c7f77d 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -908,6 +908,26 @@ resets = <&rctl STM32_RESET(APB5, 1)>; status = "disabled"; }; + + sdmmc1: sdmmc@52007000 { + compatible = "st,stm32-sdmmc"; + reg = <0x52007000 0x400>; + clocks = <&rcc STM32_CLOCK(AHB5, 8)>, + <&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>; + resets = <&rctl STM32_RESET(AHB5, 8)>; + interrupts = <108 0>; + status = "disabled"; + }; + + sdmmc2: sdmmc@48002400 { + compatible = "st,stm32-sdmmc"; + reg = <0x48002400 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 9)>, + <&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>; + resets = <&rctl STM32_RESET(AHB2, 9)>; + interrupts = <109 0>; + status = "disabled"; + }; }; otgfs_phy: otgfs_phy { From ab5dce7e03a1b16257e76ba382faa2536deb7656 Mon Sep 17 00:00:00 2001 From: Shan Pen Date: Mon, 25 Aug 2025 21:52:25 +0800 Subject: [PATCH 2/3] boards: art_pi2: Add SDMMC1 configuration with PLL2 kernel clock Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz SDMMC clock with clk-div = <13>. Signed-off-by: Shan Pen --- boards/ruiside/art_pi2/Kconfig.defconfig | 12 ++++++++++++ boards/ruiside/art_pi2/art_pi2.dts | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 boards/ruiside/art_pi2/Kconfig.defconfig diff --git a/boards/ruiside/art_pi2/Kconfig.defconfig b/boards/ruiside/art_pi2/Kconfig.defconfig new file mode 100644 index 0000000000000..51a9a9ce1771d --- /dev/null +++ b/boards/ruiside/art_pi2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ART-Pi2 board configuration +# +# Copyright (c) 2025 Shan Pen +# +# SPDX-License-Identifier: Apache-2.0 + +if DISK_DRIVER_SDMMC + +config SDMMC_STM32_CLOCK_CHECK + default n + +endif # DISK_DRIVER_SDMMC diff --git a/boards/ruiside/art_pi2/art_pi2.dts b/boards/ruiside/art_pi2/art_pi2.dts index e0fa2b3df9e88..a2469fca60918 100644 --- a/boards/ruiside/art_pi2/art_pi2.dts +++ b/boards/ruiside/art_pi2/art_pi2.dts @@ -80,6 +80,18 @@ status = "okay"; }; +&pll2 { + div-m = <2>; + mul-n = <50>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <4>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -98,6 +110,18 @@ status = "okay"; }; +&sdmmc1 { + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + clk-div = <13>; + bus-width = <4>; + cd-gpios = <&gpion 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + disk-name = "SD"; + status = "okay"; +}; + &rng { status = "okay"; }; From 44e3d05c27be3d6668c9c65e00cd407dcf15bd0c Mon Sep 17 00:00:00 2001 From: Shan Pen Date: Mon, 25 Aug 2025 22:00:07 +0800 Subject: [PATCH 3/3] boards: st: stm32h7s78_dk: Add PLL2 node and SDMMC1 node Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz SDMMC clock with clk-div = <13>. Signed-off-by: Shan Pen --- boards/st/stm32h7s78_dk/Kconfig.defconfig | 7 +++++++ boards/st/stm32h7s78_dk/stm32h7s78_dk.dts | 24 +++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/boards/st/stm32h7s78_dk/Kconfig.defconfig b/boards/st/stm32h7s78_dk/Kconfig.defconfig index de3982f531a19..3426fb7aa5b41 100644 --- a/boards/st/stm32h7s78_dk/Kconfig.defconfig +++ b/boards/st/stm32h7s78_dk/Kconfig.defconfig @@ -31,4 +31,11 @@ config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP default y endif # DISPLAY +if DISK_DRIVER_SDMMC + +config SDMMC_STM32_CLOCK_CHECK + default n + +endif # DISK_DRIVER_SDMMC + endif # BOARD_STM32H7S78_DK diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index 83f4b28bf53f3..f7fc3f6d1b2e3 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -109,6 +109,18 @@ status = "okay"; }; +&pll2 { + div-m = <2>; + mul-n = <50>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <4>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + &pll3 { div-m = <12>; mul-n = <25>; @@ -351,3 +363,15 @@ zephyr_udc0: &usb2 {}; def-back-color-green = <0xFF>; def-back-color-blue = <0xFF>; }; + +&sdmmc1 { + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + clk-div = <13>; + bus-width = <4>; + cd-gpios = <&gpiom 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + disk-name = "SD"; + status = "okay"; +};