From 8838493b287cdad5a9ebb1178f3fbecc96569102 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 09:21:06 +0200 Subject: [PATCH 1/9] soc: st: stm32: common: add common bitops functions Add a set of bitops functions in order to replace the STM32 HAL bitops macros throughout the drivers. Signed-off-by: Guillaume Gautier --- soc/st/stm32/common/stm32_bitops.h | 43 ++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 soc/st/stm32/common/stm32_bitops.h diff --git a/soc/st/stm32/common/stm32_bitops.h b/soc/st/stm32/common/stm32_bitops.h new file mode 100644 index 0000000000000..9c63b3c96db57 --- /dev/null +++ b/soc/st/stm32/common/stm32_bitops.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef STM32_BITOPS_H_ +#define STM32_BITOPS_H_ + +#include + +static ALWAYS_INLINE void stm32_reg_write(volatile uint32_t *addr, uint32_t value) +{ + sys_write32(value, (mem_addr_t)addr); +} + +static ALWAYS_INLINE uint32_t stm32_reg_read(volatile uint32_t *addr) +{ + return sys_read32((mem_addr_t)addr); +} + +static ALWAYS_INLINE void stm32_reg_set_bits(volatile uint32_t *addr, uint32_t mask) +{ + sys_set_bits((mem_addr_t)addr, mask); +} + +static ALWAYS_INLINE void stm32_reg_clear_bits(volatile uint32_t *addr, uint32_t mask) +{ + sys_clear_bits((mem_addr_t)addr, mask); +} + +static ALWAYS_INLINE uint32_t stm32_reg_read_bits(volatile uint32_t *addr, uint32_t mask) +{ + return sys_read32((mem_addr_t)addr) & mask; +} + +static ALWAYS_INLINE void stm32_reg_modify_bits(volatile uint32_t *addr, uint32_t mask, + uint32_t value) +{ + stm32_reg_write(addr, (stm32_reg_read(addr) & ~mask) | value); +} + +#endif /* STM32_BITOPS_H_ */ From 76f7f0af2513823c8b333709e099a7f1c6d2f4de Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 09:34:03 +0200 Subject: [PATCH 2/9] drivers: stm32: replace SET_BIT HAL macro by stm32_reg_set_bits For all STM32 drivers, replace the SET_BIT macro (defined in the STM32 HAL) by stm32_reg_set_bits defined in Zephyr. Signed-off-by: Guillaume Gautier --- drivers/adc/adc_stm32.c | 3 ++- drivers/clock_control/clock_stm32_ll_common.c | 4 ++-- drivers/clock_control/clock_stm32_ll_mp13.c | 3 ++- drivers/clock_control/clock_stm32_ll_u5.c | 13 +++++++------ drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c | 9 +++++---- drivers/usb_c/tcpc/ucpd_stm32.c | 3 ++- drivers/video/video_stm32_dcmipp.c | 10 +++++++--- 7 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 677c5101675e0..402e81fa426e5 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -569,7 +570,7 @@ static void adc_stm32_calibration_start(const struct device *dev, bool single_en __DMB(); MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); __DMB(); - SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF); + stm32_reg_set_bits(&adc->CALFACT, ADC_CALFACT_LATCH_COEF); adc_stm32_disable(adc); } } diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 2ec1e4a3f8be2..15a72bf400e46 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -75,12 +75,12 @@ #endif #if defined(RCC_PLLCFGR_PLLPEN) -#define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) +#define RCC_PLLP_ENABLE() stm32_reg_set_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) #else #define RCC_PLLP_ENABLE() #endif /* RCC_PLLCFGR_PLLPEN */ #if defined(RCC_PLLCFGR_PLLQEN) -#define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) +#define RCC_PLLQ_ENABLE() stm32_reg_set_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) #else #define RCC_PLLQ_ENABLE() #endif /* RCC_PLLCFGR_PLLQEN */ diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c index 6f8796ad73674..1366d209d8980 100644 --- a/drivers/clock_control/clock_stm32_ll_mp13.c +++ b/drivers/clock_control/clock_stm32_ll_mp13.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -273,7 +274,7 @@ static int stm32_clock_control_init(const struct device *dev) while (LL_RCC_PLL1_IsReady() != 1) { } - SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN); + stm32_reg_set_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN); while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) { }; diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index db9d63bbb0779..bfe39c8524860 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -8,6 +8,7 @@ #include +#include #include #include #include @@ -637,17 +638,17 @@ static int set_up_plls(void) if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR); - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); + stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); } if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) { LL_RCC_PLL2_SetQ(STM32_PLL2_Q_DIVISOR); - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); + stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); } if (IS_ENABLED(STM32_PLL2_R_ENABLED)) { LL_RCC_PLL2_SetR(STM32_PLL2_R_DIVISOR); - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); + stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); } LL_RCC_PLL2_Enable(); @@ -689,17 +690,17 @@ static int set_up_plls(void) if (IS_ENABLED(STM32_PLL3_P_ENABLED)) { LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); + stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); } if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) { LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR); - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); + stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); } if (IS_ENABLED(STM32_PLL3_R_ENABLED)) { LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR); - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); + stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); } LL_RCC_PLL3_Enable(); diff --git a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c index 0b8d7181d8641..13a4a1f5ca5d2 100644 --- a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c +++ b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c @@ -6,6 +6,7 @@ #define DT_DRV_COMPAT st_stm32_digi_temp +#include #include #include #include @@ -54,7 +55,7 @@ static void stm32_digi_temp_isr(const struct device *dev) DTS_TypeDef *dts = cfg->base; /* Clear interrupt */ - SET_BIT(dts->ICIFR, DTS_ICIFR_TS1_CITEF); + stm32_reg_set_bits(&dts->ICIFR, DTS_ICIFR_TS1_CITEF); /* Give semaphore */ k_sem_give(&data->sem_isr); @@ -78,7 +79,7 @@ static int stm32_digi_temp_sample_fetch(const struct device *dev, enum sensor_ch } /* Trigger a measurement */ - SET_BIT(dts->CFGR1, DTS_CFGR1_TS1_START); + stm32_reg_set_bits(&dts->CFGR1, DTS_CFGR1_TS1_START); CLEAR_BIT(dts->CFGR1, DTS_CFGR1_TS1_START); /* Wait for interrupt */ @@ -141,10 +142,10 @@ static void stm32_digi_temp_enable(const struct device *dev) DTS_TypeDef *dts = cfg->base; /* Enable the sensor */ - SET_BIT(dts->CFGR1, DTS_CFGR1_TS1_EN); + stm32_reg_set_bits(&dts->CFGR1, DTS_CFGR1_TS1_EN); /* Enable interrupt */ - SET_BIT(dts->ITENR, DTS_ITENR_TS1_ITEEN); + stm32_reg_set_bits(&dts->ITENR, DTS_ITENR_TS1_ITEEN); } #ifdef CONFIG_PM_DEVICE diff --git a/drivers/usb_c/tcpc/ucpd_stm32.c b/drivers/usb_c/tcpc/ucpd_stm32.c index 1ad7e081bf752..75fb3aedc0380 100644 --- a/drivers/usb_c/tcpc/ucpd_stm32.c +++ b/drivers/usb_c/tcpc/ucpd_stm32.c @@ -9,6 +9,7 @@ #include LOG_MODULE_REGISTER(ucpd_stm32, CONFIG_USBC_LOG_LEVEL); +#include #include #include #include @@ -385,7 +386,7 @@ static void dead_battery(const struct device *dev, bool en) if (en) { CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } else { - SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); + stm32_reg_set_bits(&PWR->CR3, PWR_CR3_UCPD_DBDIS); } #endif data->dead_battery_active = en; diff --git a/drivers/video/video_stm32_dcmipp.c b/drivers/video/video_stm32_dcmipp.c index ff0ec996aa089..a3114784920f2 100644 --- a/drivers/video/video_stm32_dcmipp.c +++ b/drivers/video/video_stm32_dcmipp.c @@ -6,6 +6,7 @@ #include +#include #include #include #include @@ -1298,13 +1299,16 @@ static int stm32_dcmipp_enqueue(const struct device *dev, struct video_buffer *v pipe->next = vbuf; stm32_dcmipp_set_next_buffer_addr(pipe); if (pipe->id == DCMIPP_PIPE0) { - SET_BIT(dcmipp->hdcmipp.Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + stm32_reg_set_bits(&dcmipp->hdcmipp.Instance->P0FCTCR, + DCMIPP_P0FCTCR_CPTREQ); } #if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) else if (pipe->id == DCMIPP_PIPE1) { - SET_BIT(dcmipp->hdcmipp.Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ); + stm32_reg_set_bits(&dcmipp->hdcmipp.Instance->P1FCTCR, + DCMIPP_P1FCTCR_CPTREQ); } else if (pipe->id == DCMIPP_PIPE2) { - SET_BIT(dcmipp->hdcmipp.Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ); + stm32_reg_set_bits(&dcmipp->hdcmipp.Instance->P2FCTCR, + DCMIPP_P2FCTCR_CPTREQ); } #endif pipe->state = STM32_DCMIPP_RUNNING; From 08c9ecc3d8fa7a87d613c5463d6bb977e95205d2 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 09:35:53 +0200 Subject: [PATCH 3/9] drivers: stm32: replace CLEAR_BIT HAL macro by stm32_reg_clear_bits For all STM32 drivers, replace the CLEAR_BIT macro (defined in the STM32 HAL) by stm32_reg_clear_bits defined in Zephyr. Signed-off-by: Guillaume Gautier --- drivers/clock_control/clock_stm32_ll_mp13.c | 6 +++--- drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c | 6 +++--- drivers/usb_c/tcpc/ucpd_stm32.c | 2 +- drivers/video/video_stm32_dcmipp.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c index 1366d209d8980..0b7ffe8d6d37c 100644 --- a/drivers/clock_control/clock_stm32_ll_mp13.c +++ b/drivers/clock_control/clock_stm32_ll_mp13.c @@ -240,15 +240,15 @@ static int stm32_clock_control_init(const struct device *dev) while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) { } - CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN); + stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN); while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) { }; - CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN); + stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVQEN); while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) { }; - CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN); + stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVREN); while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) { }; diff --git a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c index 13a4a1f5ca5d2..2fecae8e2436f 100644 --- a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c +++ b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c @@ -80,7 +80,7 @@ static int stm32_digi_temp_sample_fetch(const struct device *dev, enum sensor_ch /* Trigger a measurement */ stm32_reg_set_bits(&dts->CFGR1, DTS_CFGR1_TS1_START); - CLEAR_BIT(dts->CFGR1, DTS_CFGR1_TS1_START); + stm32_reg_clear_bits(&dts->CFGR1, DTS_CFGR1_TS1_START); /* Wait for interrupt */ k_sem_take(&data->sem_isr, K_FOREVER); @@ -155,10 +155,10 @@ static void stm32_digi_temp_disable(const struct device *dev) DTS_TypeDef *dts = cfg->base; /* Disable interrupt */ - CLEAR_BIT(dts->ITENR, DTS_ITENR_TS1_ITEEN); + stm32_reg_clear_bits(&dts->ITENR, DTS_ITENR_TS1_ITEEN); /* Disable the sensor */ - CLEAR_BIT(dts->CFGR1, DTS_CFGR1_TS1_EN); + stm32_reg_clear_bits(&dts->CFGR1, DTS_CFGR1_TS1_EN); } #endif diff --git a/drivers/usb_c/tcpc/ucpd_stm32.c b/drivers/usb_c/tcpc/ucpd_stm32.c index 75fb3aedc0380..71e45bf015f84 100644 --- a/drivers/usb_c/tcpc/ucpd_stm32.c +++ b/drivers/usb_c/tcpc/ucpd_stm32.c @@ -384,7 +384,7 @@ static void dead_battery(const struct device *dev, bool en) update_stm32g0x_cc_line(config->ucpd_port); #else if (en) { - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); + stm32_reg_clear_bits(&PWR->CR3, PWR_CR3_UCPD_DBDIS); } else { stm32_reg_set_bits(&PWR->CR3, PWR_CR3_UCPD_DBDIS); } diff --git a/drivers/video/video_stm32_dcmipp.c b/drivers/video/video_stm32_dcmipp.c index a3114784920f2..e7ffa2c023586 100644 --- a/drivers/video/video_stm32_dcmipp.c +++ b/drivers/video/video_stm32_dcmipp.c @@ -253,13 +253,13 @@ void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t */ pipe->state = STM32_DCMIPP_WAIT_FOR_BUFFER; if (Pipe == DCMIPP_PIPE0) { - CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + stm32_reg_clear_bits(&hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); } #if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) else if (Pipe == DCMIPP_PIPE1) { - CLEAR_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ); + stm32_reg_clear_bits(&hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ); } else if (Pipe == DCMIPP_PIPE2) { - CLEAR_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ); + stm32_reg_clear_bits(&hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ); } #endif return; From a39948791654a6bc42900730915d9205923918f5 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 10:11:28 +0200 Subject: [PATCH 4/9] drivers: stm32: replace READ_BIT HAL macro by stm32_reg_read_bits For all STM32 drivers and SoC, replace the READ_BIT macro (defined in the STM32 HAL) by stm32_reg_read_bits. Fixes some cases where the return value was tested like a boolean despite not being one. Signed-off-by: Guillaume Gautier --- drivers/clock_control/clock_stm32_ll_mp13.c | 11 ++++++----- drivers/clock_control/clock_stm32_ll_u5.c | 5 +++-- drivers/entropy/entropy_stm32.c | 7 ++++--- drivers/flash/flash_stm32_ospi.c | 6 +++--- drivers/flash/flash_stm32_qspi.c | 4 +++- drivers/flash/flash_stm32_xspi.c | 3 ++- drivers/flash/flash_stm32g4x.c | 3 ++- drivers/flash/flash_stm32h7x.c | 6 ++++-- drivers/flash/flash_stm32wb0x.c | 3 ++- drivers/i3c/i3c_stm32.c | 3 ++- drivers/rtc/rtc_ll_stm32.c | 5 +++-- drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c | 2 +- soc/st/stm32/stm32h7x/soc_m7.c | 2 +- soc/st/stm32/stm32wbax/power.c | 5 +++-- .../src/test_stm32_clock_configuration.c | 9 ++++++--- .../stm32h7_core/src/test_stm32_clock_configuration.c | 7 +++++-- .../stm32n6_core/src/test_stm32_clock_configuration.c | 7 +++++-- 17 files changed, 55 insertions(+), 33 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c index 0b7ffe8d6d37c..bf8001b3b2edf 100644 --- a/drivers/clock_control/clock_stm32_ll_mp13.c +++ b/drivers/clock_control/clock_stm32_ll_mp13.c @@ -237,19 +237,20 @@ static int stm32_clock_control_init(const struct device *dev) /* while active.*/ LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE); - while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) { + while (stm32_reg_read_bits(&RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != + RCC_MPCKSELR_MPUSRCRDY) { } stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN); - while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) { + while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) { }; stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVQEN); - while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) { + while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) { }; stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVREN); - while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) { + while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) { }; uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n); @@ -275,7 +276,7 @@ static int stm32_clock_control_init(const struct device *dev) } stm32_reg_set_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN); - while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) { + while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) { }; LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_PLL1); diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index bfe39c8524860..d7b69a9b90d05 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -906,11 +906,12 @@ int stm32_clock_control_init(const struct device *dev) /* Disable unused clocks that are enabled (e.g. by bootloader or as wakeup source). * These will not be enabled, unless the MCU uses them for PM wakeup purposes. */ - if (!IS_ENABLED(STM32_MSIS_ENABLED) && (READ_BIT(RCC->CR, RCC_CR_MSISON) != 0U)) { + if (!IS_ENABLED(STM32_MSIS_ENABLED) && + (stm32_reg_read_bits(&RCC->CR, RCC_CR_MSISON) != 0U)) { LL_RCC_MSIS_Disable(); } - if (!IS_ENABLED(STM32_HSI_ENABLED) && (READ_BIT(RCC->CR, RCC_CR_HSION) != 0U)) { + if (!IS_ENABLED(STM32_HSI_ENABLED) && (stm32_reg_read_bits(&RCC->CR, RCC_CR_HSION) != 0U)) { LL_RCC_HSI_Disable(); } #endif diff --git a/drivers/entropy/entropy_stm32.c b/drivers/entropy/entropy_stm32.c index ac2062f5a4b63..c8698a87deb5c 100644 --- a/drivers/entropy/entropy_stm32.c +++ b/drivers/entropy/entropy_stm32.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -209,9 +210,9 @@ static void configure_rng(void) * The RNG clock must be 48MHz else the clock DIV is not adpated. * The RNG_CR_CONDRST is set to 1 at the same time the RNG_CR is written */ - cur_nist_cfg = READ_BIT(rng->CR, - (RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 | - RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 + cur_nist_cfg = stm32_reg_read_bits(&rng->CR, + (RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 | + RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 #if defined(RNG_CR_ARDIS) | RNG_CR_ARDIS /* For STM32U5 series, the ARDIS bit7 is considered in the nist-config */ diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index 17592b008e194..08178a02259e1 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1139,9 +1140,8 @@ static bool stm32_ospi_is_memorymap(const struct device *dev) { struct flash_stm32_ospi_data *dev_data = dev->data; - return ((READ_BIT(dev_data->hospi.Instance->CR, - OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ? - true : false); + return stm32_reg_read_bits(&dev_data->hospi.Instance->CR, OCTOSPI_CR_FMODE) == + OCTOSPI_CR_FMODE; } static int stm32_ospi_abort(const struct device *dev) diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c index 83b945cc93b27..30ee0831553d4 100644 --- a/drivers/flash/flash_stm32_qspi.c +++ b/drivers/flash/flash_stm32_qspi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -578,7 +579,8 @@ static bool stm32_qspi_is_memory_mapped(const struct device *dev) { struct flash_stm32_qspi_data *dev_data = dev->data; - return READ_BIT(dev_data->hqspi.Instance->CCR, QUADSPI_CCR_FMODE) == QUADSPI_CCR_FMODE; + return stm32_reg_read_bits(&dev_data->hqspi.Instance->CCR, QUADSPI_CCR_FMODE) == + QUADSPI_CCR_FMODE; } static int stm32_qspi_abort(const struct device *dev) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 75a5a151921a5..feef05889f271 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1017,7 +1018,7 @@ static bool stm32_xspi_is_memorymap(const struct device *dev) { struct flash_stm32_xspi_data *dev_data = dev->data; - return READ_BIT(dev_data->hxspi.Instance->CR, XSPI_CR_FMODE) == XSPI_CR_FMODE; + return stm32_reg_read_bits(&dev_data->hxspi.Instance->CR, XSPI_CR_FMODE) == XSPI_CR_FMODE; } #endif diff --git a/drivers/flash/flash_stm32g4x.c b/drivers/flash/flash_stm32g4x.c index 3c26874b1a9ce..50e62f0e2f66a 100644 --- a/drivers/flash/flash_stm32g4x.c +++ b/drivers/flash/flash_stm32g4x.c @@ -16,6 +16,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN); #include #include #include +#include #include #include "flash_stm32.h" @@ -369,7 +370,7 @@ void flash_stm32_page_layout(const struct device *dev, int flash_stm32_check_configuration(void) { #if defined(FLASH_STM32_DBANK) - if (READ_BIT(FLASH->OPTR, FLASH_STM32_DBANK) == 0U) { + if (stm32_reg_read_bits(&FLASH->OPTR, FLASH_STM32_DBANK) == 0U) { /* Single bank not supported when dualbank is possible */ LOG_ERR("Single bank configuration not supported"); return -ENOTSUP; diff --git a/drivers/flash/flash_stm32h7x.c b/drivers/flash/flash_stm32h7x.c index c30d685d55c35..b084e6914b57c 100644 --- a/drivers/flash/flash_stm32h7x.c +++ b/drivers/flash/flash_stm32h7x.c @@ -14,6 +14,7 @@ #include #include #include +#include #if defined(CONFIG_SOC_SERIES_STM32H7RSX) #include #include @@ -465,9 +466,10 @@ static struct flash_stm32_sector_t get_sector(const struct device *dev, off_t of #ifdef DUAL_BANK off_t temp_offset = offset + (CONFIG_FLASH_BASE_ADDRESS & 0xffffff); - bool bank_swap; /* Check whether bank1/2 are swapped */ - bank_swap = (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == FLASH_OPTCR_SWAP_BANK); + bool bank_swap = stm32_reg_read_bits(&FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == + FLASH_OPTCR_SWAP_BANK; + sector.sector_index = offset / FLASH_SECTOR_SIZE; if ((temp_offset < (REAL_FLASH_SIZE_KB / 2)) && !bank_swap) { sector.bank = 1; diff --git a/drivers/flash/flash_stm32wb0x.c b/drivers/flash/flash_stm32wb0x.c index a2d4287a0e02b..c054bbe711207 100644 --- a/drivers/flash/flash_stm32wb0x.c +++ b/drivers/flash/flash_stm32wb0x.c @@ -19,6 +19,7 @@ * _MEMORY_FLASH_SIZE_ respectively. */ #include +#include #include #include #include @@ -74,7 +75,7 @@ static inline size_t get_flash_size_in_bytes(void) * minus one. */ const uint32_t words_in_flash = - READ_BIT(FLASH->SIZE, FLASH_FLASH_SIZE_FLASH_SIZE) + 1; + stm32_reg_read_bits(&FLASH->SIZE, FLASH_FLASH_SIZE_FLASH_SIZE) + 1; return words_in_flash * WORD_SIZE; } diff --git a/drivers/i3c/i3c_stm32.c b/drivers/i3c/i3c_stm32.c index 0243ae8c2587d..80651a0747a75 100644 --- a/drivers/i3c/i3c_stm32.c +++ b/drivers/i3c/i3c_stm32.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -1293,7 +1294,7 @@ static int i3c_stm32_i3c_transfer(const struct device *dev, struct i3c_device_de #ifdef CONFIG_I3C_STM32_DMA /* Fill the num_xfer for each message from the status FIFO */ for (size_t i = 0; i < num_msgs; i++) { - msgs[i].num_xfer = READ_BIT(data->status_fifo[i], I3C_SR_XDCNT); + msgs[i].num_xfer = stm32_reg_read_bits(&data->status_fifo[i], I3C_SR_XDCNT); } k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo); diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c index 11077ebb3b467..5c05d6f32f887 100644 --- a/drivers/rtc/rtc_ll_stm32.c +++ b/drivers/rtc/rtc_ll_stm32.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -1069,8 +1070,8 @@ static int rtc_stm32_get_calibration(const struct device *dev, int32_t *calibrat uint32_t calr = sys_read32((mem_addr_t) &RTC->CALR); - bool calp_enabled = READ_BIT(calr, RTC_CALR_CALP); - uint32_t calm = READ_BIT(calr, RTC_CALR_CALM); + bool calp_enabled = stm32_reg_read_bits(&calr, RTC_CALR_CALP) == RTC_CALR_CALP; + uint32_t calm = stm32_reg_read_bits(&calr, RTC_CALR_CALM); int32_t nb_pulses = -((int32_t) calm); diff --git a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c index 2fecae8e2436f..37f421aebc474 100644 --- a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c +++ b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c @@ -74,7 +74,7 @@ static int stm32_digi_temp_sample_fetch(const struct device *dev, enum sensor_ch k_mutex_lock(&data->mutex, K_FOREVER); /* Wait for the sensor to be ready (~40µS delay after enabling it) */ - while (READ_BIT(dts->SR, DTS_SR_TS1_RDY) == 0) { + while (stm32_reg_read_bits(&dts->SR, DTS_SR_TS1_RDY) == 0) { k_yield(); } diff --git a/soc/st/stm32/stm32h7x/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c index 48b2190d4c9fc..cf45837027f12 100644 --- a/soc/st/stm32/stm32h7x/soc_m7.c +++ b/soc/st/stm32/stm32h7x/soc_m7.c @@ -47,7 +47,7 @@ static int stm32h7_m4_wakeup(void) LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM); LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG); - if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { + if (stm32_reg_read_bits(&SYSCFG->UR1, SYSCFG_UR1_BCM4) != 0) { /** * Cortex-M4 has been started by hardware. * Its `soc_early_init_hook()` will stall boot until diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c index 73e81d291f84e..3ac7680bae6a2 100644 --- a/soc/st/stm32/stm32wbax/power.c +++ b/soc/st/stm32/stm32wbax/power.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,7 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); -#define HSE_ON (READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) +#define HSE_ON (stm32_reg_read_bits(&RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) static uint32_t ram_waitstates_backup; static uint32_t flash_latency_backup; @@ -161,7 +162,7 @@ static void set_mode_stop_enter(uint8_t substate_id) while (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_1) { } } - ram_waitstates_backup = READ_BIT(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC); + ram_waitstates_backup = stm32_reg_read_bits(&RAMCFG_SRAM1->CR, RAMCFG_CR_WSC); MODIFY_REG(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); MODIFY_REG(RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); } diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/test_stm32_clock_configuration.c index 826ba2c68d8f3..840d850205b7e 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/test_stm32_clock_configuration.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -91,7 +92,7 @@ ZTEST(stm32_sysclck_config, test_pll_src) defined(CONFIG_SOC_SERIES_STM32F4X) || defined(CONFIG_SOC_SERIES_STM32F7X) #define RCC_PLLSOURCE_NONE 0 /* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */ - if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { + if (stm32_reg_read_bits(&RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { /* should not happen : PLL must be disabled when not used */ pll_src = 0xFFFF; /* error code */ } else { @@ -111,9 +112,11 @@ ZTEST(stm32_sysclck_config, test_hse_css) { /* there is no function to read CSS status, so read directly from the register */ #if STM32_HSE_CSS - zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled"); + zassert_true(stm32_reg_read_bits(&RCC->CR, RCC_CR_CSSON) == RCC_CR_CSSON, + "HSE CSS is not enabled"); #else - zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled"); + zassert_false(stm32_reg_read_bits(&RCC->CR, RCC_CR_CSSON) == RCC_CR_CSSON, + "HSE CSS unexpectedly enabled"); #endif /* STM32_HSE_CSS */ } diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/test_stm32_clock_configuration.c index f61e5107d2120..8cb53e9d7f55e 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/test_stm32_clock_configuration.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -82,9 +83,11 @@ ZTEST(stm32_syclck_config, test_hse_css) { /* there is no function to read CSS status, so read directly from the register */ #if STM32_HSE_CSS - zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS is not enabled"); + zassert_true(stm32_reg_read_bits(&RCC->CR, RCC_CR_CSSHSEON) == RCC_CR_CSSHSEON, + "HSE CSS is not enabled"); #else - zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS unexpectedly enabled"); + zassert_false(stm32_reg_read_bits(&RCC->CR, RCC_CR_CSSHSEON) == RCC_CR_CSSHSEON, + "HSE CSS unexpectedly enabled"); #endif /* STM32_HSE_CSS */ } diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c index b72ada29d843b..bc6193ff23dcb 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -106,7 +107,8 @@ ZTEST(stm32n6_clock_core_config, test_pll_src) ZTEST(stm32n6_clock_core_config, test_hse_css) { /* there is no function to read CSS status, so read directly from the SoC register */ - bool css_enabled = (READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSON) == 1U); + bool css_enabled = stm32_reg_read_bits(&RCC->HSECFGR, RCC_HSECFGR_HSECSSON) == + RCC_HSECFGR_HSECSSON; if (IS_ENABLED(STM32_HSE_CSS)) { zassert_true(css_enabled, "HSE CSS is not enabled"); @@ -120,7 +122,8 @@ ZTEST(stm32n6_clock_core_config, test_hse_css) ZTEST(stm32n6_clock_core_config, test_lse_css) { /* there is no function to read CSS status, so read directly from the SoC register */ - bool css_enabled = (READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON) == 1U); + bool css_enabled = stm32_reg_read_bits(&RCC->LSECFGR, RCC_LSECFGR_LSECSSON) == + RCC_LSECFGR_LSECSSON; if (IS_ENABLED(STM32_LSE_CSS)) { zassert_true(css_enabled, "LSE CSS is not enabled"); From 17f39f2b1b88fdde25757c5f3757872662251e14 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 10:16:20 +0200 Subject: [PATCH 5/9] drivers: stm32: replace WRITE_REG HAL macro by stm32_reg_write For all STM32 drivers and SoC, replace the WRITE_REG macro and the LL_xxx_WriteReg functions (defined in the STM32 HAL) by stm32_reg_write defined in Zephyr. Signed-off-by: Guillaume Gautier --- drivers/counter/counter_ll_stm32_rtc.c | 43 +++++++++++------------ drivers/entropy/entropy_stm32.h | 3 +- drivers/gpio/gpio_stm32.c | 7 ++-- drivers/i2c/i2c_ll_stm32_v1.c | 17 +++++----- drivers/i2c/i2c_ll_stm32_v1_rtio.c | 3 +- drivers/i2c/i2c_ll_stm32_v2.c | 9 ++--- drivers/i3c/i3c_stm32.c | 14 ++++---- drivers/usb_c/tcpc/ucpd_stm32.c | 47 ++++++++++++-------------- drivers/video/video_stm32_dcmipp.c | 10 +++--- 9 files changed, 77 insertions(+), 76 deletions(-) diff --git a/drivers/counter/counter_ll_stm32_rtc.c b/drivers/counter/counter_ll_stm32_rtc.c index fe97936915efa..b1838d53079a3 100644 --- a/drivers/counter/counter_ll_stm32_rtc.c +++ b/drivers/counter/counter_ll_stm32_rtc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -270,46 +271,46 @@ static int rtc_stm32_deinit(void) } #if defined(CONFIG_SOC_SERIES_STM32F1X) - WRITE_REG(RTC->CNTL, 0U); - WRITE_REG(RTC->CNTH, 0U); - WRITE_REG(RTC->PRLH, 0U); - WRITE_REG(RTC->PRLL, 0x8000U); - WRITE_REG(RTC->CRH, 0U); - WRITE_REG(RTC->CRL, 0x20U); + stm32_reg_write(&RTC->CNTL, 0U); + stm32_reg_write(&RTC->CNTH, 0U); + stm32_reg_write(&RTC->PRLH, 0U); + stm32_reg_write(&RTC->PRLL, 0x8000U); + stm32_reg_write(&RTC->CRH, 0U); + stm32_reg_write(&RTC->CRL, 0x20U); #else /* CONFIG_SOC_SERIES_STM32F1X */ - WRITE_REG(RTC->CR, 0U); - WRITE_REG(RTC->TR, 0U); + stm32_reg_write(&RTC->CR, 0U); + stm32_reg_write(&RTC->TR, 0U); #ifdef RTC_WUTR_WUT - WRITE_REG(RTC->WUTR, RTC_WUTR_WUT); + stm32_reg_write(&RTC->WUTR, RTC_WUTR_WUT); #endif /* RTC_WUTR_WUT */ - WRITE_REG(RTC->DR, RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); - WRITE_REG(RTC->PRER, RTC_PRER_PREDIV_A | 0xFFU); - WRITE_REG(RTC->ALRMAR, 0U); + stm32_reg_write(&RTC->DR, RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); + stm32_reg_write(&RTC->PRER, RTC_PRER_PREDIV_A | 0xFFU); + stm32_reg_write(&RTC->ALRMAR, 0U); #ifdef RTC_CR_ALRBE - WRITE_REG(RTC->ALRMBR, 0U); + stm32_reg_write(&RTC->ALRMBR, 0U); #endif /* RTC_CR_ALRBE */ #if HW_SUBSECOND_SUPPORT - WRITE_REG(RTC->CALR, 0U); - WRITE_REG(RTC->SHIFTR, 0U); - WRITE_REG(RTC->ALRMASSR, 0U); + stm32_reg_write(&RTC->CALR, 0U); + stm32_reg_write(&RTC->SHIFTR, 0U); + stm32_reg_write(&RTC->ALRMASSR, 0U); #ifdef RTC_CR_ALRBE - WRITE_REG(RTC->ALRMBSSR, 0U); + stm32_reg_write(&RTC->ALRMBSSR, 0U); #endif /* RTC_CR_ALRBE */ #endif /* HW_SUBSECOND_SUPPORT */ #if defined(RTC_PRIVCFGR_PRIV) - WRITE_REG(RTC->PRIVCFGR, 0U); + stm32_reg_write(&RTC->PRIVCFGR, 0U); #endif /* RTC_PRIVCFGR_PRIV */ #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - WRITE_REG(RTC->SECCFGR, 0U); + stm32_reg_write(&RTC->SECCFGR, 0U); #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Reset I(C)SR register and exit initialization mode */ #ifdef RTC_ICSR_INIT - WRITE_REG(RTC->ICSR, 0U); + stm32_reg_write(&RTC->ICSR, 0U); #else - WRITE_REG(RTC->ISR, 0U); + stm32_reg_write(&RTC->ISR, 0U); #endif #endif /* CONFIG_SOC_SERIES_STM32F1X */ diff --git a/drivers/entropy/entropy_stm32.h b/drivers/entropy/entropy_stm32.h index 420841c20203c..13035c3083ae2 100644 --- a/drivers/entropy/entropy_stm32.h +++ b/drivers/entropy/entropy_stm32.h @@ -5,6 +5,7 @@ */ #include #include +#include #include /** @@ -109,7 +110,7 @@ static inline rng_sample_t ll_rng_read_rand_data(RNG_TypeDef *RNGx) * Raw register access is performed because STM32CubeWB0 v1.0.0 * package is lacking the LL function to clear IRQ flags. */ - WRITE_REG(RNG->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ); + stm32_reg_write(&RNGx->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ); return rnd; #elif defined(CONFIG_SOC_SERIES_STM32WB0X) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 3d8830c0d454e..e828049618a78 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -407,7 +408,7 @@ static int gpio_stm32_port_set_bits_raw(const struct device *dev, * On F1 series, using LL API requires a costly pin mask translation. * Skip it and use CMSIS API directly. Valid also on other series. */ - WRITE_REG(gpio->BSRR, pins); + stm32_reg_write(&gpio->BSRR, pins); return 0; } @@ -423,7 +424,7 @@ static int gpio_stm32_port_clear_bits_raw(const struct device *dev, * On F1 series, using LL API requires a costly pin mask translation. * Skip it and use CMSIS API directly. */ - WRITE_REG(gpio->BRR, pins); + stm32_reg_write(&gpio->BRR, pins); #else /* On other series, LL abstraction is needed */ LL_GPIO_ResetOutputPin(gpio, pins); @@ -443,7 +444,7 @@ static int gpio_stm32_port_toggle_bits(const struct device *dev, * Skip it and use CMSIS API directly. Valid also on other series. */ z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - WRITE_REG(gpio->ODR, READ_REG(gpio->ODR) ^ pins); + stm32_reg_write(&gpio->ODR, READ_REG(gpio->ODR) ^ pins); z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); return 0; diff --git a/drivers/i2c/i2c_ll_stm32_v1.c b/drivers/i2c/i2c_ll_stm32_v1.c index 5ae79b762592d..953ba797b3814 100644 --- a/drivers/i2c/i2c_ll_stm32_v1.c +++ b/drivers/i2c/i2c_ll_stm32_v1.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,7 @@ static void i2c_stm32_generate_start_condition(I2C_TypeDef *i2c) if (cr1 & I2C_CR1_STOP) { LOG_DBG("%s: START while STOP active!", __func__); - LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP); + stm32_reg_write(&i2c->CR1, cr1 & ~I2C_CR1_STOP); } LL_I2C_GenerateStartCondition(i2c); @@ -102,17 +103,17 @@ static void i2c_stm32_reset(const struct device *dev) LL_I2C_DisableReset(i2c); /* restore all important registers after reset */ - LL_I2C_WriteReg(i2c, CR1, cr1); - LL_I2C_WriteReg(i2c, CR2, cr2); + stm32_reg_write(&i2c->CR1, cr1); + stm32_reg_write(&i2c->CR2, cr2); /* bit 14 of OAR1 must always be 1 */ oar1 |= (1 << 14); - LL_I2C_WriteReg(i2c, OAR1, oar1); - LL_I2C_WriteReg(i2c, OAR2, oar2); - LL_I2C_WriteReg(i2c, CCR, ccr); - LL_I2C_WriteReg(i2c, TRISE, trise); + stm32_reg_write(&i2c->OAR1, oar1); + stm32_reg_write(&i2c->OAR2, oar2); + stm32_reg_write(&i2c->CCR, ccr); + stm32_reg_write(&i2c->TRISE, trise); #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF) - LL_I2C_WriteReg(i2c, FLTR, fltr); + stm32_reg_write(&i2c->FLTR, fltr); #endif } diff --git a/drivers/i2c/i2c_ll_stm32_v1_rtio.c b/drivers/i2c/i2c_ll_stm32_v1_rtio.c index d07c40bbcd4b5..5ebcfa2eeea99 100644 --- a/drivers/i2c/i2c_ll_stm32_v1_rtio.c +++ b/drivers/i2c/i2c_ll_stm32_v1_rtio.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -57,7 +58,7 @@ static void i2c_stm32_generate_start_condition(I2C_TypeDef *i2c) if ((cr1 & I2C_CR1_STOP) != 0) { LOG_DBG("%s: START while STOP active!", __func__); - LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP); + stm32_reg_write(&i2c->CR1, cr1 & ~I2C_CR1_STOP); } LL_I2C_GenerateStartCondition(i2c); diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 98b1fd256b023..5ac39b5bcf830 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -535,7 +536,7 @@ void i2c_stm32_event(const struct device *dev) * remaining in current message * Keep RELOAD mode and set NBYTES to 255 again */ - LL_I2C_WriteReg(regs, CR2, cr2); + stm32_reg_write(®s->CR2, cr2); } else { /* Data for a single transfer remains in buffer, set its length and * - If more messages follow and transfer direction for next message is @@ -550,7 +551,7 @@ void i2c_stm32_event(const struct device *dev) /* Disable reload mode, expect I2C_ISR_TC next */ cr2 &= ~I2C_CR2_RELOAD; } - LL_I2C_WriteReg(regs, CR2, cr2); + stm32_reg_write(®s->CR2, cr2); } } else if ((isr & I2C_ISR_TXIS) != 0U) { @@ -812,12 +813,12 @@ static int stm32_i2c_irq_xfer(const struct device *dev, struct i2c_msg *msg, #endif /* CONFIG_I2C_STM32_V2_DMA */ /* Commit configuration to I2C controller and start transfer */ - LL_I2C_WriteReg(regs, CR2, cr2); + stm32_reg_write(®s->CR2, cr2); cr1 |= LL_I2C_ReadReg(regs, CR1); /* Enable interrupts */ - LL_I2C_WriteReg(regs, CR1, cr1); + stm32_reg_write(®s->CR1, cr1); /* Wait for transfer to finish */ return stm32_i2c_irq_msg_finish(dev, msg); diff --git a/drivers/i3c/i3c_stm32.c b/drivers/i3c/i3c_stm32.c index 80651a0747a75..3bbc1edea8472 100644 --- a/drivers/i3c/i3c_stm32.c +++ b/drivers/i3c/i3c_stm32.c @@ -1208,13 +1208,13 @@ static int i3c_stm32_transfer_begin(const struct device *dev) /* Prepare all control words for all messages on the transfer */ for (size_t i = 0; i < curr_msg->num_msgs; i++) { - WRITE_REG(data->control_fifo[i], - ((curr_msg->target_addr << I3C_CR_ADD_Pos) | - i3c_stm32_curr_msg_control_get_len(dev) | - i3c_stm32_curr_msg_control_get_dir(dev) | curr_msg->msg_type | - i3c_stm32_curr_msg_control_get_end(dev)) & - (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | - I3C_CR_MEND)); + stm32_reg_write(&data->control_fifo[i], + ((curr_msg->target_addr << I3C_CR_ADD_Pos) | + i3c_stm32_curr_msg_control_get_len(dev) | + i3c_stm32_curr_msg_control_get_dir(dev) | curr_msg->msg_type | + i3c_stm32_curr_msg_control_get_end(dev)) & + (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | + I3C_CR_MEND)); i3c_stm32_curr_msg_control_next(dev); } diff --git a/drivers/usb_c/tcpc/ucpd_stm32.c b/drivers/usb_c/tcpc/ucpd_stm32.c index 71e45bf015f84..863c6cc3c1c12 100644 --- a/drivers/usb_c/tcpc/ucpd_stm32.c +++ b/drivers/usb_c/tcpc/ucpd_stm32.c @@ -115,12 +115,10 @@ static void ucpd_tx_interrupts_enable(const struct device *dev, bool enable) imr = LL_UCPD_ReadReg(config->ucpd_port, IMR); if (enable) { - LL_UCPD_WriteReg(config->ucpd_port, ICR, UCPD_ICR_TX_INT_MASK); - LL_UCPD_WriteReg(config->ucpd_port, IMR, - imr | UCPD_IMR_TX_INT_MASK); + stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_TX_INT_MASK); + stm32_reg_write(&config->ucpd_port->IMR, imr | UCPD_IMR_TX_INT_MASK); } else { - LL_UCPD_WriteReg(config->ucpd_port, IMR, - imr & ~UCPD_IMR_TX_INT_MASK); + stm32_reg_write(&config->ucpd_port->IMR, imr & ~UCPD_IMR_TX_INT_MASK); } } @@ -281,7 +279,7 @@ static int ucpd_set_vconn(const struct device *dev, bool enable) cr |= ucpd_get_cc_enable_mask(dev); /* Apply cc pull resistor change */ - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); #ifdef CONFIG_SOC_SERIES_STM32G0X update_stm32g0x_cc_line(config->ucpd_port); @@ -380,7 +378,7 @@ static void dead_battery(const struct device *dev, bool en) cr &= ~UCPD_CR_DBATTEN; } - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); update_stm32g0x_cc_line(config->ucpd_port); #else if (en) { @@ -432,7 +430,7 @@ static int ucpd_set_cc(const struct device *dev, } /* Update pull values */ - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); #ifdef CONFIG_SOC_SERIES_STM32G0X update_stm32g0x_cc_line(config->ucpd_port); @@ -473,7 +471,7 @@ static int ucpd_cc_set_polarity(const struct device *dev, } /* Update polarity */ - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); return 0; } @@ -499,16 +497,16 @@ static int ucpd_set_rx_enable(const struct device *dev, bool enable) */ if (enable) { /* Clear the RX alerts bits */ - LL_UCPD_WriteReg(config->ucpd_port, ICR, UCPD_ICR_RX_INT_MASK); + stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_RX_INT_MASK); imr |= UCPD_IMR_RX_INT_MASK; cr |= UCPD_CR_PHYRXEN; - LL_UCPD_WriteReg(config->ucpd_port, IMR, imr); - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->IMR, imr); + stm32_reg_write(&config->ucpd_port->CR, cr); } else { imr &= ~UCPD_IMR_RX_INT_MASK; cr &= ~UCPD_CR_PHYRXEN; - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); - LL_UCPD_WriteReg(config->ucpd_port, IMR, imr); + stm32_reg_write(&config->ucpd_port->CR, cr); + stm32_reg_write(&config->ucpd_port->IMR, imr); } return 0; @@ -585,16 +583,15 @@ static void ucpd_start_transmit(const struct device *dev, * register to initiate. */ /* Enable interrupt for Hard Reset sent/discarded */ - LL_UCPD_WriteReg(config->ucpd_port, ICR, - UCPD_ICR_HRSTDISCCF | UCPD_ICR_HRSTSENTCF); + stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_HRSTDISCCF | UCPD_ICR_HRSTSENTCF); imr = LL_UCPD_ReadReg(config->ucpd_port, IMR); imr |= UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; - LL_UCPD_WriteReg(config->ucpd_port, IMR, imr); + stm32_reg_write(&config->ucpd_port->IMR, imr); /* Initiate Hard Reset */ cr |= UCPD_CR_TXHRST; - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); } else if (type != PD_PACKET_MSG_INVALID) { int msg_len = 0; int mode; @@ -633,7 +630,7 @@ static void ucpd_start_transmit(const struct device *dev, /* Set tx mode */ cr &= ~UCPD_CR_TXMODE_Msk; cr |= mode; - LL_UCPD_WriteReg(config->ucpd_port, CR, cr); + stm32_reg_write(&config->ucpd_port->CR, cr); /* Index into ordset enum for start of packet */ if (type <= PD_PACKET_CABLE_RESET) { @@ -1241,7 +1238,7 @@ static void ucpd_isr(const struct device *dev_inst[]) } /* Clear interrupts now that PD events have been set */ - LL_UCPD_WriteReg(config->ucpd_port, ICR, sr & UCPD_ICR_ALL_INT_MASK); + stm32_reg_write(&config->ucpd_port->ICR, sr & UCPD_ICR_ALL_INT_MASK); /* Notify application of events */ k_work_submit(&info->work); @@ -1326,7 +1323,7 @@ static void ucpd_isr_init(const struct device *dev) k_timer_init(&data->goodcrc_rx_timer, NULL, NULL); /* Disable all alert bits */ - LL_UCPD_WriteReg(config->ucpd_port, IMR, 0); + stm32_reg_write(&config->ucpd_port->IMR, 0); /* Clear all alert handler */ ucpd_set_alert_handler_cb(dev, NULL, NULL); @@ -1338,10 +1335,8 @@ static void ucpd_isr_init(const struct device *dev) k_work_init(&info->work, ucpd_alert_handler); /* Configure CC change alerts */ - LL_UCPD_WriteReg(config->ucpd_port, IMR, - UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE); - LL_UCPD_WriteReg(config->ucpd_port, ICR, - UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF); + stm32_reg_write(&config->ucpd_port->IMR, UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE); + stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF); /* SOP'/SOP'' must be enabled via TCPCI call */ data->ucpd_rx_sop_prime_enabled = false; @@ -1394,7 +1389,7 @@ static int ucpd_init(const struct device *dev) cfg1 = LL_UCPD_ReadReg(config->ucpd_port, CFG1); cfg1 |= LL_UCPD_ORDERSET_SOP | LL_UCPD_ORDERSET_SOP1 | LL_UCPD_ORDERSET_SOP2 | LL_UCPD_ORDERSET_HARDRST; - LL_UCPD_WriteReg(config->ucpd_port, CFG1, cfg1); + stm32_reg_write(&config->ucpd_port->CFG1, cfg1); /* Enable UCPD port */ LL_UCPD_Enable(config->ucpd_port); diff --git a/drivers/video/video_stm32_dcmipp.c b/drivers/video/video_stm32_dcmipp.c index e7ffa2c023586..ab12ab1b1c306 100644 --- a/drivers/video/video_stm32_dcmipp.c +++ b/drivers/video/video_stm32_dcmipp.c @@ -162,13 +162,13 @@ static void stm32_dcmipp_set_next_buffer_addr(struct stm32_dcmipp_pipe_data *pip /* TODO - the HAL is missing a SetMemoryAddress for auxiliary addresses */ /* Update main buffer address */ if (pipe->id == DCMIPP_PIPE0) { - WRITE_REG(dcmipp->hdcmipp.Instance->P0PPM0AR1, (uint32_t)plane); + stm32_reg_write(&dcmipp->hdcmipp.Instance->P0PPM0AR1, (uint32_t)plane); } #if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) else if (pipe->id == DCMIPP_PIPE1) { - WRITE_REG(dcmipp->hdcmipp.Instance->P1PPM0AR1, (uint32_t)plane); + stm32_reg_write(&dcmipp->hdcmipp.Instance->P1PPM0AR1, (uint32_t)plane); } else { - WRITE_REG(dcmipp->hdcmipp.Instance->P2PPM0AR1, (uint32_t)plane); + stm32_reg_write(&dcmipp->hdcmipp.Instance->P2PPM0AR1, (uint32_t)plane); } if (pipe->id != DCMIPP_PIPE1) { @@ -179,13 +179,13 @@ static void stm32_dcmipp_set_next_buffer_addr(struct stm32_dcmipp_pipe_data *pip /* Y plane has 8 bit per pixel, next plane is located at off + width * height */ plane += VIDEO_FMT_PLANAR_Y_PLANE_SIZE(fmt); - WRITE_REG(dcmipp->hdcmipp.Instance->P1PPM1AR1, (uint32_t)plane); + stm32_reg_write(&dcmipp->hdcmipp.Instance->P1PPM1AR1, (uint32_t)plane); if (VIDEO_FMT_IS_PLANAR(fmt)) { /* In case of YUV420 / YVU420, U plane has half width / half height */ plane += VIDEO_FMT_PLANAR_Y_PLANE_SIZE(fmt) / 4; - WRITE_REG(dcmipp->hdcmipp.Instance->P1PPM2AR1, (uint32_t)plane); + stm32_reg_write(&dcmipp->hdcmipp.Instance->P1PPM2AR1, (uint32_t)plane); } } #endif From b410706df9232cae9b689fc7394f36303a5fcf6a Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 10:28:23 +0200 Subject: [PATCH 6/9] drivers: stm32: replace READ_REG HAL macro by stm32_reg_read For all STM32 drivers and SoC, replace the READ_REG macro and the LL_xxx_ReadReg functions (defined in the STM32 HAL) by stm32_reg_read defined in Zephyr. Signed-off-by: Guillaume Gautier --- drivers/gpio/gpio_stm32.c | 2 +- drivers/hwinfo/hwinfo_stm32.c | 5 ++- drivers/i2c/i2c_ll_stm32_v1.c | 16 +++---- drivers/i2c/i2c_ll_stm32_v1_rtio.c | 2 +- drivers/i2c/i2c_ll_stm32_v2.c | 10 ++--- drivers/rtc/rtc_ll_stm32.c | 2 +- .../st/stm32_digi_temp/stm32_digi_temp.c | 2 +- drivers/serial/uart_stm32.c | 10 ++--- drivers/spi/spi_ll_stm32.c | 3 +- drivers/usb_c/tcpc/ucpd_stm32.c | 44 +++++++++---------- 10 files changed, 47 insertions(+), 49 deletions(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index e828049618a78..fe12d9ea8f7b0 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -444,7 +444,7 @@ static int gpio_stm32_port_toggle_bits(const struct device *dev, * Skip it and use CMSIS API directly. Valid also on other series. */ z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); - stm32_reg_write(&gpio->ODR, READ_REG(gpio->ODR) ^ pins); + stm32_reg_write(&gpio->ODR, stm32_reg_read(&gpio->ODR) ^ pins); z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); return 0; diff --git a/drivers/hwinfo/hwinfo_stm32.c b/drivers/hwinfo/hwinfo_stm32.c index c29bb3a36da73..b224107ec72ae 100644 --- a/drivers/hwinfo/hwinfo_stm32.c +++ b/drivers/hwinfo/hwinfo_stm32.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #if defined(CONFIG_SOC_SERIES_STM32H5X) @@ -77,8 +78,8 @@ int z_impl_hwinfo_get_device_eui64(uint8_t *buffer) { struct stm32_eui64 dev_eui64; - dev_eui64.id[0] = sys_cpu_to_be32(READ_REG(*((uint32_t *)UID64_BASE + 1U))); - dev_eui64.id[1] = sys_cpu_to_be32(READ_REG(*((uint32_t *)UID64_BASE))); + dev_eui64.id[0] = sys_cpu_to_be32(sys_read32(UID64_BASE + sizeof(uint32_t))); + dev_eui64.id[1] = sys_cpu_to_be32(sys_read32(UID64_BASE)); memcpy(buffer, dev_eui64.id, sizeof(dev_eui64)); diff --git a/drivers/i2c/i2c_ll_stm32_v1.c b/drivers/i2c/i2c_ll_stm32_v1.c index 953ba797b3814..00bdeb01189f2 100644 --- a/drivers/i2c/i2c_ll_stm32_v1.c +++ b/drivers/i2c/i2c_ll_stm32_v1.c @@ -32,7 +32,7 @@ LOG_MODULE_REGISTER(i2c_ll_stm32_v1); static void i2c_stm32_generate_start_condition(I2C_TypeDef *i2c) { - uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1); + uint16_t cr1 = stm32_reg_read(&i2c->CR1); if (cr1 & I2C_CR1_STOP) { LOG_DBG("%s: START while STOP active!", __func__); @@ -88,14 +88,14 @@ static void i2c_stm32_reset(const struct device *dev) #endif /* save all important registers before reset */ - cr1 = LL_I2C_ReadReg(i2c, CR1); - cr2 = LL_I2C_ReadReg(i2c, CR2); - oar1 = LL_I2C_ReadReg(i2c, OAR1); - oar2 = LL_I2C_ReadReg(i2c, OAR2); - ccr = LL_I2C_ReadReg(i2c, CCR); - trise = LL_I2C_ReadReg(i2c, TRISE); + cr1 = stm32_reg_read(&i2c->CR1); + cr2 = stm32_reg_read(&i2c->CR2); + oar1 = stm32_reg_read(&i2c->OAR1); + oar2 = stm32_reg_read(&i2c->OAR2); + ccr = stm32_reg_read(&i2c->CCR); + trise = stm32_reg_read(&i2c->TRISE); #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF) - fltr = LL_I2C_ReadReg(i2c, FLTR); + fltr = stm32_reg_read(&i2c->FLTR); #endif /* reset i2c hardware */ diff --git a/drivers/i2c/i2c_ll_stm32_v1_rtio.c b/drivers/i2c/i2c_ll_stm32_v1_rtio.c index 5ebcfa2eeea99..b181906e15a99 100644 --- a/drivers/i2c/i2c_ll_stm32_v1_rtio.c +++ b/drivers/i2c/i2c_ll_stm32_v1_rtio.c @@ -54,7 +54,7 @@ static void i2c_stm32_enable_transfer_interrupts(const struct device *dev) static void i2c_stm32_generate_start_condition(I2C_TypeDef *i2c) { - uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1); + uint16_t cr1 = stm32_reg_read(&i2c->CR1); if ((cr1 & I2C_CR1_STOP) != 0) { LOG_DBG("%s: START while STOP active!", __func__); diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 5ac39b5bcf830..24a3cf0493928 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -481,7 +481,7 @@ void i2c_stm32_event(const struct device *dev) const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; I2C_TypeDef *regs = cfg->i2c; - uint32_t isr = LL_I2C_ReadReg(regs, ISR); + uint32_t isr = stm32_reg_read(®s->ISR); #if defined(CONFIG_I2C_TARGET) if (data->slave_attached && !data->master_active) { @@ -515,7 +515,7 @@ void i2c_stm32_event(const struct device *dev) /* Transfer complete with reload flag set means more data shall be transferred * in same direction (No RESTART or STOP) */ - uint32_t cr2 = LL_I2C_ReadReg(regs, CR2); + uint32_t cr2 = stm32_reg_read(®s->CR2); #ifdef CONFIG_I2C_STM32_V2_DMA /* Get number of bytes bytes transferred by DMA */ uint32_t xfer_len = (cr2 & I2C_CR2_NBYTES_Msk) >> I2C_CR2_NBYTES_Pos; @@ -724,8 +724,8 @@ static int stm32_i2c_irq_xfer(const struct device *dev, struct i2c_msg *msg, /* Enable I2C peripheral if not already done */ LL_I2C_Enable(regs); - uint32_t cr2 = LL_I2C_ReadReg(regs, CR2); - uint32_t isr = LL_I2C_ReadReg(regs, ISR); + uint32_t cr2 = stm32_reg_read(®s->CR2); + uint32_t isr = stm32_reg_read(®s->ISR); /* Clear fields in CR2 which will be filled in later in function */ cr2 &= ~(I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_NBYTES_Msk | I2C_CR2_SADD_Msk | @@ -815,7 +815,7 @@ static int stm32_i2c_irq_xfer(const struct device *dev, struct i2c_msg *msg, /* Commit configuration to I2C controller and start transfer */ stm32_reg_write(®s->CR2, cr2); - cr1 |= LL_I2C_ReadReg(regs, CR1); + cr1 |= stm32_reg_read(®s->CR1); /* Enable interrupts */ stm32_reg_write(®s->CR1, cr1); diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c index 5c05d6f32f887..b326cffc48dab 100644 --- a/drivers/rtc/rtc_ll_stm32.c +++ b/drivers/rtc/rtc_ll_stm32.c @@ -1068,7 +1068,7 @@ static int rtc_stm32_get_calibration(const struct device *dev, int32_t *calibrat { ARG_UNUSED(dev); - uint32_t calr = sys_read32((mem_addr_t) &RTC->CALR); + uint32_t calr = stm32_reg_read(&RTC->CALR); bool calp_enabled = stm32_reg_read_bits(&calr, RTC_CALR_CALP) == RTC_CALR_CALP; uint32_t calm = stm32_reg_read_bits(&calr, RTC_CALR_CALM); diff --git a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c index 37f421aebc474..1d80d8bb74ab3 100644 --- a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c +++ b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c @@ -86,7 +86,7 @@ static int stm32_digi_temp_sample_fetch(const struct device *dev, enum sensor_ch k_sem_take(&data->sem_isr, K_FOREVER); /* Read value */ - data->raw = READ_REG(dts->DR); + data->raw = stm32_reg_read(&dts->DR); k_mutex_unlock(&data->mutex); diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index b5cf9987b60bc..f97ffada55f14 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -239,12 +240,10 @@ static inline int uart_stm32_set_baudrate(const struct device *dev, uint32_t bau #endif baud_rate); /* Check BRR is greater than or equal to 0x300 */ - __ASSERT(LL_LPUART_ReadReg(usart, BRR) >= 0x300U, - "BaudRateReg >= 0x300"); + __ASSERT(stm32_reg_read(&usart->BRR) >= 0x300U, "BaudRateReg >= 0x300"); /* Check BRR is lower than or equal to 0xFFFFF */ - __ASSERT(LL_LPUART_ReadReg(usart, BRR) < 0x000FFFFFU, - "BaudRateReg < 0xFFFF"); + __ASSERT(stm32_reg_read(&usart->BRR) < 0x000FFFFFU, "BaudRateReg < 0xFFFF"); } else { #endif /* HAS_LPUART */ #ifdef USART_CR1_OVER8 @@ -272,8 +271,7 @@ static inline int uart_stm32_set_baudrate(const struct device *dev, uint32_t bau #endif baud_rate); /* Check BRR is greater than or equal to 16d */ - __ASSERT(LL_USART_ReadReg(usart, BRR) >= 16, - "BaudRateReg >= 16"); + __ASSERT(stm32_reg_read(&usart->BRR) >= 16, "BaudRateReg >= 16"); #if HAS_LPUART } diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c index ce192cfdc94f9..b5919d1ae0ff0 100644 --- a/drivers/spi/spi_ll_stm32.c +++ b/drivers/spi/spi_ll_stm32.c @@ -30,6 +30,7 @@ LOG_MODULE_REGISTER(spi_ll_stm32); #include #include +#include #include #include @@ -347,7 +348,7 @@ static bool spi_stm32_transfer_ongoing(struct spi_stm32_data *data) static int spi_stm32_get_err(SPI_TypeDef *spi) { - uint32_t sr = LL_SPI_ReadReg(spi, SR); + uint32_t sr = stm32_reg_read(&spi->SR); if ((sr & SPI_STM32_ERR_MSK) != 0U) { LOG_ERR("%s: err=%d", __func__, diff --git a/drivers/usb_c/tcpc/ucpd_stm32.c b/drivers/usb_c/tcpc/ucpd_stm32.c index 863c6cc3c1c12..a598117ee36d8 100644 --- a/drivers/usb_c/tcpc/ucpd_stm32.c +++ b/drivers/usb_c/tcpc/ucpd_stm32.c @@ -112,7 +112,7 @@ static void ucpd_tx_interrupts_enable(const struct device *dev, bool enable) const struct tcpc_config *const config = dev->config; uint32_t imr; - imr = LL_UCPD_ReadReg(config->ucpd_port, IMR); + imr = stm32_reg_read(&config->ucpd_port->IMR); if (enable) { stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_TX_INT_MASK); @@ -160,7 +160,7 @@ static uint32_t ucpd_get_cc_enable_mask(const struct device *dev) * not being used for Power Delivery messages. */ if (data->ucpd_vconn_enable) { - uint32_t cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + uint32_t cr = stm32_reg_read(&config->ucpd_port->CR); int pol = (cr & UCPD_CR_PHYCCSEL); /* Dissable CC line that's used for VCONN */ @@ -206,7 +206,7 @@ static int ucpd_get_cc(const struct device *dev, */ /* Get vstate_ccx values and power role */ - sr = LL_UCPD_ReadReg(config->ucpd_port, SR); + sr = stm32_reg_read(&config->ucpd_port->SR); /* Get Rp or Rd active */ anamode = LL_UCPD_GetRole(config->ucpd_port); @@ -274,7 +274,7 @@ static int ucpd_set_vconn(const struct device *dev, bool enable) /* Update VCONN on/off status. Do this before getting cc enable mask */ data->ucpd_vconn_enable = enable; - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + cr = stm32_reg_read(&config->ucpd_port->CR); cr &= ~UCPD_CR_CCENABLE_Msk; cr |= ucpd_get_cc_enable_mask(dev); @@ -370,7 +370,7 @@ static void dead_battery(const struct device *dev, bool en) const struct tcpc_config *const config = dev->config; uint32_t cr; - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + cr = stm32_reg_read(&config->ucpd_port->CR); if (en) { cr |= UCPD_CR_DBATTEN; @@ -408,7 +408,7 @@ static int ucpd_set_cc(const struct device *dev, dead_battery(dev, false); } - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + cr = stm32_reg_read(&config->ucpd_port->CR); /* * Always set ANASUBMODE to match desired Rp. TCPM layer has a valid @@ -453,7 +453,7 @@ static int ucpd_cc_set_polarity(const struct device *dev, const struct tcpc_config *const config = dev->config; uint32_t cr; - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + cr = stm32_reg_read(&config->ucpd_port->CR); /* * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This @@ -488,8 +488,8 @@ static int ucpd_set_rx_enable(const struct device *dev, bool enable) uint32_t imr; uint32_t cr; - imr = LL_UCPD_ReadReg(config->ucpd_port, IMR); - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + imr = stm32_reg_read(&config->ucpd_port->IMR); + cr = stm32_reg_read(&config->ucpd_port->CR); /* * USB PD receiver enable is controlled by the bit PHYRXEN in @@ -558,7 +558,7 @@ static void ucpd_start_transmit(const struct device *dev, uint32_t cr; uint32_t imr; - cr = LL_UCPD_ReadReg(config->ucpd_port, CR); + cr = stm32_reg_read(&config->ucpd_port->CR); /* Select the correct tx descriptor */ data->ucpd_tx_active_buffer = &data->ucpd_tx_buffers[msg_type]; @@ -585,7 +585,7 @@ static void ucpd_start_transmit(const struct device *dev, /* Enable interrupt for Hard Reset sent/discarded */ stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_HRSTDISCCF | UCPD_ICR_HRSTSENTCF); - imr = LL_UCPD_ReadReg(config->ucpd_port, IMR); + imr = stm32_reg_read(&config->ucpd_port->IMR); imr |= UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; stm32_reg_write(&config->ucpd_port->IMR, imr); @@ -1106,10 +1106,8 @@ static void ucpd_isr(const struct device *dev_inst[]) /* Read UCPD1 and UCPD2 Status Registers */ - sr0 = - LL_UCPD_ReadReg(((const struct tcpc_config *)dev_inst[0]->config)->ucpd_port, SR); - sr1 = - LL_UCPD_ReadReg(((const struct tcpc_config *)dev_inst[1]->config)->ucpd_port, SR); + sr0 = stm32_reg_read(&((const struct tcpc_config *)dev_inst[0]->config)->ucpd_port->SR); + sr1 = stm32_reg_read(&((const struct tcpc_config *)dev_inst[1]->config)->ucpd_port->SR); if (sr0) { dev = dev_inst[0]; @@ -1135,7 +1133,7 @@ static void ucpd_isr(const struct device *dev_inst[]) info = &data->alert_info; /* Read the status register */ - sr = LL_UCPD_ReadReg(config->ucpd_port, SR); + sr = stm32_reg_read(&config->ucpd_port->SR); /* Check for CC events, set event to wake PD task */ if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { @@ -1254,12 +1252,12 @@ static int ucpd_dump_std_reg(const struct device *dev) { const struct tcpc_config *const config = dev->config; - LOG_INF("CFGR1: %08x", LL_UCPD_ReadReg(config->ucpd_port, CFG1)); - LOG_INF("CFGR2: %08x", LL_UCPD_ReadReg(config->ucpd_port, CFG2)); - LOG_INF("CR: %08x", LL_UCPD_ReadReg(config->ucpd_port, CR)); - LOG_INF("IMR: %08x", LL_UCPD_ReadReg(config->ucpd_port, IMR)); - LOG_INF("SR: %08x", LL_UCPD_ReadReg(config->ucpd_port, SR)); - LOG_INF("ICR: %08x\n", LL_UCPD_ReadReg(config->ucpd_port, ICR)); + LOG_INF("CFGR1: %08x", stm32_reg_read(&config->ucpd_port->CFG1)); + LOG_INF("CFGR2: %08x", stm32_reg_read(&config->ucpd_port->CFG2)); + LOG_INF("CR: %08x", stm32_reg_read(&config->ucpd_port->CR)); + LOG_INF("IMR: %08x", stm32_reg_read(&config->ucpd_port->IMR)); + LOG_INF("SR: %08x", stm32_reg_read(&config->ucpd_port->SR)); + LOG_INF("ICR: %08x\n", stm32_reg_read(&config->ucpd_port->ICR)); return 0; } @@ -1386,7 +1384,7 @@ static int ucpd_init(const struct device *dev) * Set RXORDSETEN field to control which types of ordered sets the PD * receiver must receive. */ - cfg1 = LL_UCPD_ReadReg(config->ucpd_port, CFG1); + cfg1 = stm32_reg_read(&config->ucpd_port->CFG1); cfg1 |= LL_UCPD_ORDERSET_SOP | LL_UCPD_ORDERSET_SOP1 | LL_UCPD_ORDERSET_SOP2 | LL_UCPD_ORDERSET_HARDRST; stm32_reg_write(&config->ucpd_port->CFG1, cfg1); From 5a5a89af2351a0c8bf1bd0d22a6348e17eab4466 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Tue, 21 Oct 2025 10:34:13 +0200 Subject: [PATCH 7/9] drivers: stm32: replace MODIFY_REG HAL macro by stm32_reg_modify_bits For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr. Signed-off-by: Guillaume Gautier --- drivers/adc/adc_stm32.c | 12 ++++++------ drivers/adc/adc_stm32wb0.c | 5 +++-- drivers/clock_control/clock_stm32_ll_common.c | 5 +++-- drivers/clock_control/clock_stm32f2_f4_f7.c | 3 ++- drivers/entropy/entropy_stm32.c | 2 +- drivers/flash/flash_stm32_qspi.c | 5 +++-- drivers/memc/memc_stm32.c | 5 +++-- drivers/memc/memc_stm32_xspi_psram.c | 4 +++- drivers/rtc/rtc_ll_stm32.c | 2 +- drivers/sdhc/sdhc_stm32.c | 4 +++- .../sensor/st/stm32_digi_temp/stm32_digi_temp.c | 16 ++++++++-------- soc/st/stm32/stm32h7x/soc_m7.c | 3 ++- soc/st/stm32/stm32wbax/power.c | 10 ++++++---- 13 files changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 402e81fa426e5..5dceb6e2b75af 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -566,9 +566,10 @@ static void adc_stm32_calibration_start(const struct device *dev, bool single_en */ if ((dev_id != 0x482UL) && (rev_id != 0x2001UL)) { adc_stm32_enable(adc); - MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos); + stm32_reg_modify_bits(&adc->CR, ADC_CR_CALINDEX, + 0x9UL << ADC_CR_CALINDEX_Pos); __DMB(); - MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); + stm32_reg_modify_bits(&adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); __DMB(); stm32_reg_set_bits(&adc->CALFACT, ADC_CALFACT_LATCH_COEF); adc_stm32_disable(adc); @@ -866,11 +867,10 @@ static void set_reg_value(const struct device *dev, uint32_t reg, uint32_t shift, uint32_t mask, uint32_t value) { const struct adc_stm32_cfg *config = dev->config; - ADC_TypeDef *adc = config->base; - - uintptr_t addr = (uintptr_t)adc + reg; + size_t reg32_offset = reg / sizeof(uint32_t); + volatile uint32_t *addr = (volatile uint32_t *)config->base + reg32_offset; - MODIFY_REG(*(volatile uint32_t *)addr, (mask << shift), (value << shift)); + stm32_reg_modify_bits(addr, mask << shift, value << shift); } static int set_resolution(const struct device *dev, diff --git a/drivers/adc/adc_stm32wb0.c b/drivers/adc/adc_stm32wb0.c index d572f9fbcd6fa..02d65e1c7ab5b 100644 --- a/drivers/adc/adc_stm32wb0.c +++ b/drivers/adc/adc_stm32wb0.c @@ -46,6 +46,7 @@ #include #include +#include #include #include @@ -304,7 +305,7 @@ static inline void ll_adc_set_conversion_channel(ADC_TypeDef *ADCx, const uint32_t reg = (Conversion & 8) ? 1 : 0; const uint32_t shift = 4 * (Conversion & 7); - MODIFY_REG((&ADCx->SEQ_1)[reg], ADC_SEQ_1_SEQ0 << shift, Channel << shift); + stm32_reg_modify_bits((&ADCx->SEQ_1) + reg, ADC_SEQ_1_SEQ0 << shift, Channel << shift); } /** @@ -379,7 +380,7 @@ static inline void ll_adc_set_calib_point_for_any(ADC_TypeDef *ADCx, uint32_t Ty const uint32_t shift = (group_shift + type_shift); - MODIFY_REG(ADCx->COMP_SEL, (ADC_COMP_SEL_OFFSET_GAIN0 << shift), (Point << shift)); + stm32_reg_modify_bits(&ADCx->COMP_SEL, ADC_COMP_SEL_OFFSET_GAIN0 << shift, Point << shift); } static void adc_acquire_pm_locks(void) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 15a72bf400e46..268120f6dcf72 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -820,11 +821,11 @@ static void set_up_plls(void) #if defined(STM32_PLL_ENABLED) #if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR)); + stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR)); RCC_PLLP_ENABLE(); #endif #if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR)); + stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR)); RCC_PLLQ_ENABLE(); #endif diff --git a/drivers/clock_control/clock_stm32f2_f4_f7.c b/drivers/clock_control/clock_stm32f2_f4_f7.c index feb850b0e8731..a7be342a5d9ac 100644 --- a/drivers/clock_control/clock_stm32f2_f4_f7.c +++ b/drivers/clock_control/clock_stm32f2_f4_f7.c @@ -7,6 +7,7 @@ #include +#include #include #include #include @@ -97,7 +98,7 @@ __unused void config_pll_sysclock(void) { #if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR) - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); + stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); #endif LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(), pllm(STM32_PLL_M_DIVISOR), diff --git a/drivers/entropy/entropy_stm32.c b/drivers/entropy/entropy_stm32.c index c8698a87deb5c..75a759efa84ce 100644 --- a/drivers/entropy/entropy_stm32.c +++ b/drivers/entropy/entropy_stm32.c @@ -225,7 +225,7 @@ static void configure_rng(void) #endif /* health_test_config */ if (cur_nist_cfg != desired_nist_cfg || cur_htcr != desired_htcr) { - MODIFY_REG(rng->CR, cur_nist_cfg, (desired_nist_cfg | RNG_CR_CONDRST)); + stm32_reg_modify_bits(&rng->CR, cur_nist_cfg, desired_nist_cfg | RNG_CR_CONDRST); #if DT_INST_NODE_HAS_PROP(0, health_test_config) #if DT_INST_NODE_HAS_PROP(0, health_test_magic) diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c index 30ee0831553d4..e853d91d9a71e 100644 --- a/drivers/flash/flash_stm32_qspi.c +++ b/drivers/flash/flash_stm32_qspi.c @@ -486,7 +486,8 @@ static int qspi_read_sfdp(const struct device *dev, off_t addr, void *data, * flash mode is disabled during the reading to obtain the SFDP from a single flash memory * only. */ - MODIFY_REG(dev_data->hqspi.Instance->CR, QUADSPI_CR_DFM, QSPI_DUALFLASH_DISABLE); + stm32_reg_modify_bits(&dev_data->hqspi.Instance->CR, QUADSPI_CR_DFM, + QSPI_DUALFLASH_DISABLE); LOG_DBG("Dual flash mode disabled while reading SFDP"); #endif /* STM32_QSPI_DOUBLE_FLASH */ @@ -522,7 +523,7 @@ static int qspi_read_sfdp(const struct device *dev, off_t addr, void *data, end: #if STM32_QSPI_DOUBLE_FLASH /* Re-enable the dual flash mode */ - MODIFY_REG(dev_data->hqspi.Instance->CR, QUADSPI_CR_DFM, QSPI_DUALFLASH_ENABLE); + stm32_reg_modify_bits(&dev_data->hqspi.Instance->CR, QUADSPI_CR_DFM, QSPI_DUALFLASH_ENABLE); #endif /* dual_flash */ return ret; diff --git a/drivers/memc/memc_stm32.c b/drivers/memc/memc_stm32.c index e25766f2791bc..d9ebf53be46f9 100644 --- a/drivers/memc/memc_stm32.c +++ b/drivers/memc/memc_stm32.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -77,10 +78,10 @@ static int memc_stm32_init(const struct device *dev) #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_fmc) #if (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 1) /* sdram-sram */ - MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_0); + stm32_reg_modify_bits(&FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_0); #elif (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 2) /* sdramb2 */ - MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_1); + stm32_reg_modify_bits(&FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_1); #endif #endif diff --git a/drivers/memc/memc_stm32_xspi_psram.c b/drivers/memc/memc_stm32_xspi_psram.c index e7c62e9eeb36a..df016fac2f79e 100644 --- a/drivers/memc/memc_stm32_xspi_psram.c +++ b/drivers/memc/memc_stm32_xspi_psram.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -354,7 +355,8 @@ static int memc_stm32_xspi_psram_init(const struct device *dev) } #if defined(XSPI_CR_NOPREF) - MODIFY_REG(hxspi.Instance->CR, XSPI_CR_NOPREF, HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE); + stm32_reg_modify_bits(&hxspi.Instance->CR, XSPI_CR_NOPREF, + HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE); #endif #ifdef CONFIG_SHARED_MULTI_HEAP diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c index b326cffc48dab..62f0f5a32a9a7 100644 --- a/drivers/rtc/rtc_ll_stm32.c +++ b/drivers/rtc/rtc_ll_stm32.c @@ -1055,7 +1055,7 @@ static int rtc_stm32_set_calibration(const struct device *dev, int32_t calibrati LL_RTC_DisableWriteProtection(RTC); - MODIFY_REG(RTC->CALR, RTC_CALR_CALP | RTC_CALR_CALM, calp | calm); + stm32_reg_modify_bits(&RTC->CALR, RTC_CALR_CALP | RTC_CALR_CALM, calp | calm); LL_RTC_EnableWriteProtection(RTC); diff --git a/drivers/sdhc/sdhc_stm32.c b/drivers/sdhc/sdhc_stm32.c index 1011066c13756..33374af975278 100644 --- a/drivers/sdhc/sdhc_stm32.c +++ b/drivers/sdhc/sdhc_stm32.c @@ -6,6 +6,7 @@ #define DT_DRV_COMPAT st_stm32_sdio +#include #include #include #include @@ -517,7 +518,8 @@ static int sdhc_stm32_set_io(const struct device *dev, struct sdhc_io *ios) bus_width_reg_value = SDMMC_BUS_WIDE_1B; } - MODIFY_REG(config->hsd->Instance->CLKCR, SDMMC_CLKCR_WIDBUS, bus_width_reg_value); + stm32_reg_modify_bits(&config->hsd->Instance->CLKCR, SDMMC_CLKCR_WIDBUS, + bus_width_reg_value); host_io->bus_width = ios->bus_width; } diff --git a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c index 1d80d8bb74ab3..c45eae0016794 100644 --- a/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c +++ b/drivers/sensor/st/stm32_digi_temp/stm32_digi_temp.c @@ -120,20 +120,20 @@ static void stm32_digi_temp_configure(const struct device *dev) * Allowed values are between 0 and 127. */ clk_div = MIN(DIV_ROUND_UP(data->pclk_freq, ONE_MHZ), 127); - MODIFY_REG(dts->CFGR1, DTS_CFGR1_HSREF_CLK_DIV_Msk, - clk_div << DTS_CFGR1_HSREF_CLK_DIV_Pos); + stm32_reg_modify_bits(&dts->CFGR1, DTS_CFGR1_HSREF_CLK_DIV_Msk, + clk_div << DTS_CFGR1_HSREF_CLK_DIV_Pos); /* Select PCLK as reference clock */ - MODIFY_REG(dts->CFGR1, DTS_CFGR1_REFCLK_SEL_Msk, - 0 << DTS_CFGR1_REFCLK_SEL_Pos); + stm32_reg_modify_bits(&dts->CFGR1, DTS_CFGR1_REFCLK_SEL_Msk, + 0 << DTS_CFGR1_REFCLK_SEL_Pos); /* Select trigger */ - MODIFY_REG(dts->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL_Msk, - 0 << DTS_CFGR1_TS1_INTRIG_SEL_Pos); + stm32_reg_modify_bits(&dts->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL_Msk, + 0 << DTS_CFGR1_TS1_INTRIG_SEL_Pos); /* Set sampling time */ - MODIFY_REG(dts->CFGR1, DTS_CFGR1_TS1_SMP_TIME_Msk, - SAMPLING_TIME << DTS_CFGR1_TS1_SMP_TIME_Pos); + stm32_reg_modify_bits(&dts->CFGR1, DTS_CFGR1_TS1_SMP_TIME_Msk, + SAMPLING_TIME << DTS_CFGR1_TS1_SMP_TIME_Pos); } static void stm32_digi_temp_enable(const struct device *dev) diff --git a/soc/st/stm32/stm32h7x/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c index cf45837027f12..e479e74566335 100644 --- a/soc/st/stm32/stm32h7x/soc_m7.c +++ b/soc/st/stm32/stm32h7x/soc_m7.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -148,7 +149,7 @@ void soc_early_init_hook(void) * Applicable only to RevY (REV_ID 0x1003) */ if (LL_DBGMCU_GetRevisionID() == 0x1003) { - MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1); + stm32_reg_set_bits(&GPV->AXI_TARG7_FN_MOD, 0x1); } } diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c index 3ac7680bae6a2..417a2b5dd3c48 100644 --- a/soc/st/stm32/stm32wbax/power.c +++ b/soc/st/stm32/stm32wbax/power.c @@ -163,8 +163,8 @@ static void set_mode_stop_enter(uint8_t substate_id) } } ram_waitstates_backup = stm32_reg_read_bits(&RAMCFG_SRAM1->CR, RAMCFG_CR_WSC); - MODIFY_REG(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); - MODIFY_REG(RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); + stm32_reg_modify_bits(&RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); + stm32_reg_modify_bits(&RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); } switch (substate_id) { case 1: @@ -192,8 +192,10 @@ static void set_mode_stop_exit(uint8_t substate_id) __HAL_FLASH_SET_LATENCY(flash_latency_backup); while (__HAL_FLASH_GET_LATENCY() != flash_latency_backup) { } - MODIFY_REG(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, ram_waitstates_backup); - MODIFY_REG(RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, ram_waitstates_backup); + stm32_reg_modify_bits(&RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, + ram_waitstates_backup); + stm32_reg_modify_bits(&RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, + ram_waitstates_backup); } } From eb9ad57208795de82752665ae3fcb39b909bf73a Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Thu, 23 Oct 2025 11:39:39 +0200 Subject: [PATCH 8/9] drivers: i2c: stm32: v2: simplify reg operation Call stm32_reg_set_bits instead of stm32_reg_read then stm32_reg_write. Signed-off-by: Guillaume Gautier --- drivers/i2c/i2c_ll_stm32_v2.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 24a3cf0493928..55cf5ef0a2f6b 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -815,10 +815,8 @@ static int stm32_i2c_irq_xfer(const struct device *dev, struct i2c_msg *msg, /* Commit configuration to I2C controller and start transfer */ stm32_reg_write(®s->CR2, cr2); - cr1 |= stm32_reg_read(®s->CR1); - /* Enable interrupts */ - stm32_reg_write(®s->CR1, cr1); + stm32_reg_set_bits(®s->CR1, cr1); /* Wait for transfer to finish */ return stm32_i2c_irq_msg_finish(dev, msg); From b18ff3cded22dc8420191d14b1f426dddf501f7b Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Thu, 23 Oct 2025 13:19:37 +0200 Subject: [PATCH 9/9] drivers: usb_c: tcpc: stm32: use dedicated bitops functions Use dedicated set/clear bits function instead of reading/masking/writing manually. Signed-off-by: Guillaume Gautier --- drivers/usb_c/tcpc/ucpd_stm32.c | 34 ++++++++------------------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/drivers/usb_c/tcpc/ucpd_stm32.c b/drivers/usb_c/tcpc/ucpd_stm32.c index a598117ee36d8..ca69827f73511 100644 --- a/drivers/usb_c/tcpc/ucpd_stm32.c +++ b/drivers/usb_c/tcpc/ucpd_stm32.c @@ -485,11 +485,6 @@ static int ucpd_cc_set_polarity(const struct device *dev, static int ucpd_set_rx_enable(const struct device *dev, bool enable) { const struct tcpc_config *const config = dev->config; - uint32_t imr; - uint32_t cr; - - imr = stm32_reg_read(&config->ucpd_port->IMR); - cr = stm32_reg_read(&config->ucpd_port->CR); /* * USB PD receiver enable is controlled by the bit PHYRXEN in @@ -498,15 +493,11 @@ static int ucpd_set_rx_enable(const struct device *dev, bool enable) if (enable) { /* Clear the RX alerts bits */ stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_RX_INT_MASK); - imr |= UCPD_IMR_RX_INT_MASK; - cr |= UCPD_CR_PHYRXEN; - stm32_reg_write(&config->ucpd_port->IMR, imr); - stm32_reg_write(&config->ucpd_port->CR, cr); + stm32_reg_set_bits(&config->ucpd_port->IMR, UCPD_IMR_RX_INT_MASK); + stm32_reg_set_bits(&config->ucpd_port->CR, UCPD_CR_PHYRXEN); } else { - imr &= ~UCPD_IMR_RX_INT_MASK; - cr &= ~UCPD_CR_PHYRXEN; - stm32_reg_write(&config->ucpd_port->CR, cr); - stm32_reg_write(&config->ucpd_port->IMR, imr); + stm32_reg_clear_bits(&config->ucpd_port->IMR, UCPD_IMR_RX_INT_MASK); + stm32_reg_clear_bits(&config->ucpd_port->CR, UCPD_CR_PHYRXEN); } return 0; @@ -555,10 +546,6 @@ static void ucpd_start_transmit(const struct device *dev, struct tcpc_data *data = dev->data; const struct tcpc_config *const config = dev->config; enum pd_packet_type type; - uint32_t cr; - uint32_t imr; - - cr = stm32_reg_read(&config->ucpd_port->CR); /* Select the correct tx descriptor */ data->ucpd_tx_active_buffer = &data->ucpd_tx_buffers[msg_type]; @@ -585,13 +572,10 @@ static void ucpd_start_transmit(const struct device *dev, /* Enable interrupt for Hard Reset sent/discarded */ stm32_reg_write(&config->ucpd_port->ICR, UCPD_ICR_HRSTDISCCF | UCPD_ICR_HRSTSENTCF); - imr = stm32_reg_read(&config->ucpd_port->IMR); - imr |= UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; - stm32_reg_write(&config->ucpd_port->IMR, imr); - + stm32_reg_set_bits(&config->ucpd_port->IMR, + UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE); /* Initiate Hard Reset */ - cr |= UCPD_CR_TXHRST; - stm32_reg_write(&config->ucpd_port->CR, cr); + stm32_reg_set_bits(&config->ucpd_port->CR, UCPD_CR_TXHRST); } else if (type != PD_PACKET_MSG_INVALID) { int msg_len = 0; int mode; @@ -628,9 +612,7 @@ static void ucpd_start_transmit(const struct device *dev, LL_UCPD_WriteTxPaySize(config->ucpd_port, msg_len); /* Set tx mode */ - cr &= ~UCPD_CR_TXMODE_Msk; - cr |= mode; - stm32_reg_write(&config->ucpd_port->CR, cr); + stm32_reg_modify_bits(&config->ucpd_port->CR, UCPD_CR_TXMODE_Msk, mode); /* Index into ordset enum for start of packet */ if (type <= PD_PACKET_CABLE_RESET) {