diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c
index ebd01232c508e..805558cb54005 100644
--- a/drivers/pwm/pwm_stm32.c
+++ b/drivers/pwm/pwm_stm32.c
@@ -90,6 +90,7 @@ struct pwm_stm32_config {
 	TIM_TypeDef *timer;
 	uint32_t prescaler;
 	uint32_t countermode;
+	uint32_t mastermode;
 	const struct stm32_pclken *pclken;
 	size_t pclk_len;
 	const struct pinctrl_dev_config *pcfg;
@@ -699,6 +700,12 @@ static int pwm_stm32_init(const struct device *dev)
 	}
 #endif
 
+#ifdef IS_TIM_MASTER_INSTANCE
+	if (IS_TIM_MASTER_INSTANCE(timer)) {
+		LL_TIM_SetTriggerOutput(timer, cfg->mastermode);
+	}
+#endif /* IS_TIM_MASTER_INSTANCE*/
+
 #if !defined(CONFIG_SOC_SERIES_STM32L0X) && !defined(CONFIG_SOC_SERIES_STM32L1X)
 	/* enable outputs and counter */
 	if (IS_TIM_BREAK_INSTANCE(timer)) {
@@ -766,6 +773,7 @@ static void pwm_stm32_irq_config_func_##index(const struct device *dev)		\
 		.timer = (TIM_TypeDef *)DT_REG_ADDR(PWM(index)),	       \
 		.prescaler = DT_PROP(PWM(index), st_prescaler),		       \
 		.countermode = DT_PROP(PWM(index), st_countermode),	       \
+		.mastermode = DT_PROP(PWM(index), st_master_mode),	       \
 		.pclken = pclken_##index,				       \
 		.pclk_len = DT_NUM_CLOCKS(PWM(index)),			       \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),		       \
diff --git a/dts/bindings/timer/st,stm32-timers.yaml b/dts/bindings/timer/st,stm32-timers.yaml
index 135ed7eb63a0c..e58ade8029dd4 100644
--- a/dts/bindings/timer/st,stm32-timers.yaml
+++ b/dts/bindings/timer/st,stm32-timers.yaml
@@ -46,3 +46,32 @@ properties:
                                                down.
 
       If absent, then STM32_TIM_COUNTERMODE_UP is used (reset state).
+
+  st,master-mode:
+    type: int
+    default: 0
+    enum:
+      - 0    # STM32_TIM_MASTERMODE_RESET
+      - 0x10 # STM32_TIM_MASTERMODE_ENABLE
+      - 0x20 # STM32_TIM_MASTERMODE_UPDATE
+      - 0x30 # STM32_TIM_MASTERMODE_COMPARE_PULSE
+      - 0x40 # STM32_TIM_MASTERMODE_COMPARE_OC1REFC
+      - 0x50 # STM32_TIM_MASTERMODE_COMPARE_OC2REFC
+      - 0x60 # STM32_TIM_MASTERMODE_COMPARE_OC3REFC
+      - 0x70 # STM32_TIM_MASTERMODE_COMPARE_OC4REFC
+    description: |
+      Sets the master mode.
+      Only available for timer instances with master function.
+
+      For details refer to the reference manual of your device.
+
+      Use constants defined in dt-bindings/timer/stm32-timer.h.
+
+      * STM32_TIM_MASTERMODE_RESET           - Update event is used as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_ENABLE          - Uses counter enable signal as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_UPDATE          - Uses update event as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_COMPARE_PULSE   - Uses CC1IF flag as pulse source for TRGO outout.
+      * STM32_TIM_MASTERMODE_COMPARE_OC1REFC - OC1REFC signal is used as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_COMPARE_OC2REFC - OC2REFC signal is used as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_COMPARE_OC3REFC - OC3REFC signal is used as trigger output (TRGO).
+      * STM32_TIM_MASTERMODE_COMPARE_OC4REFC - OC4REFC signal is used as trigger output (TRGO).
diff --git a/include/zephyr/dt-bindings/timer/stm32-timer.h b/include/zephyr/dt-bindings/timer/stm32-timer.h
index cf9a4d0032062..c29d89be937f1 100644
--- a/include/zephyr/dt-bindings/timer/stm32-timer.h
+++ b/include/zephyr/dt-bindings/timer/stm32-timer.h
@@ -14,4 +14,15 @@
 #define STM32_TIM_COUNTERMODE_CENTER_UP      0x00000040U
 #define STM32_TIM_COUNTERMODE_CENTER_UP_DOWN 0x00000060U
 
+/* Timer master mode selection values */
+#define STM32_TIM_MASTERMODE_RESET           0x00000000U
+#define STM32_TIM_MASTERMODE_ENABLE          0x00000010U
+#define STM32_TIM_MASTERMODE_UPDATE          0x00000020U
+#define STM32_TIM_MASTERMODE_COMPARE_PULSE   0x00000030U
+#define STM32_TIM_MASTERMODE_COMPARE_OC1REFC 0x00000040U
+#define STM32_TIM_MASTERMODE_COMPARE_OC1REFC 0x00000040U
+#define STM32_TIM_MASTERMODE_COMPARE_OC2REFC 0x00000050U
+#define STM32_TIM_MASTERMODE_COMPARE_OC3REFC 0x00000060U
+#define STM32_TIM_MASTERMODE_COMPARE_OC4REFC 0x00000070U
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_STM32_TIMER_H_ */