diff --git a/drivers/flash/flash_mspi_nor.c b/drivers/flash/flash_mspi_nor.c index 444509b695b58..aa4b88813074f 100644 --- a/drivers/flash/flash_mspi_nor.c +++ b/drivers/flash/flash_mspi_nor.c @@ -26,8 +26,7 @@ LOG_MODULE_REGISTER(flash_mspi_nor, CONFIG_FLASH_LOG_LEVEL); #define NON_XIP_DEV_CFG_MASK (MSPI_DEVICE_CONFIG_ALL & ~XIP_DEV_CFG_MASK) static void set_up_xfer(const struct device *dev, enum mspi_xfer_direction dir); -static int perform_xfer(const struct device *dev, - uint8_t cmd, bool mem_access); +static int perform_xfer(const struct device *dev, uint8_t cmd); static int cmd_rdsr(const struct device *dev, uint8_t op_code, uint8_t *sr); static int wait_until_ready(const struct device *dev, k_timeout_t poll_period); static int cmd_wren(const struct device *dev); @@ -36,6 +35,14 @@ static int cmd_wrsr(const struct device *dev, uint8_t op_code, #include "flash_mspi_nor_quirks.h" +static bool in_octal_io(const struct device *dev) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + + return dev_data->last_applied_cfg && + dev_data->last_applied_cfg->io_mode == MSPI_IO_MODE_OCTAL; +} + static void set_up_xfer(const struct device *dev, enum mspi_xfer_direction dir) { const struct flash_mspi_nor_config *dev_config = dev->config; @@ -77,8 +84,7 @@ static uint16_t get_extended_command(const struct device *dev, return ((uint16_t)cmd << 8) | cmd_extension; } -static int perform_xfer(const struct device *dev, - uint8_t cmd, bool mem_access) +static int perform_xfer(const struct device *dev, uint8_t cmd) { const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; @@ -86,7 +92,7 @@ static int perform_xfer(const struct device *dev, int rc; if (dev_data->cmd_info.cmd_extension != CMD_EXTENSION_NONE && - dev_data->in_target_io_mode) { + in_octal_io(dev)) { dev_data->xfer.cmd_length = 2; dev_data->packet.cmd = get_extended_command(dev, cmd); } else { @@ -94,45 +100,28 @@ static int perform_xfer(const struct device *dev, dev_data->packet.cmd = cmd; } - if (dev_config->multi_io_cmd || - dev_config->mspi_nor_cfg.io_mode == MSPI_IO_MODE_SINGLE) { - /* If multiple IO lines are used in all the transfer phases - * or in none of them, there's no need to switch the IO mode. - */ - } else if (mem_access) { - /* For commands accessing the flash memory (read and program), - * ensure that the target IO mode is active. - */ - if (!dev_data->in_target_io_mode) { - cfg = &dev_config->mspi_nor_cfg; - } - } else { - /* For all other commands, switch to Single IO mode if a given - * command needs the data or address phase and in the target IO - * mode multiple IO lines are used in these phases. - */ - if (dev_data->in_target_io_mode) { - if (dev_data->packet.num_bytes != 0 || - (dev_data->xfer.addr_length != 0 && - !dev_config->single_io_addr)) { - /* Only the IO mode is to be changed, so the - * initial configuration structure can be used - * for this operation. - */ - cfg = &dev_config->mspi_nor_init_cfg; - } + /* If multiple IO lines are used in all the transfer phases + * there's no need to switch the IO mode. + */ + if (!dev_config->multi_io_cmd) { + if (cmd == dev_data->cmd_info.read_cmd) { + cfg = dev_data->read_cfg; + } else if (cmd == dev_data->cmd_info.pp_cmd) { + cfg = dev_data->write_cfg; + } else { + /* For all other commands, use control command config */ + cfg = &dev_data->mspi_control_cfg; } } - if (cfg) { + if (cfg && cfg != dev_data->last_applied_cfg) { rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, - MSPI_DEVICE_CONFIG_IO_MODE, cfg); + MSPI_DEVICE_CONFIG_IO_MODE | MSPI_DEVICE_CONFIG_FREQUENCY, cfg); if (rc < 0) { LOG_ERR("%s: dev_config() failed: %d", __func__, rc); return rc; } - - dev_data->in_target_io_mode = mem_access; + dev_data->last_applied_cfg = cfg; } rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, @@ -151,14 +140,14 @@ static int cmd_rdsr(const struct device *dev, uint8_t op_code, uint8_t *sr) int rc; set_up_xfer(dev, MSPI_RX); - if (dev_data->in_target_io_mode) { + if (in_octal_io(dev)) { dev_data->xfer.rx_dummy = dev_data->cmd_info.rdsr_dummy; dev_data->xfer.addr_length = dev_data->cmd_info.rdsr_addr_4 ? 4 : 0; } dev_data->packet.num_bytes = sizeof(uint8_t); dev_data->packet.data_buf = sr; - rc = perform_xfer(dev, op_code, false); + rc = perform_xfer(dev, op_code); if (rc < 0) { LOG_ERR("%s 0x%02x failed: %d", __func__, op_code, rc); return rc; @@ -194,7 +183,7 @@ static int cmd_wren(const struct device *dev) int rc; set_up_xfer(dev, MSPI_TX); - rc = perform_xfer(dev, SPI_NOR_CMD_WREN, false); + rc = perform_xfer(dev, SPI_NOR_CMD_WREN); if (rc < 0) { LOG_ERR("%s failed: %d", __func__, rc); return rc; @@ -217,7 +206,7 @@ static int cmd_wrsr(const struct device *dev, uint8_t op_code, set_up_xfer(dev, MSPI_TX); dev_data->packet.num_bytes = sr_cnt; dev_data->packet.data_buf = sr; - rc = perform_xfer(dev, op_code, false); + rc = perform_xfer(dev, op_code); if (rc < 0) { LOG_ERR("%s 0x%02x failed: %d", __func__, op_code, rc); return rc; @@ -262,7 +251,7 @@ static int acquire(const struct device *dev) LOG_ERR("mspi_dev_config() failed: %d", rc); } else { if (dev_config->multiperipheral_bus) { - dev_data->in_target_io_mode = true; + dev_data->last_applied_cfg = &dev_config->mspi_nor_cfg; } return 0; @@ -368,7 +357,7 @@ static int api_read(const struct device *dev, off_t addr, void *dest, dev_data->xfer.rx_dummy = get_rx_dummy(dev); dev_data->packet.data_buf = dest; dev_data->packet.num_bytes = to_read; - rc = perform_xfer(dev, dev_data->cmd_info.read_cmd, true); + rc = perform_xfer(dev, dev_data->cmd_info.read_cmd); addr += to_read; dest = (uint8_t *)dest + to_read; @@ -419,7 +408,7 @@ static int api_write(const struct device *dev, off_t addr, const void *src, set_up_xfer_with_addr(dev, MSPI_TX, addr); dev_data->packet.data_buf = (uint8_t *)src; dev_data->packet.num_bytes = to_write; - rc = perform_xfer(dev, dev_data->cmd_info.pp_cmd, true); + rc = perform_xfer(dev, dev_data->cmd_info.pp_cmd); if (rc < 0) { LOG_ERR("Page program xfer failed: %d", rc); break; @@ -491,7 +480,7 @@ static int api_erase(const struct device *dev, off_t addr, size_t size) if (size == flash_size) { /* Chip erase. */ set_up_xfer(dev, MSPI_TX); - rc = perform_xfer(dev, SPI_NOR_CMD_CE, false); + rc = perform_xfer(dev, SPI_NOR_CMD_CE); size -= flash_size; } else { @@ -500,7 +489,7 @@ static int api_erase(const struct device *dev, off_t addr, size_t size) if (best_et != NULL) { set_up_xfer_with_addr(dev, MSPI_TX, addr); - rc = perform_xfer(dev, best_et->cmd, false); + rc = perform_xfer(dev, best_et->cmd); addr += BIT(best_et->exp); size -= BIT(best_et->exp); @@ -554,7 +543,7 @@ static int sfdp_read(const struct device *dev, off_t addr, void *dest, int rc; set_up_xfer(dev, MSPI_RX); - if (dev_data->in_target_io_mode) { + if (in_octal_io(dev)) { dev_data->xfer.rx_dummy = dev_data->cmd_info.sfdp_dummy_20 ? 20 : 8; dev_data->xfer.addr_length = dev_data->cmd_info.sfdp_addr_4 @@ -566,7 +555,7 @@ static int sfdp_read(const struct device *dev, off_t addr, void *dest, dev_data->packet.address = addr; dev_data->packet.data_buf = dest; dev_data->packet.num_bytes = size; - rc = perform_xfer(dev, JESD216_CMD_READ_SFDP, false); + rc = perform_xfer(dev, JESD216_CMD_READ_SFDP); if (rc < 0) { LOG_ERR("Read SFDP xfer failed: %d", rc); } @@ -580,14 +569,14 @@ static int read_jedec_id(const struct device *dev, uint8_t *id) int rc; set_up_xfer(dev, MSPI_RX); - if (dev_data->in_target_io_mode) { + if (in_octal_io(dev)) { dev_data->xfer.rx_dummy = dev_data->cmd_info.rdid_dummy; dev_data->xfer.addr_length = dev_data->cmd_info.rdid_addr_4 ? 4 : 0; } dev_data->packet.data_buf = id; dev_data->packet.num_bytes = JESD216_READ_ID_LEN; - rc = perform_xfer(dev, SPI_NOR_CMD_RDID, false); + rc = perform_xfer(dev, SPI_NOR_CMD_RDID); if (rc < 0) { LOG_ERR("Read JEDEC ID failed: %d", rc); } @@ -777,7 +766,7 @@ static int octal_enable_set(const struct device *dev, bool enable) dev_data->packet.address = 0x02; dev_data->packet.num_bytes = sizeof(uint8_t); dev_data->packet.data_buf = &status_reg; - rc = perform_xfer(dev, op_code, false); + rc = perform_xfer(dev, op_code); if (rc < 0) { LOG_ERR("cmd_rdsr 0x%02x failed: %d", op_code, rc); return rc; @@ -813,7 +802,7 @@ static int enter_4byte_addressing_mode(const struct device *dev) } set_up_xfer(dev, MSPI_TX); - rc = perform_xfer(dev, 0xB7, false); + rc = perform_xfer(dev, 0xB7); if (rc < 0) { LOG_ERR("Command 0xB7 failed: %d", rc); return rc; @@ -867,9 +856,14 @@ static int switch_to_target_io_mode(const struct device *dev) } } - return mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, NON_XIP_DEV_CFG_MASK, &dev_config->mspi_nor_cfg); + if (rc < 0) { + return rc; + } + dev_data->last_applied_cfg = &dev_config->mspi_nor_cfg; + return 0; } #if defined(WITH_SUPPLY_GPIO) @@ -932,14 +926,14 @@ static int soft_reset_66_99(const struct device *dev) int rc; set_up_xfer(dev, MSPI_TX); - rc = perform_xfer(dev, SPI_NOR_CMD_RESET_EN, false); + rc = perform_xfer(dev, SPI_NOR_CMD_RESET_EN); if (rc < 0) { LOG_ERR("CMD_RESET_EN failed: %d", rc); return rc; } set_up_xfer(dev, MSPI_TX); - rc = perform_xfer(dev, SPI_NOR_CMD_RESET_MEM, false); + rc = perform_xfer(dev, SPI_NOR_CMD_RESET_MEM); if (rc < 0) { LOG_ERR("CMD_RESET_MEM failed: %d", rc); return rc; @@ -965,8 +959,7 @@ static int soft_reset(const struct device *dev) LOG_ERR("%s: dev_config() failed: %d", __func__, rc); return rc; } - - dev_data->in_target_io_mode = true; + dev_data->last_applied_cfg = &dev_config->mspi_nor_cfg; rc = soft_reset_66_99(dev); if (rc < 0) { @@ -975,13 +968,12 @@ static int soft_reset(const struct device *dev) rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, MSPI_DEVICE_CONFIG_IO_MODE, - &dev_config->mspi_nor_init_cfg); + &dev_data->mspi_control_cfg); if (rc < 0) { LOG_ERR("%s: dev_config() failed: %d", __func__, rc); return rc; } - - dev_data->in_target_io_mode = false; + dev_data->last_applied_cfg = &dev_data->mspi_control_cfg; } rc = soft_reset_66_99(dev); @@ -997,21 +989,24 @@ static int flash_chip_init(const struct device *dev) { const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; + uint32_t target_freq = dev_data->mspi_control_cfg.freq; uint8_t id[JESD216_READ_ID_LEN] = {0}; uint16_t dts_cmd = 0; uint32_t sfdp_signature; bool flash_reset = false; int rc; + /* Do initial checks at max 50MHz required to be supported by JEDEC */ + dev_data->mspi_control_cfg.freq = MIN(target_freq, MHZ(50)); rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, MSPI_DEVICE_CONFIG_ALL, - &dev_config->mspi_nor_init_cfg); + &dev_data->mspi_control_cfg); if (rc < 0) { LOG_ERR("%s: dev_config() failed: %d", __func__, rc); return rc; } - - dev_data->in_target_io_mode = false; + dev_data->last_applied_cfg = &dev_data->mspi_control_cfg; + dev_data->mspi_control_cfg.freq = target_freq; #if defined(WITH_SUPPLY_GPIO) if (dev_config->supply.port) { @@ -1086,6 +1081,33 @@ static int flash_chip_init(const struct device *dev) } } + /* If read/write commands and frequency do not match the default + * MSPI device configuration, store new ones for those commands + * specifically. + */ + if (dev_config->read_io_mode == dev_config->mspi_nor_cfg.io_mode && + dev_config->read_freq == dev_config->mspi_nor_cfg.freq) { + dev_data->read_cfg = &dev_config->mspi_nor_cfg; + } else { + memcpy(&dev_data->mspi_dev_read_cfg, &dev_config->mspi_nor_cfg, + sizeof(dev_config->mspi_nor_cfg)); + dev_data->mspi_dev_read_cfg.io_mode = dev_config->read_io_mode; + dev_data->mspi_dev_read_cfg.freq = dev_config->read_freq; + dev_data->read_cfg = &dev_data->mspi_dev_read_cfg; + } + + if (dev_config->write_io_mode == dev_config->mspi_nor_cfg.io_mode && + dev_config->write_freq == dev_config->mspi_nor_cfg.freq) { + dev_data->write_cfg = &dev_config->mspi_nor_cfg; + } else { + memcpy(&dev_data->mspi_dev_write_cfg, &dev_config->mspi_nor_cfg, + sizeof(dev_config->mspi_nor_cfg)); + dev_data->mspi_dev_write_cfg.io_mode = dev_config->write_io_mode; + dev_data->mspi_dev_write_cfg.freq = dev_config->write_freq; + dev_data->write_cfg = &dev_data->mspi_dev_write_cfg; + } + + if (dev_config->jedec_id_specified) { rc = read_jedec_id(dev, id); if (rc < 0) { @@ -1110,8 +1132,6 @@ static int flash_chip_init(const struct device *dev) return rc; } - dev_data->in_target_io_mode = true; - if (IS_ENABLED(CONFIG_FLASH_MSPI_NOR_USE_SFDP)) { /* Read the SFDP signature to test if communication with * the flash chip can be successfully performed after switching @@ -1133,31 +1153,30 @@ static int flash_chip_init(const struct device *dev) #if defined(CONFIG_MSPI_XIP) /* Enable XIP access for this chip if specified so in DT. */ if (dev_config->xip_cfg.enable) { - struct mspi_dev_cfg mspi_cfg = { - .addr_length = dev_data->cmd_info.uses_4byte_addr - ? 4 : 3, - .rx_dummy = get_rx_dummy(dev), - }; + struct mspi_dev_cfg *mspi_cfg = &dev_data->mspi_dev_xip_cfg; + mspi_cfg->addr_length = dev_data->cmd_info.uses_4byte_addr ? 4 : 3; + mspi_cfg->rx_dummy = get_rx_dummy(dev); if (dev_data->cmd_info.cmd_extension != CMD_EXTENSION_NONE) { - mspi_cfg.cmd_length = 2; - mspi_cfg.read_cmd = get_extended_command(dev, + mspi_cfg->cmd_length = 2; + mspi_cfg->read_cmd = get_extended_command(dev, dev_data->cmd_info.read_cmd); - mspi_cfg.write_cmd = get_extended_command(dev, + mspi_cfg->write_cmd = get_extended_command(dev, dev_data->cmd_info.pp_cmd); } else { - mspi_cfg.cmd_length = 1; - mspi_cfg.read_cmd = dev_data->cmd_info.read_cmd; - mspi_cfg.write_cmd = dev_data->cmd_info.pp_cmd; + mspi_cfg->cmd_length = 1; + mspi_cfg->read_cmd = dev_data->cmd_info.read_cmd; + mspi_cfg->write_cmd = dev_data->cmd_info.pp_cmd; } rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, - XIP_DEV_CFG_MASK, &mspi_cfg); + XIP_DEV_CFG_MASK, mspi_cfg); if (rc < 0) { LOG_ERR("Failed to configure controller for XIP: %d", rc); return rc; } + dev_data->last_applied_cfg = mspi_cfg; rc = mspi_xip_config(dev_config->bus, &dev_config->mspi_id, &dev_config->xip_cfg); @@ -1261,10 +1280,12 @@ static DEVICE_API(flash, drv_api) = { #endif }; -#define FLASH_INITIAL_CONFIG(inst) \ +#define FLASH_MSPI_MAX_FREQ(inst) DT_INST_PROP(inst, mspi_max_frequency) + +#define FLASH_CONTROL_CMD_CONFIG(inst) \ { \ .ce_num = DT_INST_PROP_OR(inst, mspi_hardware_ce_num, 0), \ - .freq = MIN(DT_INST_PROP(inst, mspi_max_frequency), MHZ(50)), \ + .freq = FLASH_MSPI_MAX_FREQ(inst), \ .io_mode = MSPI_IO_MODE_SINGLE, \ .data_rate = MSPI_DATA_RATE_SINGLE, \ .cpp = MSPI_CPP_MODE_0, \ @@ -1321,7 +1342,9 @@ BUILD_ASSERT((FLASH_SIZE(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \ SFDP_BUILD_ASSERTS(inst); \ PM_DEVICE_DT_INST_DEFINE(inst, dev_pm_action_cb); \ DEFAULT_ERASE_TYPES_DEFINE(inst); \ - static struct flash_mspi_nor_data dev##inst##_data; \ + static struct flash_mspi_nor_data dev##inst##_data = { \ + .mspi_control_cfg = FLASH_CONTROL_CMD_CONFIG(inst), \ + }; \ static const struct flash_mspi_nor_config dev##inst##_config = { \ .bus = DEVICE_DT_GET(DT_INST_BUS(inst)), \ .packet_data_limit = DT_PROP_OR(DT_INST_BUS(inst), \ @@ -1330,7 +1353,6 @@ BUILD_ASSERT((FLASH_SIZE(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \ .page_size = FLASH_PAGE_SIZE(inst), \ .mspi_id = MSPI_DEVICE_ID_DT_INST(inst), \ .mspi_nor_cfg = MSPI_DEVICE_CONFIG_DT_INST(inst), \ - .mspi_nor_init_cfg = FLASH_INITIAL_CONFIG(inst), \ IF_ENABLED(CONFIG_MSPI_XIP, \ (.xip_cfg = MSPI_XIP_CONFIG_DT_INST(inst),)) \ IF_ENABLED(WITH_SUPPLY_GPIO, \ @@ -1348,6 +1370,14 @@ BUILD_ASSERT((FLASH_SIZE(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \ .default_erase_types = DEFAULT_ERASE_TYPES(inst), \ .default_cmd_info = DEFAULT_CMD_INFO(inst), \ .default_switch_info = DEFAULT_SWITCH_INFO(inst), \ + .read_freq = DT_INST_PROP_OR(inst, read_frequency, \ + FLASH_MSPI_MAX_FREQ(inst)), \ + .read_io_mode = DT_INST_ENUM_IDX_OR(inst, read_io_mode, \ + DT_INST_ENUM_IDX(inst, mspi_io_mode)), \ + .write_freq = DT_INST_PROP_OR(inst, write_frequency, \ + FLASH_MSPI_MAX_FREQ(inst)), \ + .write_io_mode = DT_INST_ENUM_IDX_OR(inst, write_io_mode, \ + DT_INST_ENUM_IDX(inst, mspi_io_mode)), \ .jedec_id_specified = DT_INST_NODE_HAS_PROP(inst, jedec_id), \ .rx_dummy_specified = DT_INST_NODE_HAS_PROP(inst, rx_dummy), \ .multiperipheral_bus = DT_PROP(DT_INST_BUS(inst), \ diff --git a/drivers/flash/flash_mspi_nor.h b/drivers/flash/flash_mspi_nor.h index 335af449b2616..5a6a489ddbcba 100644 --- a/drivers/flash/flash_mspi_nor.h +++ b/drivers/flash/flash_mspi_nor.h @@ -75,7 +75,6 @@ struct flash_mspi_nor_config { uint16_t page_size; struct mspi_dev_id mspi_id; struct mspi_dev_cfg mspi_nor_cfg; - struct mspi_dev_cfg mspi_nor_init_cfg; #if defined(CONFIG_MSPI_XIP) struct mspi_xip_cfg xip_cfg; #endif @@ -96,6 +95,10 @@ struct flash_mspi_nor_config { const struct jesd216_erase_type *default_erase_types; struct flash_mspi_nor_cmd_info default_cmd_info; struct flash_mspi_nor_switch_info default_switch_info; + uint32_t read_freq; + enum mspi_io_mode read_io_mode; + uint32_t write_freq; + enum mspi_io_mode write_io_mode; bool jedec_id_specified : 1; bool rx_dummy_specified : 1; bool multiperipheral_bus : 1; @@ -113,7 +116,15 @@ struct flash_mspi_nor_data { struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES]; struct flash_mspi_nor_cmd_info cmd_info; struct flash_mspi_nor_switch_info switch_info; - bool in_target_io_mode; + struct mspi_dev_cfg mspi_control_cfg; +#if defined(CONFIG_MSPI_XIP) + struct mspi_dev_cfg mspi_dev_xip_cfg; +#endif + const struct mspi_dev_cfg *last_applied_cfg; + const struct mspi_dev_cfg *read_cfg; + struct mspi_dev_cfg mspi_dev_read_cfg; + const struct mspi_dev_cfg *write_cfg; + struct mspi_dev_cfg mspi_dev_write_cfg; }; #ifdef __cplusplus diff --git a/drivers/flash/flash_mspi_nor_quirks.h b/drivers/flash/flash_mspi_nor_quirks.h index d58fbea4ff9b8..83480b4643a8e 100644 --- a/drivers/flash/flash_mspi_nor_quirks.h +++ b/drivers/flash/flash_mspi_nor_quirks.h @@ -80,7 +80,7 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev) set_up_xfer(dev, MSPI_TX); dev_data->packet.data_buf = mxicy_mx25r_hp_payload; dev_data->packet.num_bytes = sizeof(mxicy_mx25r_hp_payload); - rc = perform_xfer(dev, SPI_NOR_CMD_WRSR, false); + rc = perform_xfer(dev, SPI_NOR_CMD_WRSR); if (rc < 0) { return rc; } @@ -101,7 +101,7 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev) set_up_xfer(dev, MSPI_RX); dev_data->packet.num_bytes = sizeof(config); dev_data->packet.data_buf = config; - rc = perform_xfer(dev, SPI_NOR_CMD_RDCR, false); + rc = perform_xfer(dev, SPI_NOR_CMD_RDCR); if (rc < 0) { return rc; } @@ -159,7 +159,7 @@ static inline int mxicy_mx25u_post_switch_mode(const struct device *dev) dev_data->packet.address = 0; dev_data->packet.data_buf = &opi_enable; dev_data->packet.num_bytes = sizeof(opi_enable); - return perform_xfer(dev, SPI_NOR_CMD_WR_CFGREG2, false); + return perform_xfer(dev, SPI_NOR_CMD_WR_CFGREG2); } static int mxicy_mx25u_pre_init(const struct device *dev) @@ -192,7 +192,7 @@ static int mxicy_mx25u_pre_init(const struct device *dev) dev_data->packet.address = 0x300; dev_data->packet.data_buf = &cfg_reg; dev_data->packet.num_bytes = sizeof(cfg_reg); - rc = perform_xfer(dev, SPI_NOR_CMD_RD_CFGREG2, false); + rc = perform_xfer(dev, SPI_NOR_CMD_RD_CFGREG2); if (rc < 0) { LOG_ERR("Failed to read Dummy Cycle from CFGREG2"); return rc; diff --git a/dts/bindings/mtd/jedec,mspi-nor.yaml b/dts/bindings/mtd/jedec,mspi-nor.yaml index 348e11cd98339..e59fe117557e9 100644 --- a/dts/bindings/mtd/jedec,mspi-nor.yaml +++ b/dts/bindings/mtd/jedec,mspi-nor.yaml @@ -21,6 +21,62 @@ include: - t-exit-dpd properties: + read-frequency: + type: int + description: | + Clock frequency of device to configure in Hz for read + command, when reads are desired to be in a different + frequency than the rest of the commands. + + read-io-mode: + type: string + enum: + - "MSPI_IO_MODE_SINGLE" + - "MSPI_IO_MODE_DUAL" + - "MSPI_IO_MODE_DUAL_1_1_2" + - "MSPI_IO_MODE_DUAL_1_2_2" + - "MSPI_IO_MODE_QUAD" + - "MSPI_IO_MODE_QUAD_1_1_4" + - "MSPI_IO_MODE_QUAD_1_4_4" + - "MSPI_IO_MODE_OCTAL" + - "MSPI_IO_MODE_OCTAL_1_1_8" + - "MSPI_IO_MODE_OCTAL_1_8_8" + - "MSPI_IO_MODE_HEX" + - "MSPI_IO_MODE_HEX_8_8_16" + - "MSPI_IO_MODE_HEX_8_16_16" + description: | + MSPI I/O mode setting for read command when desired to + be different from base device `mspi-io-mode` for the rest + of the commands. + + write-frequency: + type: int + description: | + Clock frequency of device to configure in Hz for write + command, when write are desired to be in a different + frequency than the rest of the commands. + + write-io-mode: + type: string + enum: + - "MSPI_IO_MODE_SINGLE" + - "MSPI_IO_MODE_DUAL" + - "MSPI_IO_MODE_DUAL_1_1_2" + - "MSPI_IO_MODE_DUAL_1_2_2" + - "MSPI_IO_MODE_QUAD" + - "MSPI_IO_MODE_QUAD_1_1_4" + - "MSPI_IO_MODE_QUAD_1_4_4" + - "MSPI_IO_MODE_OCTAL" + - "MSPI_IO_MODE_OCTAL_1_1_8" + - "MSPI_IO_MODE_OCTAL_1_8_8" + - "MSPI_IO_MODE_HEX" + - "MSPI_IO_MODE_HEX_8_8_16" + - "MSPI_IO_MODE_HEX_8_16_16" + description: | + MSPI I/O mode setting for write command when desired to + be different from base device `mspi-io-mode` for the rest + of the commands. + reset-gpios: type: phandle-array description: |