diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 722becfb56d55..ab72f9fc0a1e8 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -1,29 +1,37 @@ # Copyright (c) 2022 Carlo Caione # SPDX-License-Identifier: Apache-2.0 +RISCV_ISA_BASE_PROP := riscv,isa-base +RISCV_ISA_EXT_PROP := riscv,isa-extensions + config RISCV_ISA_RV32I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32i) help RV32I Base Integer Instruction Set - 32bit config RISCV_ISA_RV32E bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32e) help RV32E Base Integer Instruction Set (Embedded) - 32bit config RISCV_ISA_RV64I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv64i) default y if 64BIT help RV64I Base Integer Instruction Set - 64bit config RISCV_ISA_RV128I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv128i) help RV128I Base Integer Instruction Set - 128bit config RISCV_ISA_EXT_M bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),m) help (M) - Standard Extension for Integer Multiplication and Division @@ -33,6 +41,7 @@ config RISCV_ISA_EXT_M config RISCV_ISA_EXT_A bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),a) imply RISCV_ISA_EXT_ZAAMO imply RISCV_ISA_EXT_ZALRSC help @@ -45,6 +54,7 @@ config RISCV_ISA_EXT_A config RISCV_ISA_EXT_F bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),f) help (F) - Standard Extension for Single-Precision Floating-Point @@ -55,6 +65,7 @@ config RISCV_ISA_EXT_F config RISCV_ISA_EXT_D bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),d) depends on RISCV_ISA_EXT_F help (D) - Standard Extension for Double-Precision Floating-Point @@ -66,6 +77,7 @@ config RISCV_ISA_EXT_D config RISCV_ISA_EXT_G bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),g) select RISCV_ISA_EXT_M select RISCV_ISA_EXT_A select RISCV_ISA_EXT_F @@ -77,6 +89,7 @@ config RISCV_ISA_EXT_G config RISCV_ISA_EXT_Q bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),q) depends on RISCV_ISA_RV64I depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_D @@ -89,6 +102,7 @@ config RISCV_ISA_EXT_Q config RISCV_ISA_EXT_C bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),c) select RISCV_ISA_EXT_ZCA select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) @@ -101,6 +115,7 @@ config RISCV_ISA_EXT_C config RISCV_ISA_EXT_ZICNTR bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicntr) depends on RISCV_ISA_EXT_ZICSR help (Zicntr) - Standard Extension for Base Counters and Timers @@ -111,6 +126,7 @@ config RISCV_ISA_EXT_ZICNTR config RISCV_ISA_EXT_ZICSR bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicsr) help (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions @@ -119,6 +135,7 @@ config RISCV_ISA_EXT_ZICSR config RISCV_ISA_EXT_ZIFENCEI bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zifencei) help (Zifencei) - Standard Extension for Instruction-Fetch Fence @@ -128,6 +145,7 @@ config RISCV_ISA_EXT_ZIFENCEI config RISCV_ISA_EXT_ZAAMO bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zaamo) help (Zaamo) - Atomic memory operation subset of the A extension @@ -135,6 +153,7 @@ config RISCV_ISA_EXT_ZAAMO config RISCV_ISA_EXT_ZALRSC bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zalrsc) help (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension @@ -142,6 +161,7 @@ config RISCV_ISA_EXT_ZALRSC config RISCV_ISA_EXT_ZCA bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zca) help (Zca) - Zba Extension for Compressed Instructions @@ -150,6 +170,7 @@ config RISCV_ISA_EXT_ZCA config RISCV_ISA_EXT_ZCB bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcb) depends on RISCV_ISA_EXT_ZCA help (Zcb) - Zcb Extension for Simple Compressed Instructions @@ -159,6 +180,7 @@ config RISCV_ISA_EXT_ZCB config RISCV_ISA_EXT_ZCD bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcd) depends on RISCV_ISA_EXT_D depends on RISCV_ISA_EXT_ZCA help @@ -169,6 +191,7 @@ config RISCV_ISA_EXT_ZCD config RISCV_ISA_EXT_ZCF bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcf) depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_ZCA @@ -180,6 +203,7 @@ config RISCV_ISA_EXT_ZCF config RISCV_ISA_EXT_ZCMP bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmp) depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD help @@ -190,6 +214,7 @@ config RISCV_ISA_EXT_ZCMP config RISCV_ISA_EXT_ZCMT bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmt) depends on RISCV_ISA_EXT_ZICSR depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD @@ -201,6 +226,7 @@ config RISCV_ISA_EXT_ZCMT config RISCV_ISA_EXT_ZBA bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zba) help (Zba) - Zba BitManip Extension @@ -211,6 +237,7 @@ config RISCV_ISA_EXT_ZBA config RISCV_ISA_EXT_ZBB bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbb) help (Zbb) - Zbb BitManip Extension (Basic bit-manipulation) @@ -220,6 +247,7 @@ config RISCV_ISA_EXT_ZBB config RISCV_ISA_EXT_ZBC bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbc) help (Zbc) - Zbc BitManip Extension (Carry-less multiplication) @@ -228,6 +256,7 @@ config RISCV_ISA_EXT_ZBC config RISCV_ISA_EXT_ZBS bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbs) help (Zbs) - Zbs BitManip Extension (Single-bit instructions) @@ -237,6 +266,7 @@ config RISCV_ISA_EXT_ZBS config RISCV_ISA_EXT_ZMMUL bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zmmul) help (Zmmul) - Zmmul Extension for Integer Multiplication diff --git a/doc/build/kconfig/preprocessor-functions.rst b/doc/build/kconfig/preprocessor-functions.rst index ab7429963409b..e4e3e33e74057 100644 --- a/doc/build/kconfig/preprocessor-functions.rst +++ b/doc/build/kconfig/preprocessor-functions.rst @@ -46,6 +46,7 @@ while the ``*_hex`` version returns a hexadecimal value starting with ``0x``. $(dt_compat_on_bus,,) $(dt_gpio_hogs_enabled) $(dt_has_compat,) + $(dt_node_array_prop_has_val,,,) $(dt_node_array_prop_hex,,,[,]) $(dt_node_array_prop_int,,,[,]) $(dt_node_bool_prop,,) diff --git a/dts/bindings/cpu/riscv,cpus.yaml b/dts/bindings/cpu/riscv,cpus.yaml index 883146d76b2ae..7bdd9a5bd0527 100644 --- a/dts/bindings/cpu/riscv,cpus.yaml +++ b/dts/bindings/cpu/riscv,cpus.yaml @@ -15,5 +15,12 @@ properties: riscv,isa: description: RISC-V instruction set architecture - required: true type: string + + riscv,isa-base: + description: The base ISA implemented by the hart. + type: string + + riscv,isa-extensions: + description: Extensions supported by the hart. + type: string-array diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index 33f7bd03fc286..9d6d953aef6be 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -26,6 +26,8 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv32im_zicsr_zifencei"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "i", "m", "zicsr", "zifencei"; status = "okay"; }; }; diff --git a/scripts/kconfig/kconfigfunctions.py b/scripts/kconfig/kconfigfunctions.py index 4bc69d4398b1b..7c70ab9b6783a 100644 --- a/scripts/kconfig/kconfigfunctions.py +++ b/scripts/kconfig/kconfigfunctions.py @@ -888,6 +888,8 @@ def dt_nodelabel_array_prop_has_val(kconf, _, label, prop, val): If the node exists, it checks if the node node has a property 'prop' with type "array". If so, and the property contains an element equal to the integer 'val', it returns "y". + If the property is of type "string-array", it checks if 'val' is + one of the strings in the array, returning "y" if so. Otherwise, it returns "n". """ if doc_mode or edt is None: @@ -895,10 +897,42 @@ def dt_nodelabel_array_prop_has_val(kconf, _, label, prop, val): node = edt.label2node.get(label) - if not node or (prop not in node.props) or (node.props[prop].type != "array"): + if not node or (prop not in node.props): return "n" + elif node.props[prop].type == "array": + return "y" if int(val, base=0) in node.props[prop].val else "n" + elif node.props[prop].type == "string-array": + return "y" if val in node.props[prop].val else "n" else: + return "n" + + +def dt_node_array_prop_has_val(kconf, _, path, prop, val): + """ + This function looks for a node at 'path'. + If the node exists, it checks if the node has a property + 'prop' with type "array". If so, and the property contains + an element equal to the integer 'val', it returns "y". + If the property is of type "string-array", it checks if 'val' is + one of the strings in the array, returning "y" if so. + Otherwise, it returns "n". + """ + if doc_mode or edt is None: + return "n" + + try: + node = edt.get_node(path) + except edtlib.EDTError: + return "n" + + if not node or (prop not in node.props): + return "n" + elif node.props[prop].type == "array": return "y" if int(val, base=0) in node.props[prop].val else "n" + elif node.props[prop].type == "string-array": + return "y" if val in node.props[prop].val else "n" + else: + return "n" def dt_nodelabel_path(kconf, _, label): @@ -1123,6 +1157,7 @@ def inc_dec(kconf, name, *args): "dt_nodelabel_path": (dt_nodelabel_path, 1, 1), "dt_node_parent": (dt_node_parent, 1, 1), "dt_nodelabel_array_prop_has_val": (dt_nodelabel_array_prop_has_val, 3, 3), + "dt_node_array_prop_has_val": (dt_node_array_prop_has_val, 3, 3), "dt_gpio_hogs_enabled": (dt_gpio_hogs_enabled, 0, 0), "dt_chosen_partition_addr_int": (dt_chosen_partition_addr, 1, 3), "dt_chosen_partition_addr_hex": (dt_chosen_partition_addr, 1, 3), diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig index 6a684f5c4ca9a..8750f724f2169 100644 --- a/soc/litex/litex_vexriscv/Kconfig +++ b/soc/litex/litex_vexriscv/Kconfig @@ -4,10 +4,6 @@ config SOC_LITEX_VEXRISCV select RISCV select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI imply XIP if SOC_LITEX_VEXRISCV