diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6.dts b/boards/st/nucleo_c031c6/nucleo_c031c6.dts index 35949cc93bab1..73d62c78e8a35 100644 --- a/boards/st/nucleo_c031c6/nucleo_c031c6.dts +++ b/boards/st/nucleo_c031c6/nucleo_c031c6.dts @@ -119,6 +119,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_SYSCLK ADC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>; pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.dts b/boards/st/nucleo_c071rb/nucleo_c071rb.dts index 73ba63c1fa52a..b143f6becbd41 100644 --- a/boards/st/nucleo_c071rb/nucleo_c071rb.dts +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.dts @@ -152,6 +152,7 @@ st,adc-clock-source = "ASYNC"; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_HSI ADC_SEL(2)>; + clock-names = "adcx", "adc_ker"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; diff --git a/boards/st/nucleo_c092rc/nucleo_c092rc.dts b/boards/st/nucleo_c092rc/nucleo_c092rc.dts index d3bf59e195b4e..6a1147abd94ac 100644 --- a/boards/st/nucleo_c092rc/nucleo_c092rc.dts +++ b/boards/st/nucleo_c092rc/nucleo_c092rc.dts @@ -167,6 +167,7 @@ st,adc-clock-source = "ASYNC"; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_HSI ADC_SEL(2)>; + clock-names = "adcx", "adc_ker"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; diff --git a/boards/st/nucleo_f103rb/nucleo_f103rb.dts b/boards/st/nucleo_f103rb/nucleo_f103rb.dts index ef3abcbff6659..fe4a9cd3b7a39 100644 --- a/boards/st/nucleo_f103rb/nucleo_f103rb.dts +++ b/boards/st/nucleo_f103rb/nucleo_f103rb.dts @@ -71,7 +71,6 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; - adc-prescaler = <2>; }; &usart1 { diff --git a/boards/st/nucleo_f303k8/nucleo_f303k8.dts b/boards/st/nucleo_f303k8/nucleo_f303k8.dts index f748c976d9987..31466a2c3c702 100644 --- a/boards/st/nucleo_f303k8/nucleo_f303k8.dts +++ b/boards/st/nucleo_f303k8/nucleo_f303k8.dts @@ -66,7 +66,6 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; - adc12-prescaler = <0>; }; &timers2 { diff --git a/boards/st/nucleo_f303re/nucleo_f303re.dts b/boards/st/nucleo_f303re/nucleo_f303re.dts index 0535f1163481e..22497abbd2221 100644 --- a/boards/st/nucleo_f303re/nucleo_f303re.dts +++ b/boards/st/nucleo_f303re/nucleo_f303re.dts @@ -71,8 +71,6 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; - adc12-prescaler = <0>; - adc34-prescaler = <0>; }; &usart2 { diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts index 3128f8e0122ac..f7d0639083189 100644 --- a/boards/st/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/st/nucleo_g071rb/nucleo_g071rb.dts @@ -147,6 +147,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_SYSCLK ADC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/boards/st/nucleo_h533re/nucleo_h533re.dts b/boards/st/nucleo_h533re/nucleo_h533re.dts index 818707efc20a5..c51a51014dabb 100644 --- a/boards/st/nucleo_h533re/nucleo_h533re.dts +++ b/boards/st/nucleo_h533re/nucleo_h533re.dts @@ -131,6 +131,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp0_pa0>; /* Arduino A0 */ pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 75f824c0d9e8f..e3082eee2d6ba 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -158,6 +158,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp3_pa6 &adc1_inp15_pa3>; /* Zio A0, Zio D35 */ pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi index 7bbb69b776935..1a750a081ce4b 100644 --- a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi +++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi @@ -61,8 +61,8 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = , - ; + gpio-map = , + ; }; }; @@ -170,6 +170,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_CKPER ADC12_SEL(1)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */ pinctrl-names = "default"; vref-mv = <1800>; diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts index b9cc5ffc4738f..1adbca30c8478 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.dts +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts @@ -120,6 +120,7 @@ st,adc-clock-source = "ASYNC"; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_HSI ADC_SEL(2)>; + clock-names = "adcx", "adc_ker"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk-common.dtsi b/boards/st/stm32h573i_dk/stm32h573i_dk-common.dtsi index cf0c211cfcc63..bd65b516742e2 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk-common.dtsi +++ b/boards/st/stm32h573i_dk/stm32h573i_dk-common.dtsi @@ -321,6 +321,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A5 */ pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi index e93f6ffa86f14..c1c94cce15a92 100644 --- a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi +++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi @@ -241,6 +241,7 @@ &adc1 { clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_CKPER ADC12_SEL(1)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */ pinctrl-names = "default"; vref-mv = <1800>; diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts index 4506778fd18af..8a5a38a247362 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.dts +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts @@ -80,6 +80,7 @@ st,adc-clock-source = "ASYNC"; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_HSI ADC_SEL(2)>; + clock-names = "adcx", "adc_ker"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; diff --git a/boards/weact/blackpill_h523ce/blackpill_h523ce.dts b/boards/weact/blackpill_h523ce/blackpill_h523ce.dts index b7914b2fe54b9..8e8126ecdacea 100644 --- a/boards/weact/blackpill_h523ce/blackpill_h523ce.dts +++ b/boards/weact/blackpill_h523ce/blackpill_h523ce.dts @@ -91,6 +91,7 @@ zephyr_udc0: &usb { &adc1 { clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; pinctrl-0 = <&adc1_inp1_pa1>; pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; diff --git a/doc/releases/migration-guide-4.3.rst b/doc/releases/migration-guide-4.3.rst index 9369e5c2db23f..2bb59cf57d6d9 100644 --- a/doc/releases/migration-guide-4.3.rst +++ b/doc/releases/migration-guide-4.3.rst @@ -96,6 +96,11 @@ ADC * ``iadc_gecko.c`` driver is replaced by ``adc_silabs_iadc.c``. :dtcompatible:`silabs,gecko-iadc` is replaced by :dtcompatible:`silabs,iadc`. +* :dtcompatible:`st,stm32-adc` and its derivatives now require the ``clock-names`` property to be + defined and to match the number of clocks in the ``clocks`` property. The expected clock names are + ``adcx`` for the register clock, ``adc-ker`` for the kernel source clock, and ``adc-pre`` to set + the ADC prescaler (for series where it is located in the RCC registers). + Clock Control ============= @@ -104,6 +109,11 @@ Clock Control is enabled (otherwise, the symbol is not defined). This change should only affect STM32 MPU-based platforms and aligns them with existing practice from STM32 MCU platforms. +* :dtcompatible:`st,stm32f1-rcc` and :dtcompatible:`st,stm32f3-rcc` do not exist anymore. Therefore + ``adc-prescaler``, ``adc12-prescaler`` and ``adc34-prescaler`` properties are no longer defined + either. They are replaced by adding the prescaler as an additional clock in the ADC ``clocks`` + property. + Comparator ========== diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 677c5101675e0..0f2c4c23142af 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -216,8 +216,9 @@ struct adc_stm32_data { struct adc_stm32_cfg { ADC_TypeDef *base; void (*irq_cfg_func)(void); - const struct stm32_pclken *pclken; - size_t pclk_len; + const struct stm32_pclken pclken; + const struct stm32_pclken pclken_ker; + const struct stm32_pclken pclken_pre; uint32_t clk_prescaler; const struct pinctrl_dev_config *pcfg; const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME]; @@ -225,6 +226,8 @@ struct adc_stm32_cfg { int8_t sequencer_type; int8_t oversampler_type; int8_t internal_regulator; + bool has_pclken_ker :1; + bool has_pclken_pre :1; bool has_deep_powerdown :1; bool has_channel_preselection :1; bool has_differential_support :1; @@ -471,8 +474,7 @@ static void adc_stm32_calibration_delay(const struct device *dev) const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); uint32_t adc_rate, wait_cycles; - if (clock_control_get_rate(clk, - (clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) { + if (clock_control_get_rate(clk, (clock_control_subsys_t)&config->pclken, &adc_rate) < 0) { LOG_ERR("ADC clock rate get error."); } @@ -1496,8 +1498,8 @@ static int adc_stm32h7_setup_boost(const struct adc_stm32_cfg *config, ADC_TypeD int presc; /* Get the input frequency */ - clk_src = (clock_control_subsys_t)(adc_stm32_is_clk_sync(config) ? &config->pclken[0] - : &config->pclken[1]); + clk_src = (clock_control_subsys_t)(adc_stm32_is_clk_sync(config) ? &config->pclken + : &config->pclken_ker); if (clock_control_get_rate(clk, clk_src, &input_freq) != 0) { LOG_ERR("Failed to get ADC clock frequency"); @@ -1534,14 +1536,6 @@ static int adc_stm32h7_setup_boost(const struct adc_stm32_cfg *config, ADC_TypeD } #endif -/* This symbol takes the value 1 if one of the device instances */ -/* is configured in dts with a domain clock */ -#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT -#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1 -#else -#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0 -#endif - static int adc_stm32_set_clock(const struct device *dev) { const struct adc_stm32_cfg *config = dev->config; @@ -1549,18 +1543,20 @@ static int adc_stm32_set_clock(const struct device *dev) __maybe_unused ADC_TypeDef *adc = config->base; int ret = 0; - if (clock_control_on(clk, - (clock_control_subsys_t) &config->pclken[0]) != 0) { + if (clock_control_on(clk, (clock_control_subsys_t)&config->pclken) != 0) { return -EIO; } - if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { - /* Enable ADC clock source */ - if (clock_control_configure(clk, - (clock_control_subsys_t) &config->pclken[1], - NULL) != 0) { - return -EIO; - } + /* Enable ADC clock source if applicable */ + if (config->has_pclken_ker && + clock_control_configure(clk, (clock_control_subsys_t)&config->pclken_ker, NULL) != 0) { + return -EIO; + } + + /* Configure ADC prescaler (at RCC level) if applicable */ + if (config->has_pclken_pre && + clock_control_configure(clk, (clock_control_subsys_t)&config->pclken_pre, NULL) != 0) { + return -EIO; } #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source) @@ -1735,7 +1731,7 @@ static int adc_stm32_suspend_setup(const struct device *dev) adc_stm32_disable_analog_supply(); /* Stop device clock. Note: fixed clocks are not handled yet. */ - err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]); + err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken); if (err != 0) { LOG_ERR("Could not disable ADC clock"); return err; @@ -1806,7 +1802,7 @@ static DEVICE_API(adc, api_stm32_driver_api) = { /* Macro to check if the ADC instance clock setup is correct */ #define ADC_STM32_CHECK_DT_CLOCK(x) \ - BUILD_ASSERT(IS_EQ(ADC_STM32_CLOCK(x), SYNC) || (DT_INST_NUM_CLOCKS(x) > 1), \ + BUILD_ASSERT(IS_EQ(ADC_STM32_CLOCK(x), SYNC) || DT_INST_CLOCKS_HAS_NAME(x, adc_ker), \ "ASYNC clock mode defined without ASYNC clock defined in device tree") #else /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source) */ @@ -1963,14 +1959,21 @@ ADC_STM32_CHECK_DT_CLOCK(index); \ \ PINCTRL_DT_INST_DEFINE(index); \ \ -static const struct stm32_pclken pclken_##index[] = \ - STM32_DT_INST_CLOCKS(index); \ - \ static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \ .base = (ADC_TypeDef *)DT_INST_REG_ADDR(index), \ ADC_STM32_IRQ_FUNC(index) \ - .pclken = pclken_##index, \ - .pclk_len = DT_INST_NUM_CLOCKS(index), \ + .pclken = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(index, adcx, bus), \ + .enr = DT_INST_CLOCKS_CELL_BY_NAME(index, adcx, bits)}, \ + COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(index, adc_ker), \ + (.pclken_ker = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(index, adc_ker, bus), \ + .enr = DT_INST_CLOCKS_CELL_BY_NAME(index, adc_ker, bits)}, \ + .has_pclken_ker = true,), \ + (.has_pclken_ker = false,)) \ + COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(index, adc_pre), \ + (.pclken_pre = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(index, adc_pre, bus), \ + .enr = DT_INST_CLOCKS_CELL_BY_NAME(index, adc_pre, bits)}, \ + .has_pclken_pre = true,), \ + (.has_pclken_pre = false,)) \ .clk_prescaler = ADC_STM32_DT_PRESC(index), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ .differential_channels_used = (ANY_CHILD_NODE_IS_DIFFERENTIAL(index) > 0), \ diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 2ec1e4a3f8be2..f8ffac6ebecca 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -1142,15 +1142,6 @@ int stm32_clock_control_init(const struct device *dev) #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler) LL_RCC_SetAHB4Prescaler(ahb_prescaler(STM32_AHB4_PRESCALER)); #endif -#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc_prescaler) - LL_RCC_SetADCClockSource(adc12_prescaler(STM32_ADC_PRESCALER)); -#endif -#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc12_prescaler) - LL_RCC_SetADCClockSource(adc12_prescaler(STM32_ADC12_PRESCALER)); -#endif -#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc34_prescaler) - LL_RCC_SetADCClockSource(adc34_prescaler(STM32_ADC34_PRESCALER)); -#endif #if defined(RCC_DCKCFGR_TIMPRE) || defined(RCC_DCKCFGR1_TIMPRE) if (IS_ENABLED(STM32_TIMER_PRESCALER)) { LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_FOUR_TIMES); diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi index 5941dace1b751..aba15487ce46d 100644 --- a/dts/arm/st/c0/stm32c0.dtsi +++ b/dts/arm/st/c0/stm32c0.dtsi @@ -459,6 +459,7 @@ compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; + clock-names = "adcx"; interrupts = <12 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <12 0>; #io-channel-cells = <1>; resolutions = ; reg = <0x40021000 0x400>; @@ -394,6 +394,7 @@ compatible = "st,stm32f1-adc", "st,stm32-adc"; reg = <0x40012400 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi index cab9915dc640a..c2fbd01ab02ad 100644 --- a/dts/arm/st/f1/stm32f103Xc.dtsi +++ b/dts/arm/st/f1/stm32f103Xc.dtsi @@ -131,6 +131,7 @@ compatible = "st,stm32-adc"; reg = <0x40012800 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 10)>; + clock-names = "adcx"; /* Shares vector with ADC1 */ interrupts = <18 0>; #io-channel-cells = <1>; @@ -146,6 +147,7 @@ compatible = "st,stm32-adc"; reg = <0x40013c00 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 15)>; + clock-names = "adcx"; interrupts = <47 0>; #io-channel-cells = <1>; resolutions = ; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index 1cdf6ad01b41e..6672c8cddd69c 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -370,6 +370,7 @@ compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 8)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; reg = <0x40021000 0x400>; diff --git a/dts/arm/st/f3/stm32f302.dtsi b/dts/arm/st/f3/stm32f302.dtsi index ca766f72d1ac8..eb0c84bf470b3 100644 --- a/dts/arm/st/f3/stm32f302.dtsi +++ b/dts/arm/st/f3/stm32f302.dtsi @@ -111,6 +111,7 @@ compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 28)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 28)>; + clock-names = "adcx"; interrupts = <18 0>; vref-mv = <3000>; #io-channel-cells = <1>; @@ -165,6 +166,7 @@ compatible = "st,stm32-adc"; reg = <0x50000100 0x4c>; clocks = <&rcc STM32_CLOCK(AHB1, 28)>; + clock-names = "adcx"; interrupts = <18 0>; vref-mv = <3000>; #io-channel-cells = <1>; diff --git a/dts/arm/st/f3/stm32f334.dtsi b/dts/arm/st/f3/stm32f334.dtsi index 8b69016d5f4d5..9dca41871ec8e 100644 --- a/dts/arm/st/f3/stm32f334.dtsi +++ b/dts/arm/st/f3/stm32f334.dtsi @@ -86,6 +86,7 @@ compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 28)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = #include +#include #include / { soc { compatible = "st,stm32f373", "st,stm32f3", "simple-bus"; - rcc: rcc@40021000 { - /* - * Use the STM32F1 compatible that define the same ADC - * prescaler in the RCC register - */ - compatible = "st,stm32f1-rcc"; - }; - pinctrl: pin-controller@48000000 { gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; @@ -254,6 +247,7 @@ compatible = "st,stm32f1-adc", "st,stm32-adc"; reg = <0x40012400 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index 1018c1eb74c71..20a019bf8ea2f 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -555,6 +555,7 @@ compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 8)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 10)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 10)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 22)>; dmas = <&dma2 1 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS) 0>; + STM32_DMA_16BITS) 0>; status = "disabled"; }; @@ -189,7 +191,7 @@ reg = <0x40015824 0x20>; clocks = <&rcc STM32_CLOCK(APB2, 22)>; dmas = <&dma2 5 0 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS) 0>; + STM32_DMA_16BITS) 0>; status = "disabled"; }; }; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index b203b93271127..7f8bc1744ce1d 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -812,6 +812,7 @@ compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x50>; clocks = <&rcc STM32_CLOCK(APB2, 8)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 10)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; + clock-names = "adcx"; interrupts = <12 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 21)>; dmas = <&dma1 1 108 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS)>; + STM32_DMA_16BITS)>; status = "disabled"; }; @@ -734,7 +736,7 @@ reg = <0x40015424 0x20>; clocks = <&rcc STM32_CLOCK(APB2, 21)>; dmas = <&dma1 2 109 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS)>; + STM32_DMA_16BITS)>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g473.dtsi b/dts/arm/st/g4/stm32g473.dtsi index f3faa547a86e4..2217c095c121d 100644 --- a/dts/arm/st/g4/stm32g473.dtsi +++ b/dts/arm/st/g4/stm32g473.dtsi @@ -39,6 +39,7 @@ compatible = "st,stm32-adc"; reg = <0x50000500 0x100>; clocks = <&rcc STM32_CLOCK(AHB2, 14)>; + clock-names = "adcx"; interrupts = <61 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 14)>; + clock-names = "adcx"; interrupts = <62 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 14)>; + clock-names = "adcx"; interrupts = <47 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 10)>; + clock-names = "adcx"; interrupts = <37 0>; vref-mv = <3300>; #io-channel-cells = <1>; @@ -549,7 +550,6 @@ status = "disabled"; }; - gpdma1: dma@40020000 { compatible = "st,stm32u5-dma"; #dma-cells = <3>; @@ -582,9 +582,9 @@ clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>, + STM32_DMA_PRIORITY_HIGH)>, <&gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>; + STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <55 3>; status = "disabled"; @@ -598,9 +598,9 @@ clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>, + STM32_DMA_PRIORITY_HIGH)>, <&gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>; + STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <56 3>; status = "disabled"; @@ -614,9 +614,9 @@ clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>, + STM32_DMA_PRIORITY_HIGH)>, <&gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | - STM32_DMA_PRIORITY_HIGH)>; + STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <57 3>; status = "disabled"; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index 3e8ff990e9728..cba3c73e15bf4 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -297,6 +297,7 @@ compatible = "st,stm32-adc"; reg = <0x42028100 0x400>; clocks = <&rcc STM32_CLOCK(AHB2, 10)>; + clock-names = "adcx"; interrupts = <69 0>; vref-mv = <3300>; #io-channel-cells = <1>; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index a4549f6ba024f..120ebca517589 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -914,6 +914,7 @@ compatible = "st,stm32-adc"; reg = <0x40022000 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB4, 24)>; + clock-names = "adcx"; interrupts = <127 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <38 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <38 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <12 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>, <&rcc STM32_SRC_HSI NO_SEL>; + clock-names = "adcx", "adc_ker"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <47 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = , <&rcc STM32_SRC_PLLSAI1_P SAI1_SEL(0)>; dmas = <&dma1 1 37 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS)>; + STM32_DMA_16BITS)>; status = "disabled"; }; @@ -810,7 +812,7 @@ clocks = <&rcc STM32_CLOCK(APB2, 21)>, <&rcc STM32_SRC_PLLSAI1_P SAI1_SEL(0)>; dmas = <&dma1 2 38 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | - STM32_DMA_16BITS)>; + STM32_DMA_16BITS)>; status = "disabled"; }; }; diff --git a/dts/arm/st/n6/stm32n6.dtsi b/dts/arm/st/n6/stm32n6.dtsi index e3df2576ccfc8..efb6d2a71150d 100644 --- a/dts/arm/st/n6/stm32n6.dtsi +++ b/dts/arm/st/n6/stm32n6.dtsi @@ -437,6 +437,7 @@ compatible = "st,stm32n6-adc", "st,stm32-adc"; reg = <0x50022000 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <46 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB1, 5)>; + clock-names = "adcx"; interrupts = <46 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; + clock-names = "adcx"; interrupts = <12 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 10)>; + clock-names = "adcx"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 10)>; + clock-names = "adcx"; interrupts = <113 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB3, 5)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; interrupts = <113 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = ; - clocks = <&rcc STM32_CLOCK(AHB2, 10)>; + clocks = <&rcc STM32_CLOCK(AHB2, 10)>, + <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + clock-names = "adcx", "adc_ker"; interrupts = <37 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB2, 13)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(AHB4, 5)>, <&rcc STM32_SRC_HCLK1 ADC_SEL(0)>; + clock-names = "adcx", "adc_ker"; interrupts = <65 0>; #io-channel-cells = <1>; resolutions = ; clocks = <&rcc STM32_CLOCK(APB2, 9)>; + clock-names = "adcx"; interrupts = <18 0>; #io-channel-cells = <1>; resolutions = +# Copyright (c) 2025 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 description: STM32 ADC @@ -15,6 +16,22 @@ properties: clocks: required: true + clock-names: + required: true + enum: + - "adcx" + - "adc_ker" + - "adc_pre" + description: | + Expected names are the following: + - "adcx" for the enabling the register clock (mandatory) + - "adc_ker" for configuring the kernel clock (if applicable) + - "adc_pre" for configuring the prescaler (if applicable) + Kernel clock and prescaler may be shared between several ADC instances. + In that case, the same kernel clock/prescaler Device Tree configuration + must be used on all instances that share the kernel clock/prescaler + to avoid conflicts. + interrupts: required: true @@ -32,7 +49,7 @@ properties: - "SYNC": derived from the bus clock. - "ASYNC" : independent and asynchronous with the bus clock One of the two values may not apply to some series. Refer to the RefMan. - If an asynchronous clock is selected, a domain clock in the clock property + If an asynchronous clock is selected, a kernel clock in the "clocks" property has to be defined explicitly. st,adc-prescaler: @@ -57,9 +74,8 @@ properties: st,adc-clock-source. Some of the values may not apply to some series, and may depend on the selected clock source. Refer to the RefMan. - On STM32F3x (except STM32F37x), this configures only the synchronous - prescaler (see properties adcXX-prescaler in st,stm32f3-rcc bindings to - set asynchronous prescaler). + On STM32F3x, this configures only the synchronous prescaler + (use the "clocks" property to set asynchronous prescaler). vref-mv: type: int diff --git a/dts/bindings/clock/st,stm32f1-rcc.yaml b/dts/bindings/clock/st,stm32f1-rcc.yaml deleted file mode 100644 index f013d8daa093c..0000000000000 --- a/dts/bindings/clock/st,stm32f1-rcc.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -description: | - STM32F1/F3/7x RCC (Reset and Clock controller). - - Adds the ADC prescaler to the standard generic STM32 RCC. - For more description confere st,stm32-rcc.yaml - -compatible: "st,stm32f1-rcc" - -include: st,stm32-rcc.yaml - -properties: - adc-prescaler: - type: int - enum: - - 2 - - 4 - - 6 - - 8 - description: | - ADC prescaler. Defines ADC core clock frequency - based on APB2 frequency input. diff --git a/dts/bindings/clock/st,stm32f3-rcc.yaml b/dts/bindings/clock/st,stm32f3-rcc.yaml deleted file mode 100644 index 6db97343e9886..0000000000000 --- a/dts/bindings/clock/st,stm32f3-rcc.yaml +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -description: | - STM32F3 RCC (Reset and Clock controller). - - Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC. - For more description confere st,stm32-rcc.yaml - -compatible: "st,stm32f3-rcc" - -include: st,stm32-rcc.yaml - -properties: - adc12-prescaler: - type: int - enum: - - 0 # Synchronous mode - - 1 # not divided - - 2 - - 4 - - 6 - - 8 - - 10 - - 12 - - 16 - - 32 - - 64 - - 128 - - 256 - description: | - ADC 1 and 2 prescaler - - 0: Disables the clock so the ADC can use AHB clock (synchronous mode) - - Other values n: The ADC can use the PLL clock divided by n - On STM32F37x, only 2/4/6/8 are allowed. - - adc34-prescaler: - type: int - enum: - - 0 # Synchronous mode - - 1 # not divided - - 2 - - 4 - - 6 - - 8 - - 10 - - 12 - - 16 - - 32 - - 64 - - 128 - - 256 - description: | - ADC 3 and 4 prescaler - - 0: Disables the clock so the ADC can use AHB clock (synchronous mode) - - Other values n: The ADC can use the PLL clock divided by n - Check RefMan for availability. diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index 58a033a15676e..0d79af05597f5 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -107,10 +107,6 @@ #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER #endif -#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler) -#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler) -#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler) - #define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre) /** STM2H7RS specific RCC dividers */ @@ -861,7 +857,7 @@ struct stm32_pclken { * @param clock Clock bit field value. */ #define STM32_DT_CLKSEL_MASK_GET(clock) \ - (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK) + BIT_MASK((((clock) >> STM32_DT_CLKSEL_WIDTH_SHIFT) & STM32_DT_CLKSEL_WIDTH_MASK) + 1) /** * @brief Obtain value field from clock source selection configuration. diff --git a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h index 5992fee999b80..a7b0e307c9cc8 100644 --- a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h +++ b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h @@ -23,30 +23,31 @@ /** Helper macros to pack RCC clock source selection register info in the DT */ #define STM32_DT_CLKSEL_REG_MASK 0xFFFFU #define STM32_DT_CLKSEL_REG_SHIFT 0U -#define STM32_DT_CLKSEL_SHIFT_MASK 0x3FU +#define STM32_DT_CLKSEL_SHIFT_MASK 0x1FU #define STM32_DT_CLKSEL_SHIFT_SHIFT 16U -#define STM32_DT_CLKSEL_MASK_MASK 0x1FU -#define STM32_DT_CLKSEL_MASK_SHIFT 22U -#define STM32_DT_CLKSEL_VAL_MASK 0x1FU -#define STM32_DT_CLKSEL_VAL_SHIFT 27U +#define STM32_DT_CLKSEL_WIDTH_MASK 0x3U +#define STM32_DT_CLKSEL_WIDTH_SHIFT 21U +#define STM32_DT_CLKSEL_VAL_MASK 0xFFU +#define STM32_DT_CLKSEL_VAL_SHIFT 24U /** * @brief Pack STM32 source clock selection RCC register bit fields for the DT * * @param val Clock configuration field value - * @param mask Mask of register field in RCC register - * @param shift Position of field within RCC register (= field LSB's index) + * @param msb Field MSB's index + * @param lsb Field LSB's index * @param reg Offset to target clock configuration register in RCC * + * @note Internally, the data are stored as follows * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ] - * @note 'shift' range: 0~63 [ 16 : 21 ] - * @note 'mask' range: 0x00~0x1F [ 22 : 26 ] - * @note 'val' range: 0x00~0x1F [ 27 : 31 ] + * @note 'shift' range: 0~31 [ 16 : 20 ] + * @note 'width' range: 0~7 [ 21 : 23 ] Value encodes bit fields width minus 1 + * @note 'val' range: 0x00~0xFF [ 24 : 31 ] */ -#define STM32_DT_CLOCK_SELECT(val, mask, shift, reg) \ - ((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) | \ - (((shift) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) | \ - (((mask) & STM32_DT_CLKSEL_MASK_MASK) << STM32_DT_CLKSEL_MASK_SHIFT) | \ +#define STM32_DT_CLOCK_SELECT(val, msb, lsb, reg) \ + ((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) | \ + (((lsb) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) | \ + ((((msb) - (lsb)) & STM32_DT_CLKSEL_WIDTH_MASK) << STM32_DT_CLKSEL_WIDTH_SHIFT) | \ (((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT)) /** diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h index 8512b2655d39b..efdd3f200e777 100644 --- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -46,21 +46,21 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG) /** CCIPR2 devices */ -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR2_REG) /** CSR1 devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CSR1_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 28, CFGR1_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 16, CFGR1_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 20, CFGR1_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 16, CFGR1_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 23, 20, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 31, 28, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32f0_clock.h b/include/zephyr/dt-bindings/clock/stm32f0_clock.h index 4f815bacd686f..cc34d18c0ae5b 100644 --- a/include/zephyr/dt-bindings/clock/stm32f0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f0_clock.h @@ -40,17 +40,17 @@ /** @brief Device domain clocks selection helpers */ /** CFGR3 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) -#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG) -#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CFGR3_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, CFGR3_REG) +#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CFGR3_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 7, CFGR3_REG) +#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CFGR3_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CFGR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h index d7410b8b50e8d..f17c9e32a2ab0 100644 --- a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h @@ -19,7 +19,7 @@ /** CFGR1 devices */ #undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) /* No MCO prescaler support on STM32F1 series. */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/include/zephyr/dt-bindings/clock/stm32f1_clock.h index d8b1f140321fc..9b5038311f5f3 100644 --- a/include/zephyr/dt-bindings/clock/stm32f1_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f1_clock.h @@ -38,14 +38,22 @@ #define BDCR_REG 0x20 /** @brief Device domain clocks selection helpers */ +/** CFGR1 devices */ +#define ADC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CFGR1_REG) /** CFGR2 devices */ -#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG) -#define I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG) +#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 17, CFGR2_REG) +#define I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 18, CFGR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR1_REG) /* No MCO prescaler support on STM32F1 series. */ +/* ADC prescaler division factor */ +#define ADC_PRE_DIV_2 0 +#define ADC_PRE_DIV_4 1 +#define ADC_PRE_DIV_6 2 +#define ADC_PRE_DIV_8 3 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f37x_clock.h b/include/zephyr/dt-bindings/clock/stm32f37x_clock.h new file mode 100644 index 0000000000000..13dcd15891eed --- /dev/null +++ b/include/zephyr/dt-bindings/clock/stm32f37x_clock.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F37X_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F37X_CLOCK_H_ + +#include "stm32f3_clock.h" + +/* On STM32F37x, the ADC prescaler is located in CFGR1 and the prescaler values are more limited */ +#undef ADC12_PRE +#undef ADC34_PRE +#undef ADC_PRE_DISABLED +#undef ADC_PRE_DIV_1 +#undef ADC_PRE_DIV_2 +#undef ADC_PRE_DIV_4 +#undef ADC_PRE_DIV_6 +#undef ADC_PRE_DIV_8 +#undef ADC_PRE_DIV_10 +#undef ADC_PRE_DIV_12 +#undef ADC_PRE_DIV_16 +#undef ADC_PRE_DIV_32 +#undef ADC_PRE_DIV_64 +#undef ADC_PRE_DIV_128 +#undef ADC_PRE_DIV_256 + +/** @brief Device domain clocks selection helpers */ +/** CFGR devices */ +#define ADC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CFGR_REG) + +/* ADC prescaler division factor for STM32F37x */ +#define ADC_PRE_DIV_2 0 +#define ADC_PRE_DIV_4 1 +#define ADC_PRE_DIV_6 2 +#define ADC_PRE_DIV_8 3 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F37X_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f3_clock.h b/include/zephyr/dt-bindings/clock/stm32f3_clock.h index 4723c3b65e90c..56fdf5b2a0448 100644 --- a/include/zephyr/dt-bindings/clock/stm32f3_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f3_clock.h @@ -36,6 +36,7 @@ /** @brief RCC_CFGRx register offset */ #define CFGR_REG 0x04 +#define CFGR2_REG 0x2C #define CFGR3_REG 0x30 /** @brief RCC_BDCR register offset */ @@ -43,27 +44,45 @@ /** @brief Device domain clocks selection helpers) */ /** CFGR devices */ -#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) +#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR_REG) +/** CFGR2 devices */ +#define ADC12_PRE(val) STM32_DT_CLOCK_SELECT((val), 8, 4, CFGR2_REG) +#define ADC34_PRE(val) STM32_DT_CLOCK_SELECT((val), 13, 9, CFGR2_REG) /** CFGR3 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 5, CFGR3_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) -#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CFGR3_REG) -#define TIM8_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 9, CFGR3_REG) -#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CFGR3_REG) -#define TIM16_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CFGR3_REG) -#define TIM17_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR3_REG) -#define TIM20_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CFGR3_REG) -#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) -#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CFGR3_REG) -#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR3_REG) -#define TIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CFGR3_REG) -#define TIM3_4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 25, CFGR3_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CFGR3_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, CFGR3_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 5, CFGR3_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CFGR3_REG) +#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, CFGR3_REG) +#define TIM8_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 9, CFGR3_REG) +#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 10, CFGR3_REG) +#define TIM16_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CFGR3_REG) +#define TIM17_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR3_REG) +#define TIM20_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CFGR3_REG) +#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CFGR3_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CFGR3_REG) +#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CFGR3_REG) +#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR3_REG) +#define TIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CFGR3_REG) +#define TIM3_4_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 25, CFGR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) + +/* ADC prescaler division factor for all F3 except F37x */ +#define ADC_PRE_DISABLED 0x0 +#define ADC_PRE_DIV_1 0x10 +#define ADC_PRE_DIV_2 0x11 +#define ADC_PRE_DIV_4 0x12 +#define ADC_PRE_DIV_6 0x13 +#define ADC_PRE_DIV_8 0x14 +#define ADC_PRE_DIV_10 0x15 +#define ADC_PRE_DIV_12 0x16 +#define ADC_PRE_DIV_16 0x17 +#define ADC_PRE_DIV_32 0x18 +#define ADC_PRE_DIV_64 0x19 +#define ADC_PRE_DIV_128 0x1A +#define ADC_PRE_DIV_256 0x1B #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f410_clock.h b/include/zephyr/dt-bindings/clock/stm32f410_clock.h index eb7a39c3fb7c3..1894e1cbe3db1 100644 --- a/include/zephyr/dt-bindings/clock/stm32f410_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f410_clock.h @@ -14,19 +14,19 @@ /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ -#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG) -#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG) -#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG) -#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG) -#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 25, DCKCFGR_REG) -#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 27, DCKCFGR_REG) -#define CKDFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, DCKCFGR_REG) +#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, DCKCFGR_REG) +#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, DCKCFGR_REG) +#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, DCKCFGR_REG) +#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, DCKCFGR_REG) +#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 25, DCKCFGR_REG) +#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 27, DCKCFGR_REG) +#define CKDFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, DCKCFGR_REG) /** DCKCFGR2 devices */ -#define I2CFMP1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG) -#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG) -#define SDIO_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, DCKCFGR2_REG) +#define I2CFMP1_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, DCKCFGR2_REG) +#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 27, DCKCFGR2_REG) +#define SDIO_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, DCKCFGR2_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, DCKCFGR2_REG) /* F4 generic I2S_SEL is not compatible with F410 devices */ #ifdef I2S_SEL diff --git a/include/zephyr/dt-bindings/clock/stm32f427_clock.h b/include/zephyr/dt-bindings/clock/stm32f427_clock.h index 4fb2f72325f6f..e4f520a805cb1 100644 --- a/include/zephyr/dt-bindings/clock/stm32f427_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f427_clock.h @@ -13,12 +13,12 @@ /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ -#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG) -#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG) -#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG) -#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG) -#define CLK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR_REG) -#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR_REG) +#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, DCKCFGR_REG) +#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, DCKCFGR_REG) +#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, DCKCFGR_REG) +#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, DCKCFGR_REG) +#define CLK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 27, DCKCFGR_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, DCKCFGR_REG) +#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 29, DCKCFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/include/zephyr/dt-bindings/clock/stm32f4_clock.h index b58553dcdca88..5f09416e0a081 100644 --- a/include/zephyr/dt-bindings/clock/stm32f4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f4_clock.h @@ -60,13 +60,13 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ -#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 21, CFGR_REG) +#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 23, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 29, 27, CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CFGR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/include/zephyr/dt-bindings/clock/stm32f7_clock.h index 9b3cf3508fa38..5a441af624add 100644 --- a/include/zephyr/dt-bindings/clock/stm32f7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f7_clock.h @@ -57,11 +57,11 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ -#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 21, CFGR_REG) +#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 23, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 29, 27, CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CFGR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 @@ -71,7 +71,7 @@ #define MCO_PRE_DIV_5 7 /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** @brief RCC_DKCFGR register offset */ #define DCKCFGR1_REG 0x8C @@ -79,23 +79,23 @@ /** @brief Dedicated clocks configuration register selection helpers */ /** DKCFGR2 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, DCKCFGR2_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, DCKCFGR2_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, DCKCFGR2_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG) -#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, DCKCFGR2_REG) -#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, DCKCFGR2_REG) -#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, DCKCFGR2_REG) -#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, DCKCFGR2_REG) -#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, DCKCFGR2_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, DCKCFGR2_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, DCKCFGR2_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR2_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, DCKCFGR2_REG) -#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, DCKCFGR2_REG) -#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG) -#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG) -#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR2_REG) -#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 30, DCKCFGR2_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, DCKCFGR2_REG) +#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, DCKCFGR2_REG) +#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, DCKCFGR2_REG) +#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, DCKCFGR2_REG) +#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, DCKCFGR2_REG) +#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, DCKCFGR2_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, DCKCFGR2_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, DCKCFGR2_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, DCKCFGR2_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, DCKCFGR2_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, DCKCFGR2_REG) +#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 26, DCKCFGR2_REG) +#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 27, DCKCFGR2_REG) +#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, DCKCFGR2_REG) +#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 29, DCKCFGR2_REG) +#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 30, DCKCFGR2_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32g0_clock.h b/include/zephyr/dt-bindings/clock/stm32g0_clock.h index d14952b63cfa6..1405e7e5c64e2 100644 --- a/include/zephyr/dt-bindings/clock/stm32g0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32g0_clock.h @@ -48,32 +48,32 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 24, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 28, CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 16, CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 20, CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 16, CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 23, 20, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 31, 28, CFGR_REG) /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) -#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG) -#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG) -#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR_REG) +#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR_REG) +#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 22, CCIPR_REG) +#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG) /** CCIPR2 devices */ -#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) +#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) #define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG) -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR2_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32g4_clock.h b/include/zephyr/dt-bindings/clock/stm32g4_clock.h index 4e66ba4e90916..e0a156ba2a1c7 100644 --- a/include/zephyr/dt-bindings/clock/stm32g4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32g4_clock.h @@ -50,26 +50,26 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) -#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) -#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define I2S23_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG) -#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) -#define ADC34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR_REG) +#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR_REG) +#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define I2S23_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR_REG) +#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) +#define ADC34_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG) /** CCIPR2 devices */ -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) -#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) +#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32h5_clock.h b/include/zephyr/dt-bindings/clock/stm32h5_clock.h index 890ca069e8609..3d3a0611d22b6 100644 --- a/include/zephyr/dt-bindings/clock/stm32h5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h5_clock.h @@ -68,67 +68,67 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG) -#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR1_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG) -#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR1_REG) -#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR1_REG) -#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR1_REG) -#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 18, CCIPR1_REG) -#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, CCIPR1_REG) -#define USART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR1_REG) -#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 27, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR1_REG) +#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, CCIPR1_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, CCIPR1_REG) +#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 9, CCIPR1_REG) +#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR1_REG) +#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 15, CCIPR1_REG) +#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 18, CCIPR1_REG) +#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 21, CCIPR1_REG) +#define USART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR1_REG) +#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 27, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, CCIPR1_REG) /** CCIPR2 devices */ -#define USART11_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG) -#define USART12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR2_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR2_REG) -#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG) -#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR2_REG) -#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR2_REG) -#define LPTIM6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR2_REG) +#define USART11_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR2_REG) +#define USART12_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR2_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR2_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR2_REG) +#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR2_REG) +#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR2_REG) +#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR2_REG) +#define LPTIM6_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CCIPR2_REG) /** CCIPR3 devices */ -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR3_REG) -#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG) -#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR3_REG) -#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG) -#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR2_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR3_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR3_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, CCIPR3_REG) +#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 9, CCIPR3_REG) +#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR3_REG) +#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 15, CCIPR2_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR3_REG) /** CCIPR4 devices */ -#define OCTOSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR4_REG) +#define OCTOSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR4_REG) #define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR4_REG) -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR4_REG) -#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR4_REG) -#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CCIPR4_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR4_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR4_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR4_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR4_REG) -#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR4_REG) +#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR4_REG) +#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 7, CCIPR4_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR4_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR4_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR4_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR4_REG) +#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR4_REG) /** CCIPR5 devices */ -#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG) -#define DAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR5_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR5_REG) -#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR5_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR5_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 19, CCIPR5_REG) -#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR5_REG) +#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR5_REG) +#define DAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR5_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR5_REG) +#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR5_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR5_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR5_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 19, CCIPR5_REG) +#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR5_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR1_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR1_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 21, 18, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 22, CFGR1_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 28, 25, CFGR1_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 1 diff --git a/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/include/zephyr/dt-bindings/clock/stm32h7_clock.h index ae8df9b9a0965..652f03484a25b 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7_clock.h @@ -75,46 +75,46 @@ /** @brief Device domain clocks selection helpers (RM0399.pdf) */ /** D1CCIPR devices */ -#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG) -#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) -#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, D1CCIPR_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, D1CCIPR_REG) -#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG) +#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, D1CCIPR_REG) +#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, D1CCIPR_REG) +#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, D1CCIPR_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, D1CCIPR_REG) +#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D1CCIPR_REG) /* Device domain clocks selection helpers (RM0468.pdf) */ -#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) +#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, D1CCIPR_REG) /** D2CCIP1R devices */ -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP1R_REG) -#define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, D2CCIP1R_REG) -#define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D2CCIP1R_REG) -#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIP1R_REG) -#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP1R_REG) -#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, D2CCIP1R_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D2CCIP1R_REG) -#define SWP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, D2CCIP1R_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D2CCIP1R_REG) +#define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, D2CCIP1R_REG) +#define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, D2CCIP1R_REG) +#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, D2CCIP1R_REG) +#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, D2CCIP1R_REG) +#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, D2CCIP1R_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D2CCIP1R_REG) +#define SWP_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, D2CCIP1R_REG) /** D2CCIP2R devices */ -#define USART2345678_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP2R_REG) -#define USART16_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, D2CCIP2R_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIP2R_REG) -#define I2C123_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIP2R_REG) -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP2R_REG) -#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIP2R_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D2CCIP2R_REG) +#define USART2345678_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D2CCIP2R_REG) +#define USART16_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, D2CCIP2R_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, D2CCIP2R_REG) +#define I2C123_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, D2CCIP2R_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, D2CCIP2R_REG) +#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, D2CCIP2R_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, D2CCIP2R_REG) /** D3CCIPR devices */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D3CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 10, D3CCIPR_REG) -#define LPTIM345_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 13, D3CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, D3CCIPR_REG) -#define SAI4A_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, D3CCIPR_REG) -#define SAI4B_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, D3CCIPR_REG) -#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D3CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D3CCIPR_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, D3CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 10, D3CCIPR_REG) +#define LPTIM345_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 13, D3CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, D3CCIPR_REG) +#define SAI4A_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 21, D3CCIPR_REG) +#define SAI4B_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, D3CCIPR_REG) +#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, D3CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 22, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 18, CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 21, 18, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 22, CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 28, 25, CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CFGR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 1 diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h index 06c5e1f392d2d..e9133f65457b2 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h @@ -78,44 +78,43 @@ /* TODO to be completed */ /** D1CCIPR devices */ -#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG) -#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) -#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG) -#define OTGFS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG) -#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG) +#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, D1CCIPR_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, D1CCIPR_REG) +#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, D1CCIPR_REG) +#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, D1CCIPR_REG) +#define OTGFS_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, D1CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, D1CCIPR_REG) +#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D1CCIPR_REG) /** D2CCIPR devices */ -#define USART234578_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIPR_REG) -#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D2CCIPR_REG) -#define I2C23_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG) -#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIPR_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIPR_REG) +#define USART234578_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D2CCIPR_REG) +#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, D2CCIPR_REG) +#define I2C23_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, D2CCIPR_REG) +#define I2C1_I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, D2CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, D2CCIPR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, D2CCIPR_REG) /** D3CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG) -#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D3CCIPR_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, D3CCIPR_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D3CCIPR_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, D3CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D3CCIPR_REG) +#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, D3CCIPR_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, D3CCIPR_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, D3CCIPR_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, D3CCIPR_REG) /** D4CCIPR devices */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D4CCIPR_REG) -#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D4CCIPR_REG) -#define LPTIM23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, D4CCIPR_REG) -#define LPTIM45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D4CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D4CCIPR_REG) +#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, D4CCIPR_REG) +#define LPTIM23_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, D4CCIPR_REG) +#define LPTIM45_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, D4CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 29, CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 25, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 21, 18, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 22, CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 28, 25, CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CFGR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 1 diff --git a/include/zephyr/dt-bindings/clock/stm32l0_clock.h b/include/zephyr/dt-bindings/clock/stm32l0_clock.h index 37ddc6481f2cb..f697fccd04ea9 100644 --- a/include/zephyr/dt-bindings/clock/stm32l0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l0_clock.h @@ -41,14 +41,14 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define HSI48_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define HSI48_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 26, CCIPR_REG) /** CSR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32l1_clock.h b/include/zephyr/dt-bindings/clock/stm32l1_clock.h index 3097c88c6e8e7..9b9bf4bbde593 100644 --- a/include/zephyr/dt-bindings/clock/stm32l1_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l1_clock.h @@ -32,6 +32,6 @@ /** @brief RCC_CSR register offset */ #define CSR_REG 0x34 -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h index cdef7de2b6426..d603418bc371e 100644 --- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h @@ -59,35 +59,35 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) -#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG) -#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) -#define SWPMI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 30, CCIPR_REG) -#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR_REG) +#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR_REG) +#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) +#define SWPMI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 30, CCIPR_REG) +#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, CCIPR_REG) /** CCIPR2 devices */ -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) -#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG) -#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG) -#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) -#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) +#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR2_REG) +#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 3, CCIPR2_REG) +#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR2_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG) +#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32l4plus_clock.h b/include/zephyr/dt-bindings/clock/stm32l4plus_clock.h index 03786d6981c9f..e7358ae7c0a64 100644 --- a/include/zephyr/dt-bindings/clock/stm32l4plus_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l4plus_clock.h @@ -17,6 +17,6 @@ /** CCIPR2 devices */ #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR2_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4PLUS_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32l5_clock.h b/include/zephyr/dt-bindings/clock/stm32l5_clock.h index 451f004b04085..ea6c03a393f12 100644 --- a/include/zephyr/dt-bindings/clock/stm32l5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l5_clock.h @@ -59,34 +59,34 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) -#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG) -#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR_REG) +#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR_REG) +#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) /** CCIPR2 devices */ -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) -#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG) -#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) -#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) +#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR2_REG) +#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 3, CCIPR2_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR2_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG) +#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32mp13_clock.h b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h index c3f0b8cd7ad23..66808ee0ddade 100644 --- a/include/zephyr/dt-bindings/clock/stm32mp13_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h @@ -75,10 +75,10 @@ #define SAESCKSELR_REG 0x668 /** MCO1CFGR / MCO2CFGR devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, MCO1CFGR_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 7, 4, MCO1CFGR_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, MCO2CFGR_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 7, 4, MCO2CFGR_REG) #define MCOX_ON BIT(12) @@ -115,41 +115,41 @@ #define MCO_PRE_DIV_15 14 #define MCO_PRE_DIV_16 15 -#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG) -#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG) -#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG) -#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG) -#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG) -#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG) -#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG) -#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG) -#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG) -#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG) -#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG) -#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG) -#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG) -#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG) -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG) -#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG) -#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG) -#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG) -#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG) -#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG) -#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG) -#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG) -#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG) -#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG) -#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG) -#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG) -#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG) -#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG) -#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG) -#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG) +#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, I2C12CKSELR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, I2C345CKSELR_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, I2C345CKSELR_REG) +#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, I2C345CKSELR_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI2S1CKSELR_REG) +#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI2S23CKSELR_REG) +#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI45CKSELR_REG) +#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, SPI45CKSELR_REG) +#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART12CKSELR_REG) +#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, UART12CKSELR_REG) +#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART35CKSELR_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART4CKSELR_REG) +#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART6CKSELR_REG) +#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART78CKSELR_REG) +#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM1CKSELR_REG) +#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM23CKSELR_REG) +#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, LPTIM23CKSELR_REG) +#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM45CKSELR_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SAI1CKSELR_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SAI2CKSELR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, FDCANCKSELR_REG) +#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, SPDIFCKSELR_REG) +#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, ADC12CKSELR_REG) +#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, ADC12CKSELR_REG) +#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SDMMC12CKSELR_REG) +#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, SDMMC12CKSELR_REG) +#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, ETH12CKSELR_REG) +#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, ETH12CKSELR_REG) +#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, USBCKSELR_REG) +#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, USBCKSELR_REG) +#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, QSPICKSELR_REG) +#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, FMCCKSELR_REG) +#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, RNG1CKSELR_REG) +#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, STGENCKSELR_REG) +#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, DCMIPPCKSELR_REG) +#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, SAESCKSELR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32n6_clock.h b/include/zephyr/dt-bindings/clock/stm32n6_clock.h index 6d243fa39e612..b32202716a107 100644 --- a/include/zephyr/dt-bindings/clock/stm32n6_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32n6_clock.h @@ -96,85 +96,91 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG) -#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG) -#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) +#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR1_REG) +#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR1_REG) +#define ADC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 8, CCIPR1_REG) +#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR1_REG) /** CCIPR2 devices */ -#define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) -#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) -#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG) -#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG) -#define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG) +#define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) +#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG) +#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR2_REG) +#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG) +#define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR2_REG) /** CCIPR3 devices */ -#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) -#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG) +#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR3_REG) /** CCIPR4 devices */ -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR4_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR4_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR4_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR4_REG) -#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR4_REG) -#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR4_REG) -#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR4_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR4_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR4_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR4_REG) +#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR4_REG) +#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR4_REG) +#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR4_REG) /** CCIPR5 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR5_REG) -#define MDF1SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR5_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR5_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR5_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR5_REG) +#define MDF1SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR5_REG) /** CCIPR6 devices */ -#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR6_REG) -#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR6_REG) -#define XSPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR6_REG) -#define OTGPHY1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR6_REG) -#define OTGPHY1CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR6_REG) -#define OTGPHY2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR6_REG) -#define OTGPHY2CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR6_REG) +#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR6_REG) +#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR6_REG) +#define XSPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR6_REG) +#define OTGPHY1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR6_REG) +#define OTGPHY1CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR6_REG) +#define OTGPHY2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR6_REG) +#define OTGPHY2CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR6_REG) /** CCIPR7 devices */ -#define PER_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR7_REG) -#define PSSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR7_REG) -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR7_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR7_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR7_REG) +#define PER_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR7_REG) +#define PSSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR7_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR7_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR7_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR7_REG) /** CCIPR8 devices */ -#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR8_REG) -#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR8_REG) +#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR8_REG) +#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR8_REG) /** CCIPR9 devices */ -#define SPDIFRX1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR9_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR9_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR9_REG) -#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR9_REG) -#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR9_REG) -#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR9_REG) -#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR9_REG) +#define SPDIFRX1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR9_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR9_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR9_REG) +#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR9_REG) +#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR9_REG) +#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR9_REG) +#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR9_REG) /** CCIPR12 devices */ -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR12_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR12_REG) -#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR12_REG) -#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR12_REG) -#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR12_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR12_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR12_REG) +#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR12_REG) +#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR12_REG) +#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR12_REG) /** CCIPR13 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR13_REG) -#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR13_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR13_REG) -#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR13_REG) -#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR13_REG) -#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR13_REG) -#define UART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR13_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR13_REG) +#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR13_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR13_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR13_REG) +#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR13_REG) +#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 20, CCIPR13_REG) +#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, CCIPR13_REG) +#define UART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CCIPR13_REG) /** CCIPR14 devices */ -#define UART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR14_REG) -#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR14_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR14_REG) +#define UART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR14_REG) +#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR14_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR14_REG) /** @brief RCC_ICxCFGR register offset (RM0486.pdf) */ #define ICxCFGR_REG(ic) (0xC4 + ((ic) - 1) * 4) /** @brief Divider ICx source selection */ -#define ICx_PLLy_SEL(ic, pll) STM32_DT_CLOCK_SELECT((pll) - 1, 3, 28, ICxCFGR_REG(ic)) +#define ICx_PLLy_SEL(ic, pll) STM32_DT_CLOCK_SELECT((pll) - 1, 29, 28, ICxCFGR_REG(ic)) /** @brief RCC_CFGR1 register offset (RM0486.pdf) */ #define CFGR1_REG 0x20 /** @brief CPU clock switch selection */ -#define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG) +#define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CFGR1_REG) + +/* ADC prescaler division factor helper */ +#define ADC_PRE_DIV(pres) ((pres - 1) & 0xFFU) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32u0_clock.h b/include/zephyr/dt-bindings/clock/stm32u0_clock.h index d4d135d72c727..962f550f60130 100644 --- a/include/zephyr/dt-bindings/clock/stm32u0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32u0_clock.h @@ -45,21 +45,21 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define LPUART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) -#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG) -#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 25, CCIPR_REG) -#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) +#define LPUART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR_REG) +#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR_REG) +#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 25, CCIPR_REG) +#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32u3_clock.h b/include/zephyr/dt-bindings/clock/stm32u3_clock.h index 667e6069407b9..bba29272cb595 100644 --- a/include/zephyr/dt-bindings/clock/stm32u3_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32u3_clock.h @@ -54,41 +54,42 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR1_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CCIPR1_REG) -#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR1_REG) -#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CCIPR1_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CCIPR1_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR1_REG) -#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR1_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR1_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR1_REG) -#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) -#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR1_REG) -#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG) -#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0, 0, CCIPR1_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR1_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, CCIPR1_REG) +#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR1_REG) +#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR1_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 10, CCIPR1_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR1_REG) +#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR1_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR1_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR1_REG) +#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG) +#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR1_REG) +#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG) +#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG) /** CCIPR2 devices */ -#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) -#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR2_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG) -#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR2_REG) -#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 19, CCIPR2_REG) -#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG) +#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG) +#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG) +#define ADCDAC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR2_REG) +#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG) +#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 19, CCIPR2_REG) +#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG) /** CCIPR3 devices */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR3_REG) -#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR3_REG) +#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 @@ -100,4 +101,16 @@ #define MCO_PRE_DIV_64 6 #define MCO_PRE_DIV_128 7 +/* ADC/DAC prescaler division factor */ +#define ADCDAC_PRE_DIV_1 0x0 +#define ADCDAC_PRE_DIV_2 0x1 +#define ADCDAC_PRE_DIV_4 0x8 +#define ADCDAC_PRE_DIV_8 0x9 +#define ADCDAC_PRE_DIV_16 0xA +#define ADCDAC_PRE_DIV_32 0xB +#define ADCDAC_PRE_DIV_64 0xC +#define ADCDAC_PRE_DIV_128 0xD +#define ADCDAC_PRE_DIV_256 0xE +#define ADCDAC_PRE_DIV_512 0xF + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/include/zephyr/dt-bindings/clock/stm32u5_clock.h index 6a68e6ae8a686..ecaa4305236f3 100644 --- a/include/zephyr/dt-bindings/clock/stm32u5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32u5_clock.h @@ -69,51 +69,51 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG) -#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR1_REG) -#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR1_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) -#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) -#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR1_REG) -#define ICKLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR1_REG) +#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG) +#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR1_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR1_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR1_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR1_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR1_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR1_REG) +#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG) +#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR1_REG) +#define ICKLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG) /** CCIPR2 devices */ -#define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG) +#define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR2_REG) #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) -#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) -#define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) -#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) -#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG) -#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG) -#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG) -#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) -#define HSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR2_REG) -#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR2_REG) -#define I2C6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR2_REG) -#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR2_REG) +#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR2_REG) +#define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG) +#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG) +#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR2_REG) +#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR2_REG) +#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 18, CCIPR2_REG) +#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG) +#define HSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR2_REG) +#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR2_REG) +#define I2C6_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR2_REG) +#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR2_REG) /** CCIPR3 devices */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG) -#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG) -#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG) -#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG) -#define DAC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR3_REG) -#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR3_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 3, CCIPR3_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG) +#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG) +#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR3_REG) +#define DAC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR3_REG) +#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, CCIPR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32wb0_clock.h b/include/zephyr/dt-bindings/clock/stm32wb0_clock.h index d3b96b49ca4f5..d51e7b473c436 100644 --- a/include/zephyr/dt-bindings/clock/stm32wb0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32wb0_clock.h @@ -36,10 +36,10 @@ /** @brief Device clk sources selection helpers */ /* WB05/WB09 only */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR_REG) /* WB06/WB07 only */ -#define SPI2_I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CFGR_REG) -/* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */ -#define SPI3_I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR_REG) +#define SPI2_I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 22, CFGR_REG) +/* `msb` is only 22 for WB06/WB07, but a single definition with msb=23 is acceptable */ +#define SPI3_I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32wb_clock.h b/include/zephyr/dt-bindings/clock/stm32wb_clock.h index dc6fa712448c3..b70d08fe00a41 100644 --- a/include/zephyr/dt-bindings/clock/stm32wb_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32wb_clock.h @@ -51,19 +51,19 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CSR devices */ -#define RFWKP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CSR_REG) +#define RFWKP_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32wba_clock.h b/include/zephyr/dt-bindings/clock/stm32wba_clock.h index 4405dc4cd5282..41ac53e5d078d 100644 --- a/include/zephyr/dt-bindings/clock/stm32wba_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32wba_clock.h @@ -57,34 +57,34 @@ /** @brief Device clk sources selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) -#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG) -#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) -#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) -#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG) +#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR1_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR1_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR1_REG) +#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR1_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR1_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG) +#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR1_REG) +#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, CCIPR1_REG) /** CCIPR2 devices */ #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) -#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR2_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG) +#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR2_REG) /** CCIPR3 devices */ -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) -#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 3, CCIPR3_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR3_REG) /** BCDR1 devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BCDR1_REG) /** @brief RCC_CFGRx register offset */ #define CFGR1_REG 0x1C /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/include/zephyr/dt-bindings/clock/stm32wl_clock.h b/include/zephyr/dt-bindings/clock/stm32wl_clock.h index ec3806c1e9e38..6ff95298c56ca 100644 --- a/include/zephyr/dt-bindings/clock/stm32wl_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32wl_clock.h @@ -52,23 +52,23 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG) #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) -#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) -#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) -#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) -#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) +#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR_REG) +#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG) +#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, CCIPR_REG) +#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT(val, 0xF, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT(val, 0x7, 28, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT(val, 27, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT(val, 30, 28, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0 diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay index 8c3d46634a56a..8f213e775e43b 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay @@ -69,5 +69,6 @@ /* changes clock source for both ADC1 and ADC2 */ clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>, <&rcc STM32_SRC_PLL_P ADC12_SEL(1)>; + clock-names = "adcx", "adc_ker"; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay index d05075de3e982..f1d27aa416126 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay @@ -97,5 +97,6 @@ &adc1 { clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>, <&rcc STM32_SRC_PLL_P ADC_SEL(2)>; + clock-names = "adcx", "adc_ker"; status = "okay"; };