From 815ea69e944e44058e25879f941ab4b2b23a1d42 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Thu, 16 Oct 2025 15:39:39 +0200 Subject: [PATCH 1/2] drivers: clock_control: stm32: enable clocks for SRAM1 and SRAM2 enables the AHB2 peripheral clocks for SRAM1 and SRAM2 on STM32H7RSX series using LL_AHB2_GRP1_EnableClock. These clocks are required to access the corresponding SRAM regions during runtime. Fixes potential access faults when using SRAM1 and SRAM2. Signed-off-by: Fabrice DJIATSA --- drivers/clock_control/clock_stm32_ll_h7.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 3b99555d1eead..2f0a581d24bec 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -1040,6 +1040,14 @@ int stm32_clock_control_init(const struct device *dev) #endif z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram1)) + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AHBSRAM1); +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram2)) + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AHBSRAM2); +#endif +#endif /* Set up individual enabled clocks */ set_up_fixed_clock_sources(); From ba95743e155769ad7b823f96c28da28c4a2396d5 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Fri, 17 Oct 2025 12:09:45 +0200 Subject: [PATCH 2/2] dts: arm: st: h7rs: Add zephyr,memory-attr to SRAM1 and SRAM2 regions adds the `zephyr,memory-attr` property to the SRAM1 and SRAM2 memory nodes to explicitly define their MPU attributes as normal RAM. This ensures proper memory protection and caching behavior when these regions are used by the kernel or application. Resolve a Data Access Violation encountered during test, where the faulting address was 0x30000000. Note: add the zephyr,memory-attr property in the board overlay for SRAM2 to avoid conflict with the support of h7rs ethernet with MPU regions enabled. see link below for more details : https://github.com/zephyrproject-rtos/zephyr/pull/97364/files#r2439668915 Signed-off-by: Fabrice DJIATSA --- dts/arm/st/h7rs/stm32h7rs.dtsi | 1 + tests/drivers/memc/ram/boards/stm32h7s78_dk.overlay | 9 +++++++++ 2 files changed, 10 insertions(+) create mode 100644 tests/drivers/memc/ram/boards/stm32h7s78_dk.overlay diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index 15be4b8c3c18d..b11ce5da933dc 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -60,6 +60,7 @@ reg = <0x30000000 DT_SIZE_K(16)>; compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "SRAM1"; + zephyr,memory-attr = ; }; /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ diff --git a/tests/drivers/memc/ram/boards/stm32h7s78_dk.overlay b/tests/drivers/memc/ram/boards/stm32h7s78_dk.overlay new file mode 100644 index 0000000000000..e640ef5aaec49 --- /dev/null +++ b/tests/drivers/memc/ram/boards/stm32h7s78_dk.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sram2 { + zephyr,memory-attr = ; +};