From 56697d62725ad90df226e1326dc23eaf28cd7eb8 Mon Sep 17 00:00:00 2001 From: Yuriy Vynnychek Date: Wed, 8 Oct 2025 12:20:18 +0300 Subject: [PATCH 1/4] dts: infineon: xmc7200: fix wrong Flash and SRAM namings Fix wrong case when Flash was called "data" and SRAM was called "code". Rename Flash to "code" and SRAM to "data". Signed-off-by: Yuriy Vynnychek --- .../kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts | 4 ++-- .../kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts | 4 ++-- .../kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts | 4 ++-- .../cat1c/xmc7200/memory_partition.dtsi | 18 ++++++++++++------ 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts index 0820c7d669379..8c5a65b19e9b1 100644 --- a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts @@ -16,8 +16,8 @@ compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; chosen { - zephyr,sram = &m0p_code; - zephyr,flash = &m0p_data; + zephyr,sram = &sram_m0p; + zephyr,flash = &flash_m0p; zephyr,console = &uart3; zephyr,shell-uart = &uart3; }; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts index 1e14555daedf0..fe4a2ffe56554 100644 --- a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts @@ -20,8 +20,8 @@ }; chosen { - zephyr,sram = &cm7_0_code; - zephyr,flash = &cm7_0_data; + zephyr,sram = &sram_m7_0; + zephyr,flash = &flash_m7_0; zephyr,dtcm = &dtcm; zephyr,itcm = &itcm; zephyr,console = &uart3; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts index ccfb909208a18..138ffa114b23c 100644 --- a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts @@ -20,8 +20,8 @@ }; chosen { - zephyr,sram = &cm7_1_code; - zephyr,flash = &cm7_1_data; + zephyr,sram = &sram_m7_1; + zephyr,flash = &flash_m7_1; zephyr,dtcm = &dtcm; zephyr,itcm = &itcm; zephyr,console = &uart3; diff --git a/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi b/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi index e9fe7fa7ce7f5..0d69b200f3715 100644 --- a/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi @@ -1,34 +1,40 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ / { - m0p_code: m0p_code@28000800 { + sram_m0p: sram@28000800 { compatible = "mmio-sram"; reg = <0x28000800 DT_SIZE_K(16)>; }; - m0p_data: m0p_data@10000000 { + flash_m0p: flash@10000000 { compatible = "soc-nv-flash"; reg = <0x10000000 DT_SIZE_K(512)>; write-block-size = <512>; erase-block-size = <512>; }; - cm7_0_code: cm7_0_code@28004000 { + sram_m7_0: sram@28004000 { compatible = "mmio-sram"; reg = <0x28004000 DT_SIZE_K(816)>; }; - cm7_0_data: cm7_0_data@10080000 { + flash_m7_0: flash@10080000 { compatible = "soc-nv-flash"; reg = <0x10080000 DT_SIZE_K(2048)>; write-block-size = <512>; erase-block-size = <512>; }; - cm7_1_code: cm7_1_code@280d0000 { + sram_m7_1: sram@280d0000 { compatible = "mmio-sram"; reg = <0x280d0000 DT_SIZE_K(64)>; }; - cm7_1_data: cm7_1_data@10280000 { + flash_m7_1: flash@10280000 { compatible = "soc-nv-flash"; reg = <0x10280000 DT_SIZE_K(5824)>; write-block-size = <512>; From 54b2a09474a8574ba1378fc47ac32cf3d2ffaf93 Mon Sep 17 00:00:00 2001 From: Yuriy Vynnychek Date: Wed, 8 Oct 2025 12:56:08 +0300 Subject: [PATCH 2/4] soc: infineon: xmc7200: extend CYT4BFxx MPNs support - Add Cortex M0+, M7(0) and M7(1) selection. - Add TEQFP_176 and BGA_320 package support. Signed-off-by: Yuriy Vynnychek --- modules/hal_infineon/CMakeLists.txt | 5 + .../hal_infineon/mtb-hal-cat1/CMakeLists.txt | 4 + soc/infineon/cat1c/soc.yml | 48 +++++ soc/infineon/cat1c/xmc7200/CMakeLists.txt | 3 - soc/infineon/cat1c/xmc7200/Kconfig | 154 ++++++++++++++++ soc/infineon/cat1c/xmc7200/Kconfig.soc | 168 ++++++++++++++++++ soc/infineon/cat1c/xmc7200/soc_m7.c | 12 +- 7 files changed, 385 insertions(+), 9 deletions(-) diff --git a/modules/hal_infineon/CMakeLists.txt b/modules/hal_infineon/CMakeLists.txt index ac5eb53d7fc00..a25da7df3369b 100644 --- a/modules/hal_infineon/CMakeLists.txt +++ b/modules/hal_infineon/CMakeLists.txt @@ -70,6 +70,11 @@ if(CONFIG_SOC_FAMILY_INFINEON_EDGE) add_subdirectory(mtb-dsl-pse8xxgp) endif() +if(CONFIG_SOC_FAMILY_INFINEON_CAT1C) + zephyr_library_compile_definitions_ifdef(CONFIG_SOC_XMC7200_CORE_NAME_M7_0 CORE_NAME_CM7_0) + zephyr_library_compile_definitions_ifdef(CONFIG_SOC_XMC7200_CORE_NAME_M7_1 CORE_NAME_CM7_1) +endif() + if(CONFIG_SOC_SERIES_PSC3) add_subdirectory(zephyr-ifx-cycfg) endif() diff --git a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt index 6a5de56184cc2..ffa26edb2498d 100644 --- a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt +++ b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt @@ -63,8 +63,12 @@ zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_04_80_TQFP zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_CYW20829_56_QFN ${hal_cat1b_dir}/source/pin_packages/cyhal_cyw20829_56_qfn.c) +zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_XMC7200_176_TEQFP + ${hal_cat1c_dir}/source/pin_packages/cyhal_xmc7200_176_teqfp.c) zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_XMC7200_272_BGA ${hal_cat1c_dir}/source/pin_packages/cyhal_xmc7200_272_bga.c) +zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_XMC7200_320_BGA + ${hal_cat1c_dir}/source/pin_packages/cyhal_xmc7200_320_bga.c.c) zephyr_library_sources_ifdef(CONFIG_SOC_DIE_CYW20829 ${hal_cat1b_dir}/source/triggers/cyhal_triggers_cyw20829.c) diff --git a/soc/infineon/cat1c/soc.yml b/soc/infineon/cat1c/soc.yml index 38f1fe272ed19..8fd0aebeb611c 100644 --- a/soc/infineon/cat1c/soc.yml +++ b/soc/infineon/cat1c/soc.yml @@ -14,14 +14,62 @@ family: - name: cyt4bf socs: - name: cyt4bf8ces + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bf8cee + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bf8cds + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bf8cde + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfbcjs + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfbcje + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfbchs + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfbche + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfccjs + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfccje + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfcchs + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 - name: cyt4bfcche + cpuclusters: + - name: m0p + - name: m7_0 + - name: m7_1 diff --git a/soc/infineon/cat1c/xmc7200/CMakeLists.txt b/soc/infineon/cat1c/xmc7200/CMakeLists.txt index 431df0971babc..5dd825da64717 100644 --- a/soc/infineon/cat1c/xmc7200/CMakeLists.txt +++ b/soc/infineon/cat1c/xmc7200/CMakeLists.txt @@ -1,9 +1,6 @@ # Copyright (c) 2025 Cypress Semiconductor Corporation. # SPDX-License-Identifier: Apache-2.0 -zephyr_compile_definitions_ifdef(CONFIG_SOC_XMC7200D_E272K8384_M7_0 CORE_NAME_CM7_0) -zephyr_compile_definitions_ifdef(CONFIG_SOC_XMC7200D_E272K8384_M7_1 CORE_NAME_CM7_1) - zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS soc_m0p.c) zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) zephyr_include_directories(.) diff --git a/soc/infineon/cat1c/xmc7200/Kconfig b/soc/infineon/cat1c/xmc7200/Kconfig index b04d8f88f82e3..fff3571d0be03 100644 --- a/soc/infineon/cat1c/xmc7200/Kconfig +++ b/soc/infineon/cat1c/xmc7200/Kconfig @@ -15,11 +15,165 @@ config SOC_SERIES_XMC7200 select CPU_HAS_FPU if CPU_CORTEX_M7 select SOC_PREP_HOOK +# SOC Cortex M7 Cores +config SOC_XMC7200_CORE_NAME_M7_0 + bool + +config SOC_XMC7200_CORE_NAME_M7_1 + bool + +# xmc7200d_e272k8384 config SOC_XMC7200D_E272K8384_M0PLUS select CPU_CORTEX_M0PLUS config SOC_XMC7200D_E272K8384_M7_0 select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 config SOC_XMC7200D_E272K8384_M7_1 select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bf8ces +config SOC_CYT4BF8CES_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BF8CES_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BF8CES_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bf8cee +config SOC_CYT4BF8CEE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BF8CEE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BF8CEE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bf8cds +config SOC_CYT4BF8CDS_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BF8CDS_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BF8CDS_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bf8cde +config SOC_CYT4BF8CDE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BF8CDE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BF8CDE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfbcjs +config SOC_CYT4BFBCJS_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFBCJS_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFBCJS_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfbcje +config SOC_CYT4BFBCJE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFBCJE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFBCJE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfbchs +config SOC_CYT4BFBCHS_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFBCHS_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFBCHS_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfbche +config SOC_CYT4BFBCHE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFBCHE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFBCHE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfccjs +config SOC_CYT4BFCCJS_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFCCJS_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFCCJS_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfccje +config SOC_CYT4BFCCJE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFCCJE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFCCJE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfcchs +config SOC_CYT4BFCCHS_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFCCHS_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFCCHS_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 + +# cyt4bfcche +config SOC_CYT4BFCCHE_M0PLUS + select CPU_CORTEX_M0PLUS + +config SOC_CYT4BFCCHE_M7_0 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_0 + +config SOC_CYT4BFCCHE_M7_1 + select CPU_CORTEX_M7 + select SOC_XMC7200_CORE_NAME_M7_1 diff --git a/soc/infineon/cat1c/xmc7200/Kconfig.soc b/soc/infineon/cat1c/xmc7200/Kconfig.soc index 0e9110aa72141..7847e8e30c464 100644 --- a/soc/infineon/cat1c/xmc7200/Kconfig.soc +++ b/soc/infineon/cat1c/xmc7200/Kconfig.soc @@ -60,64 +60,232 @@ config SOC_XMC7200D_E272K8384_M7_1 select SOC_PACKAGE_XMC7200_272_BGA select SOC_SERIES_XMC7200 +# Infineon T2G Body High series MCUs: CYT4BF8CES +config SOC_CYT4BF8CES_M0PLUS + bool + select SOC_CYT4BF8CES + +config SOC_CYT4BF8CES_M7_0 + bool + select SOC_CYT4BF8CES + +config SOC_CYT4BF8CES_M7_1 + bool + select SOC_CYT4BF8CES + config SOC_CYT4BF8CES bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_176_TEQFP +# Infineon T2G Body High series MCUs: CYT4BF8CEE +config SOC_CYT4BF8CEE_M0PLUS + bool + select SOC_CYT4BF8CEE + +config SOC_CYT4BF8CEE_M7_0 + bool + select SOC_CYT4BF8CEE + +config SOC_CYT4BF8CEE_M7_1 + bool + select SOC_CYT4BF8CEE + config SOC_CYT4BF8CEE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_176_TEQFP +# Infineon T2G Body High series MCUs: CYT4BF8CDS +config SOC_CYT4BF8CDS_M0PLUS + bool + select SOC_CYT4BF8CDS + +config SOC_CYT4BF8CDS_M7_0 + bool + select SOC_CYT4BF8CDS + +config SOC_CYT4BF8CDS_M7_1 + bool + select SOC_CYT4BF8CDS + config SOC_CYT4BF8CDS bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_176_TEQFP +# Infineon T2G Body High series MCUs: CYT4BF8CDE +config SOC_CYT4BF8CDE_M0PLUS + bool + select SOC_CYT4BF8CDE + +config SOC_CYT4BF8CDE_M7_0 + bool + select SOC_CYT4BF8CDE + +config SOC_CYT4BF8CDE_M7_1 + bool + select SOC_CYT4BF8CDE + config SOC_CYT4BF8CDE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_176_TEQFP +# Infineon T2G Body High series MCUs: CYT4BFBCJS +config SOC_CYT4BFBCJS_M0PLUS + bool + select SOC_CYT4BFBCJS + +config SOC_CYT4BFBCJS_M7_0 + bool + select SOC_CYT4BFBCJS + +config SOC_CYT4BFBCJS_M7_1 + bool + select SOC_CYT4BFBCJS + config SOC_CYT4BFBCJS bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_272_BGA +# Infineon T2G Body High series MCUs: CYT4BFBCJE +config SOC_CYT4BFBCJE_M0PLUS + bool + select SOC_CYT4BFBCJE + +config SOC_CYT4BFBCJE_M7_0 + bool + select SOC_CYT4BFBCJE + +config SOC_CYT4BFBCJE_M7_1 + bool + select SOC_CYT4BFBCJE + config SOC_CYT4BFBCJE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_272_BGA +# Infineon T2G Body High series MCUs: CYT4BFBCHS +config SOC_CYT4BFBCHS_M0PLUS + bool + select SOC_CYT4BFBCHS + +config SOC_CYT4BFBCHS_M7_0 + bool + select SOC_CYT4BFBCHS + +config SOC_CYT4BFBCHS_M7_1 + bool + select SOC_CYT4BFBCHS + config SOC_CYT4BFBCHS bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_272_BGA +# Infineon T2G Body High series MCUs: CYT4BFBCHE +config SOC_CYT4BFBCHE_M0PLUS + bool + select SOC_CYT4BFBCHE + +config SOC_CYT4BFBCHE_M7_0 + bool + select SOC_CYT4BFBCHE + +config SOC_CYT4BFBCHE_M7_1 + bool + select SOC_CYT4BFBCHE + config SOC_CYT4BFBCHE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_272_BGA +# Infineon T2G Body High series MCUs: CYT4BFCCJS +config SOC_CYT4BFCCJS_M0PLUS + bool + select SOC_CYT4BFCCJS + +config SOC_CYT4BFCCJS_M7_0 + bool + select SOC_CYT4BFCCJS + +config SOC_CYT4BFCCJS_M7_1 + bool + select SOC_CYT4BFCCJS + config SOC_CYT4BFCCJS bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_320_BGA +# Infineon T2G Body High series MCUs: CYT4BFCCJE +config SOC_CYT4BFCCJE_M0PLUS + bool + select SOC_CYT4BFCCJE + +config SOC_CYT4BFCCJE_M7_0 + bool + select SOC_CYT4BFCCJE + +config SOC_CYT4BFCCJE_M7_1 + bool + select SOC_CYT4BFCCJE + config SOC_CYT4BFCCJE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_320_BGA +# Infineon T2G Body High series MCUs: CYT4BFCCHS +config SOC_CYT4BFCCHS_M0PLUS + bool + select SOC_CYT4BFCCHS + +config SOC_CYT4BFCCHS_M7_0 + bool + select SOC_CYT4BFCCHS + +config SOC_CYT4BFCCHS_M7_1 + bool + select SOC_CYT4BFCCHS + config SOC_CYT4BFCCHS bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_320_BGA +# Infineon T2G Body High series MCUs: CYT4BFCCHE +config SOC_CYT4BFCCHE_M0PLUS + bool + select SOC_CYT4BFCCHE + +config SOC_CYT4BFCCHE_M7_0 + bool + select SOC_CYT4BFCCHE + +config SOC_CYT4BFCCHE_M7_1 + bool + select SOC_CYT4BFCCHE + config SOC_CYT4BFCCHE bool select SOC_DIE_XMC7200 + select SOC_SERIES_XMC7200 select SOC_PACKAGE_XMC7200_320_BGA config SOC diff --git a/soc/infineon/cat1c/xmc7200/soc_m7.c b/soc/infineon/cat1c/xmc7200/soc_m7.c index 1fdaedfb63971..774ab35011434 100644 --- a/soc/infineon/cat1c/xmc7200/soc_m7.c +++ b/soc/infineon/cat1c/xmc7200/soc_m7.c @@ -38,7 +38,7 @@ __attribute__((section(".itcm"))) void sys_int_handler(uint32_t intrNum) { uint32_t system_int_idx; -#ifdef CORE_NAME_CM7_0 +#ifdef CONFIG_SOC_XMC7200_CORE_NAME_M7_0 if ((_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum]))) { system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[intrNum]); @@ -46,7 +46,7 @@ __attribute__((section(".itcm"))) void sys_int_handler(uint32_t intrNum) (entry->isr)(entry->arg); } #endif -#ifdef CORE_NAME_CM7_1 +#ifdef CONFIG_SOC_XMC7200_CORE_NAME_M7_1 if ((_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum]))) { system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[intrNum]); @@ -103,9 +103,9 @@ void soc_prep_hook(void) /* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register * (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0]) */ -#ifdef CORE_NAME_CM7_1 +#ifdef CONFIG_SOC_XMC7200_CORE_NAME_M7_1 CPUSS->CM7_1_CTL &= ~(0xB); -#elif CORE_NAME_CM7_0 +#elif CONFIG_SOC_XMC7200_CORE_NAME_M7_0 CPUSS->CM7_0_CTL &= ~(0xB); #else #error "Not valid" @@ -118,12 +118,12 @@ void soc_prep_hook(void) SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */ SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */ -#ifdef CORE_NAME_CM7_0 +#ifdef CONFIG_SOC_XMC7200_CORE_NAME_M7_0 CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos); CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos); CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos); CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos); -#elif CORE_NAME_CM7_1 +#elif CONFIG_SOC_XMC7200_CORE_NAME_M7_1 CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos); CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos); CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos); From 9afe1c4d68216a13ce00f6435de717ef716523bf Mon Sep 17 00:00:00 2001 From: Yuriy Vynnychek Date: Wed, 8 Oct 2025 13:27:01 +0300 Subject: [PATCH 3/4] board: infineon: kit_t2g_b_h_lite: new board basic support Add new board basic support: dts, kconfig, defconfig, openocd and doc. Signed-off-by: Yuriy Vynnychek --- .../kit_t2g_b_h_lite/Kconfig.kit_t2g_b_h_lite | 9 ++ boards/infineon/kit_t2g_b_h_lite/board.cmake | 9 ++ boards/infineon/kit_t2g_b_h_lite/board.yml | 11 ++ .../doc/img/kit_t2g_b_h_lite.webp | Bin 0 -> 91094 bytes .../infineon/kit_t2g_b_h_lite/doc/index.rst | 148 ++++++++++++++++++ .../kit_t2g_b_h_lite_common.dtsi | 102 ++++++++++++ ...t_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi | 23 +++ .../kit_t2g_b_h_lite_cyt4bf8cds_m0p.dts | 26 +++ .../kit_t2g_b_h_lite_cyt4bf8cds_m0p.yaml | 15 ++ .../kit_t2g_b_h_lite_cyt4bf8cds_m0p_defconfig | 21 +++ .../kit_t2g_b_h_lite_cyt4bf8cds_m7_0.dts | 28 ++++ .../kit_t2g_b_h_lite_cyt4bf8cds_m7_0.yaml | 18 +++ ...kit_t2g_b_h_lite_cyt4bf8cds_m7_0_defconfig | 22 +++ .../kit_t2g_b_h_lite_cyt4bf8cds_m7_1.dts | 28 ++++ .../kit_t2g_b_h_lite_cyt4bf8cds_m7_1.yaml | 18 +++ ...kit_t2g_b_h_lite_cyt4bf8cds_m7_1_defconfig | 22 +++ .../kit_t2g_b_h_lite/support/openocd.cfg | 17 ++ .../arm_irq_advanced_features/testcase.yaml | 2 + .../arm_irq_zero_latency_levels/testcase.yaml | 2 + 19 files changed, 521 insertions(+) create mode 100644 boards/infineon/kit_t2g_b_h_lite/Kconfig.kit_t2g_b_h_lite create mode 100644 boards/infineon/kit_t2g_b_h_lite/board.cmake create mode 100644 boards/infineon/kit_t2g_b_h_lite/board.yml create mode 100644 boards/infineon/kit_t2g_b_h_lite/doc/img/kit_t2g_b_h_lite.webp create mode 100644 boards/infineon/kit_t2g_b_h_lite/doc/index.rst create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_common.dtsi create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.dts create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.yaml create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.dts create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.yaml create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.dts create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.yaml create mode 100644 boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_lite/support/openocd.cfg diff --git a/boards/infineon/kit_t2g_b_h_lite/Kconfig.kit_t2g_b_h_lite b/boards/infineon/kit_t2g_b_h_lite/Kconfig.kit_t2g_b_h_lite new file mode 100644 index 0000000000000..33e0f2ab9d533 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/Kconfig.kit_t2g_b_h_lite @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KIT_T2G_B_H_LITE + select SOC_CYT4BF8CDS_M0PLUS if BOARD_KIT_T2G_B_H_LITE_CYT4BF8CDS_M0P + select SOC_CYT4BF8CDS_M7_0 if BOARD_KIT_T2G_B_H_LITE_CYT4BF8CDS_M7_0 + select SOC_CYT4BF8CDS_M7_1 if BOARD_KIT_T2G_B_H_LITE_CYT4BF8CDS_M7_1 diff --git a/boards/infineon/kit_t2g_b_h_lite/board.cmake b/boards/infineon/kit_t2g_b_h_lite/board.cmake new file mode 100644 index 0000000000000..e67b978332bcd --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Connect to CM0P core. +board_runner_args(openocd "--target-handle=cat1c.cpu.cm0") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/kit_t2g_b_h_lite/board.yml b/boards/infineon/kit_t2g_b_h_lite/board.yml new file mode 100644 index 0000000000000..030c178d877b1 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/board.yml @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or 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z1xX{NdAv`j7OhEw0NgGG&m^h~ekbLfyyYi=@4sX5FDftLXayJLoj`z&Zm0LLW#7*s zw=YUBz3c>%!+4>lB84cHxA++1a%Bg7oJt185GNtcIi`)DpMFG}`NGkohwP98ZCp)&>#2z?+smT$rg&{0%CwEq$TL1igq^Dc3p*K}s8XL3_8uQPv5_K=@9po;*o`;!lCR#BG@}3>&>_ua z5Y-hgB|PgryibDc6BOUW!2zEA2m97|=?J z`mw^TPwoKmF{Skp@tQv004(Ffa`KvHgdKW~nAem0GDu=ez z00000001dg7A$ZGDEvRrOR+p5P!PR)SwcM2G0A|VEABgwplG*bSM{>mad2+ERsW6D ze7fU%|1Q7%ON%yMUdvCV%9G6B^|V{A{4$D}fZw~S$zv3)=r^_rZTdnlso?;GMC?Qu zlNN27ZXx^YfTv9Rx9%?l6%v4>7}6i~^SA8-XlmO8fTMJZjI@ zP8^`516CIR9w3VI4)e*PX$*FkqB&CD)TFU%_;V3_yAF~L%np2fUO)kO%{7|Z9x=~2 z`2~i`rg=~G8Sy`AZzdUew=vl%D3z1W45FX}AQN? +#include +#include + +/ { + aliases { + led0 = &user_led0; + led1 = &user_led1; + led2 = &user_led2; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt5 0 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt5 1 GPIO_ACTIVE_LOW>; + }; + + user_led2: led_2 { + label = "LED_2"; + gpios = <&gpio_prt5 2 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt5 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt17 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +uart0: &scb0 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + + /* UART pins */ + pinctrl-0 = <&p0_1_scb0_uart_tx &p0_0_scb0_uart_rx + &p0_2_scb0_uart_rts &p0_3_scb0_uart_cts>; + pinctrl-names = "default"; +}; + +&gpio_prt5 { + status = "okay"; +}; + +&gpio_prt17 { + status = "okay"; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_mem { + status = "okay"; +}; + +&clk_peri { + status = "okay"; +}; + +&clk_slow { + status = "okay"; +}; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi new file mode 100644 index 0000000000000..a23a877fdd3ed --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart pins */ +&p0_1_scb0_uart_tx { + drive-push-pull; +}; + +&p0_0_scb0_uart_rx { + input-enable; +}; + +&p0_2_scb0_uart_rts { + drive-push-pull; +}; + +&p0_3_scb0_uart_cts { + input-enable; +}; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.dts b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.dts new file mode 100644 index 0000000000000..0610d269bc488 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_lite_common.dtsi" + +/ { + model = "Infineon Evaluation Lite board for CYT4BF8CDS M0"; + compatible = "infineon,kit_t2g_b_h_lite", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m0p; + zephyr,flash = &flash_m0p; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.yaml b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.yaml new file mode 100644 index 0000000000000..0a4b6054aa7c4 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_lite/cyt4bf8cds/m0p +name: T2G Body High Lite Evaluation Kit (M0P) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p_defconfig b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p_defconfig new file mode 100644 index 0000000000000..8bb4abc1696a6 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m0p_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.dts b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.dts new file mode 100644 index 0000000000000..8f5c58880c44a --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_lite_common.dtsi" + +/ { + model = "Infineon Evaluation Lite board for CYT4BF8CDS M7_0"; + compatible = "infineon,kit_t2g_b_h_lite", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m7_0; + zephyr,flash = &flash_m7_0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.yaml b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.yaml new file mode 100644 index 0000000000000..add01e19d49ba --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_lite/cyt4bf8cds/m7_0 +name: T2G Body High Lite Evaluation Kit (M7_0) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0_defconfig b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0_defconfig new file mode 100644 index 0000000000000..d9577b283e1fc --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_0_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.dts b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.dts new file mode 100644 index 0000000000000..a6513801898f1 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_lite_cyt4bf8cds_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_lite_common.dtsi" + +/ { + model = "Infineon Evaluation Lite board for CYT4BF8CDS M7_1"; + compatible = "infineon,kit_t2g_b_h_lite", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m7_1; + zephyr,flash = &flash_m7_1; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.yaml b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.yaml new file mode 100644 index 0000000000000..3f944d2edd046 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_lite/cyt4bf8cds/m7_1 +name: T2G Body High Lite Evaluation Kit (M7_1) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1_defconfig b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1_defconfig new file mode 100644 index 0000000000000..d9577b283e1fc --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_cyt4bf8cds_m7_1_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_lite/support/openocd.cfg b/boards/infineon/kit_t2g_b_h_lite/support/openocd.cfg new file mode 100644 index 0000000000000..330e17aadc656 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_lite/support/openocd.cfg @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + #default connect over Debug USB port + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +source [find target/cat1c.cfg] \ No newline at end of file diff --git a/tests/arch/arm/arm_irq_advanced_features/testcase.yaml b/tests/arch/arm/arm_irq_advanced_features/testcase.yaml index bfe23667e0dca..bb23dfe64a34e 100644 --- a/tests/arch/arm/arm_irq_advanced_features/testcase.yaml +++ b/tests/arch/arm/arm_irq_advanced_features/testcase.yaml @@ -10,5 +10,7 @@ tests: platform_exclude: - kit_xmc72_evk/xmc7200d_e272k8384/m7_0 - kit_xmc72_evk/xmc7200d_e272k8384/m7_1 + - kit_t2g_b_h_lite/cyt4bf8cds/m7_0 + - kit_t2g_b_h_lite/cyt4bf8cds/m7_1 arch.arm.irq_advanced_features.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml index 6a012fbb09277..5e037d6cb11aa 100644 --- a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml +++ b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml @@ -13,6 +13,8 @@ tests: platform_exclude: - kit_xmc72_evk/xmc7200d_e272k8384/m7_0 - kit_xmc72_evk/xmc7200d_e272k8384/m7_1 + - kit_t2g_b_h_lite/cyt4bf8cds/m7_0 + - kit_t2g_b_h_lite/cyt4bf8cds/m7_1 arch.arm.irq_zero_latency_levels.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE integration_platforms: From a646b19f1f1b5e6eae4056266e1f293e9c38a535 Mon Sep 17 00:00:00 2001 From: Yuriy Vynnychek Date: Fri, 10 Oct 2025 15:58:16 +0300 Subject: [PATCH 4/4] board: infineon: kit_t2g_b_h_evk: new board basic support Add new board basic support: dts, kconfig, defconfig, openocd and doc. Signed-off-by: Yuriy Vynnychek --- .../kit_t2g_b_h_evk/Kconfig.kit_t2g_b_h_evk | 9 + boards/infineon/kit_t2g_b_h_evk/board.cmake | 9 + boards/infineon/kit_t2g_b_h_evk/board.yml | 11 ++ .../doc/img/kit_t2g_b_h_evk.webp | Bin 0 -> 74914 bytes boards/infineon/kit_t2g_b_h_evk/doc/index.rst | 160 ++++++++++++++++++ .../kit_t2g_b_h_evk_common.dtsi | 106 ++++++++++++ ...it_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi | 23 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m0p.dts | 26 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m0p.yaml | 15 ++ .../kit_t2g_b_h_evk_cyt4bfbche_m0p_defconfig | 21 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_0.dts | 28 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_0.yaml | 18 ++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_0_defconfig | 22 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_1.dts | 28 +++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_1.yaml | 18 ++ .../kit_t2g_b_h_evk_cyt4bfbche_m7_1_defconfig | 22 +++ .../kit_t2g_b_h_evk/support/openocd.cfg | 17 ++ .../arm_irq_advanced_features/testcase.yaml | 2 + .../arm_irq_zero_latency_levels/testcase.yaml | 2 + 19 files changed, 537 insertions(+) create mode 100644 boards/infineon/kit_t2g_b_h_evk/Kconfig.kit_t2g_b_h_evk create mode 100644 boards/infineon/kit_t2g_b_h_evk/board.cmake create mode 100644 boards/infineon/kit_t2g_b_h_evk/board.yml create mode 100644 boards/infineon/kit_t2g_b_h_evk/doc/img/kit_t2g_b_h_evk.webp create mode 100644 boards/infineon/kit_t2g_b_h_evk/doc/index.rst create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.dts create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.yaml create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.dts create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.yaml create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.dts create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.yaml create mode 100644 boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1_defconfig create mode 100644 boards/infineon/kit_t2g_b_h_evk/support/openocd.cfg diff --git a/boards/infineon/kit_t2g_b_h_evk/Kconfig.kit_t2g_b_h_evk b/boards/infineon/kit_t2g_b_h_evk/Kconfig.kit_t2g_b_h_evk new file mode 100644 index 0000000000000..08c8a121f7f8a --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/Kconfig.kit_t2g_b_h_evk @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KIT_T2G_B_H_EVK + select SOC_CYT4BFBCHE_M0PLUS if BOARD_KIT_T2G_B_H_EVK_CYT4BFBCHE_M0P + select SOC_CYT4BFBCHE_M7_0 if BOARD_KIT_T2G_B_H_EVK_CYT4BFBCHE_M7_0 + select SOC_CYT4BFBCHE_M7_1 if BOARD_KIT_T2G_B_H_EVK_CYT4BFBCHE_M7_1 diff --git a/boards/infineon/kit_t2g_b_h_evk/board.cmake b/boards/infineon/kit_t2g_b_h_evk/board.cmake new file mode 100644 index 0000000000000..e67b978332bcd --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Connect to CM0P core. +board_runner_args(openocd "--target-handle=cat1c.cpu.cm0") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/kit_t2g_b_h_evk/board.yml b/boards/infineon/kit_t2g_b_h_evk/board.yml new file mode 100644 index 0000000000000..4efea315225ea --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/board.yml @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an 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The TRAVEO™ T2G B-H MCU is specifically designed for automotive +applications and it is a true programmable embedded system-on-chip, integrating two 350-MHz Arm® +Cortex®-M7 as the primary application processor, a 100-MHz Arm® Cortex®-M0+ that supports the +following: + +- Low-power operations +- Up to 8 MB flash and 1 MB SRAM +- Secure Digital Host Controller (SDHC) supporting SD/SDIO/eMMC interfaces +- Programmable analog and digital peripherals that allow faster time-to-market + +The evaluation board carries a TRAVEO™ T2G-B-H MCU, an M.2 interface connector for interfacing radio +modules based on AIROC™ Wi-Fi & Bluetooth® combos (currently not supported), a Dual-PMOD SMIF +connector for interfacing HYPERBUS™ memories, and Arduino headers for interfacing Arduino Shields. +In addition, the board features an on-board programmer/debugger (KitProg3), a 512-Mb QSPI NOR flash, +a micro-B connector for the USB device interface, three user LEDs, one potentiometer, a Gigabit +ethernet port for ethernet applications and two push buttons. The board supports operating voltages +from 1.8 V to 5.0 V for TRAVEO™ T2G-B-H MCU. + +Hardware +******** + +For more information about KIT_T2G-B-H_EVK: + +- `kit_t2g_b_h_evk Board Website`_ +- `T2G_B_H SoC Website`_ + +Kit Features +============= + +- Evaluation board for CYT4BF MCU4 in BGA package with 272 pins, dual-core Arm®Cortex® M7 CPUs running at 350-MHz and an Arm® Cortex® M0+ CPU running at 100-MHz +- Full-system approach on the board, featuring Gigabit Ethernet PHY and connector, CAN FD transceiver, user LEDs, buttons, and potentiometer +- M.2 interface connector for interfacing radio modules based on AIROC™ Wi-Fi & Bluetooth®combos (currently not - supported) +- Headers compatible with Arduino for interfacing Arduino shields +- Fully compatible with ModusToolbox™ v3.0 +- KitProg3 on-board SWD programmer/debugger, USB-UART, and USB-I2C bridge functionality through USB connector +- Digilent dual PMOD SMIF header for interfacing HYPERBUS™ memories (currently not supported) +- A 512-Mbit external QSPI NOR flash +- Evaluation board supports operating voltages from 3.3 V to 5.0 V for CYT4BF + +Kit Contents +============= + +- TRAVEO™ T2G-B-H evaluation board +- USB Type-A to Micro-B cable +- 12V/3A DC power adapter with additional blades +- Quick start guide + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +Here is an example for building the :zephyr:code-sample:`blinky` sample application for Cortex®-M0+. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_t2g_b_h_evk/cyt4bfbche/m0p + :goals: build + +The same for the first Cortex®-M7 core: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_t2g_b_h_evk/cyt4bfbche/m7_0 + :goals: build + +And the second Cortex®-M7 core: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_t2g_b_h_evk/cyt4bfbche/m7_1 + :goals: build + +.. note:: Only Cortex®-M0+ core is enabled at startup. To enable the first Cortex®-M7 core, add the next code to Cortex®-M0+ application: ``Cy_SysEnableCM7(CORE_CM7_0, CY_CORTEX_M7_0_APPL_ADDR);``, and the next code to enable the second Cortex®-M7 core: ``Cy_SysEnableCM7(CORE_CM7_1, CY_CORTEX_M7_1_APPL_ADDR);``. + +Flashing +======== + +The KIT_T2G_B_H_EVK includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. + +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b kit_t2g_b_h_evk/cyt4bfbche/m0p -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b kit_t2g_b_h_evk/cyt4bfbche/m0p -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. + +References +********** + +.. target-notes:: + +.. _T2G_B_H SoC Website: + https://www.infineon.com/products/microcontroller/32-bit-traveo-t2g-arm-cortex/for-body/t2g-cyt4bf + +.. _kit_t2g_b_h_evk Board Website: + https://www.infineon.com/evaluation-board/KIT-T2G-B-H-EVK + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi new file mode 100644 index 0000000000000..45b5df0cfd0b9 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + aliases { + led0 = &user_led0; + led1 = &user_led1; + led2 = &user_led2; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt16 1 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt16 2 GPIO_ACTIVE_LOW>; + }; + + user_led2: led_2 { + label = "LED_2"; + gpios = <&gpio_prt16 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt21 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt17 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +uart3: &scb3 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + + /* UART pins */ + pinctrl-0 = <&p13_1_scb3_uart_tx &p13_0_scb3_uart_rx + &p13_2_scb3_uart_rts &p13_3_scb3_uart_cts>; + pinctrl-names = "default"; +}; + +&gpio_prt16 { + status = "okay"; +}; + +&gpio_prt17 { + status = "okay"; +}; + +&gpio_prt21 { + status = "okay"; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_mem { + status = "okay"; +}; + +&clk_peri { + status = "okay"; +}; + +&clk_slow { + status = "okay"; +}; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi new file mode 100644 index 0000000000000..2a670436b07c3 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart pins */ +&p13_1_scb3_uart_tx { + drive-push-pull; +}; + +&p13_0_scb3_uart_rx { + input-enable; +}; + +&p13_2_scb3_uart_rts { + drive-push-pull; +}; + +&p13_3_scb3_uart_cts { + input-enable; +}; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.dts b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.dts new file mode 100644 index 0000000000000..fca69bb86a101 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_evk_common.dtsi" + +/ { + model = "Infineon Evaluation board for CYT4BFBCHE M0"; + compatible = "infineon,kit_t2g_b_h_evk", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m0p; + zephyr,flash = &flash_m0p; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.yaml b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.yaml new file mode 100644 index 0000000000000..e84df502a14ae --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_evk/cyt4bfbche/m0p +name: T2G Body High Evaluation Kit (M0P) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p_defconfig b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p_defconfig new file mode 100644 index 0000000000000..8bb4abc1696a6 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m0p_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.dts b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.dts new file mode 100644 index 0000000000000..c737ba683bb64 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_evk_common.dtsi" + +/ { + model = "Infineon Evaluation Evk board for CYT4BFBCHE M7_0"; + compatible = "infineon,kit_t2g_b_h_evk", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m7_0; + zephyr,flash = &flash_m7_0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.yaml b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.yaml new file mode 100644 index 0000000000000..17efd89360902 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_evk/cyt4bfbche/m7_0 +name: T2G Body High Evaluation Kit (M7_0) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0_defconfig b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0_defconfig new file mode 100644 index 0000000000000..d9577b283e1fc --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_0_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.dts b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.dts new file mode 100644 index 0000000000000..b71630a87c5f6 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_t2g_b_h_evk_cyt4bfbche_m0p-pinctrl.dtsi" +#include "kit_t2g_b_h_evk_common.dtsi" + +/ { + model = "Infineon Evaluation board for CYT4BFBCHE M7_1"; + compatible = "infineon,kit_t2g_b_h_evk", "infineon,TVIIBH8M"; + + chosen { + zephyr,sram = &sram_m7_1; + zephyr,flash = &flash_m7_1; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.yaml b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.yaml new file mode 100644 index 0000000000000..bc0420c8db98d --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: kit_t2g_b_h_evk/cyt4bfbche/m7_1 +name: T2G Body High Evaluation Kit (M7_1) +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1_defconfig b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1_defconfig new file mode 100644 index 0000000000000..cdde406d467c5 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_cyt4bfbche_m7_1_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# General configurations +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_t2g_b_h_evk/support/openocd.cfg b/boards/infineon/kit_t2g_b_h_evk/support/openocd.cfg new file mode 100644 index 0000000000000..330e17aadc656 --- /dev/null +++ b/boards/infineon/kit_t2g_b_h_evk/support/openocd.cfg @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + #default connect over Debug USB port + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +source [find target/cat1c.cfg] \ No newline at end of file diff --git a/tests/arch/arm/arm_irq_advanced_features/testcase.yaml b/tests/arch/arm/arm_irq_advanced_features/testcase.yaml index bb23dfe64a34e..61b2314fa4104 100644 --- a/tests/arch/arm/arm_irq_advanced_features/testcase.yaml +++ b/tests/arch/arm/arm_irq_advanced_features/testcase.yaml @@ -12,5 +12,7 @@ tests: - kit_xmc72_evk/xmc7200d_e272k8384/m7_1 - kit_t2g_b_h_lite/cyt4bf8cds/m7_0 - kit_t2g_b_h_lite/cyt4bf8cds/m7_1 + - kit_t2g_b_h_evk/cyt4bfbche/m7_0 + - kit_t2g_b_h_evk/cyt4bfbche/m7_1 arch.arm.irq_advanced_features.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml index 5e037d6cb11aa..5e3a49de0a93e 100644 --- a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml +++ b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml @@ -15,6 +15,8 @@ tests: - kit_xmc72_evk/xmc7200d_e272k8384/m7_1 - kit_t2g_b_h_lite/cyt4bf8cds/m7_0 - kit_t2g_b_h_lite/cyt4bf8cds/m7_1 + - kit_t2g_b_h_evk/cyt4bfbche/m7_0 + - kit_t2g_b_h_evk/cyt4bfbche/m7_1 arch.arm.irq_zero_latency_levels.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE integration_platforms: