diff --git a/boards/retronix/index.rst b/boards/retronix/index.rst new file mode 100644 index 0000000000000..026ba26fb3398 --- /dev/null +++ b/boards/retronix/index.rst @@ -0,0 +1,10 @@ +.. _boards-retronix: + +Retronix Technology Inc +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.defconfig b/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.defconfig new file mode 100644 index 0000000000000..7dee6a7a7412f --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BUILD_OUTPUT_BIN + default y if BOARD_SPARROWHAWK_RCAR_V4H_R8A779G0_R52 diff --git a/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.sparrowhawk_rcar_v4h b/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.sparrowhawk_rcar_v4h new file mode 100644 index 0000000000000..fcd1071cdf638 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/Kconfig.sparrowhawk_rcar_v4h @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARROWHAWK_RCAR_V4H + select SOC_R8A779G0_R52 if BOARD_SPARROWHAWK_RCAR_V4H_R8A779G0_R52 diff --git a/boards/retronix/sparrowhawk_rcar_v4h/board.cmake b/boards/retronix/sparrowhawk_rcar_v4h/board.cmake new file mode 100644 index 0000000000000..3907efd79b5a2 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +if(CONFIG_BOARD_SPARROWHAWK_RCAR_V4H_R8A779G0_R52) + board_runner_args(openocd "--use-elf") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/retronix/sparrowhawk_rcar_v4h/board.yml b/boards/retronix/sparrowhawk_rcar_v4h/board.yml new file mode 100644 index 0000000000000..f954afb832ae3 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/board.yml @@ -0,0 +1,6 @@ +board: + name: sparrowhawk_rcar_v4h + full_name: Sparrow Hawk R-Car V4H SBC + vendor: retronix + socs: + - name: r8a779g0 diff --git a/boards/retronix/sparrowhawk_rcar_v4h/doc/img/sparrowhawk_rcar_v4h.webp b/boards/retronix/sparrowhawk_rcar_v4h/doc/img/sparrowhawk_rcar_v4h.webp new file mode 100644 index 0000000000000..b59ce2045d6d5 Binary files /dev/null and b/boards/retronix/sparrowhawk_rcar_v4h/doc/img/sparrowhawk_rcar_v4h.webp differ diff --git a/boards/retronix/sparrowhawk_rcar_v4h/doc/sparrow_hawk_rcar_v4h_r52.rst b/boards/retronix/sparrowhawk_rcar_v4h/doc/sparrow_hawk_rcar_v4h_r52.rst new file mode 100644 index 0000000000000..ef06537985d25 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/doc/sparrow_hawk_rcar_v4h_r52.rst @@ -0,0 +1,148 @@ +.. zephyr:board:: sparrowhawk_rcar_v4h + +Overview +******** +Retronix Sparrow Hawk Single Board Computer (SBC) is powered by the latest Renesas R-Car V4H +System-on-Chip. Sparrow Hawk focuses on robotics, industrial automation, and rapid prototyping, +offering a highly flexible and cost-effective development platform. + +The R-Car V4H system-on-chip is tailored for central processing for advanced driver-assistance (ADAS) +and automated driving (AD) systems. The R-Car V4H achieves deep learning performance of up to 34 TOPS +(Tera Operations Per Second), enabling high-speed image recognition and processing of surrounding +objects by automotive cameras, radar, and Light Detection and Ranging (LiDAR). + +Hardware +******** + +Hardware capabilities of the board can be found on `Retronix Sparrow Hawk`_ page. +All the features of Renesas R-Car V4H SoC are described in the product page `Renesas R-Car V4H`_. + +Supported Features +================== + +We support Zephyr running on Cortex R52 processor that is provided for RTOS purpose. + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +For the connections and IO interfaces, refer to the official page `Retronix Sparrow Hawk`_ + +UART +---- + +Here is information about serial ports provided on Sparrow Hawk board : + ++--------------------------+--------------------+--------------------+-------------+---------------------------+ +| Software interface | Physical Interface | Hardware Interface | Converter | Usage Note | ++==========================+====================+====================+=============+===========================+ +| /tty/USBx, COMn (lower) | CN4 USB Port | HSCIF0 | FT2232H | Used by U-Boot and Linux | ++--------------------------+--------------------+--------------------+-------------+---------------------------+ +| /tty/USBy, COMm (higher) | CN4 USB Port | HSCIF1 | FT2232H | Default for Zephyr | ++--------------------------+--------------------+--------------------+-------------+---------------------------+ + +.. note:: + By default, Zephyr console output is assigned to HSCIF1 with 921600 8N1 without + hardware flow control. + +Programming and Debugging +************************* + +You can build the applications as usual. This is the example for Hello World: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sparrowhawk_rcar_v4h/r8a779g0/r52 + :goals: build + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN4 USB port. There are two COM ports (or /tty/USB devices) available. +Both of them are used for booting procedure. Use the following settings with your serial terminal of choice +(minicom, putty, etc.): + +* Speed: 921600 +* Data: 8 bits +* Parity: None +* Stop bits: 1 + +Flashing +======== + +The board does not support flashing Zephyr image. However, the image writing and loading +can be done with U-Boot. + +Make sure you have already flashed the board with U-Boot, see the guideline at: `Retronix Sparrow Hawk`_, +section "4.2.1. Flashing loader". +Connect the terminal software to the serial port of HSCIF0 (lower /tty/USBx or COMn). +Powerup the board by pressing SW1 switch. You would see the boot log: + +.. code-block:: console + + U-Boot SPL 2025.07 (Aug 07 2025 - 04:02:12 +0000) + Trying to boot from SPI + + + U-Boot 2025.07 (Aug 07 2025 - 04:02:12 +0000) + + CPU: Renesas Electronics R8A779G0 rev 3.0 + Model: Retronix Sparrow Hawk board based on r8a779g3 + DRAM: 2 GiB (total 16 GiB) + Core: 87 devices, 23 uclasses, devicetree: separate + MMC: mmc@ee140000: 0 + Loading Environment from SPIFlash... SF: Detected w77q51nw with page size 256 Bytes, erase size 64 KiB, total 64 MiB + OK + In: serial@e6540000 + Out: serial@e6540000 + Err: serial@e6540000 + Net: eth0: ethernet@e6800000 + => + +Press any key to stop the booting and continue at the U-Boot prompt. + +Method 1: Using TFTP to transfer Zephyr image + +This assumes that you have already installed a TFTP server in the host PC. +Put the image bin file ``build/zephyr/zephyr.bin`` inside TFTP root directory. Run these +U-Boot commands: + +.. code-block:: console + + => setenv ipaddr + => setenv serverip + => tftp 0x40040000 zephyr.bin + => rproc init; rproc load 0:3 0x40040000 0x200000; rproc start 0 + +Method 2: Using serial to transfer Zephyr image + +Some terminal software support transferring file via serial using Kermit protocol. Use this U-Boot commands: + +.. code-block:: console + + => loadb 0x40040000 921600 + ## Ready for binary (kermit) download to 0x40040000 at 921600 bps... + (Transfer zephyr.bin after this line) + ## Total Size = 0x00009f2c = 40748 Bytes + ## Start Addr = 0x40040000 + => rproc init; rproc load 0:3 0x40040000 0x200000; rproc start 0 + +You should see Zephyr boot log in the terminal of HSCIF1: + +.. code-block:: console + + *** Booting Zephyr OS build v4.2.0-4945-g8fc6351ef451 *** + Hello World! sparrowhawk_rcar_v4h/r8a779g0/r52 + +References +********** + +- `Renesas R-Car V4H`_ +- `Retronix Sparrow Hawk`_ + +.. _Renesas R-Car V4H: + https://www.renesas.com/en/products/r-car-v4h + +.. _Retronix Sparrow Hawk: + https://rcar-community.github.io/Sparrow-Hawk/index.html diff --git a/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52-pinctrl.dtsi b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52-pinctrl.dtsi new file mode 100644 index 0000000000000..fde35bcae664d --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pfc { + hscif0_data_tx_default: hscif0_data_tx_default { + pin = ; + }; + + hscif0_data_rx_default: hscif0_data_rx_default { + pin = ; + }; + + hscif1_data_tx_default: hscif1_data_tx_default { + pin = ; + }; + + hscif1_data_rx_default: hscif1_data_rx_default { + pin = ; + }; +}; diff --git a/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.dts b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.dts new file mode 100644 index 0000000000000..cad2bc51456b2 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "sparrowhawk_rcar_v4h_r8a779g0_r52-pinctrl.dtsi" + +/ { + model = "Retronix Sparrow Hawk on R-Car V4H"; + compatible = "retronix,sparrowhawk-v4h-cr52"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &hscif1; + zephyr,shell-uart = &hscif1; + }; +}; + +/* USB serial */ +&hscif0 { + pinctrl-0 = <&hscif0_data_tx_default &hscif0_data_rx_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_data_tx_default &hscif1_data_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.yaml b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.yaml new file mode 100644 index 0000000000000..05bf823b2da45 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52.yaml @@ -0,0 +1,11 @@ +identifier: sparrowhawk_rcar_v4h/r8a779g0/r52 +name: Retronix Sparrow Hawk with Renesas R-Car V4H Cortex R52 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - clock_control + - uart diff --git a/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52_defconfig b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52_defconfig new file mode 100644 index 0000000000000..2462bb8580726 --- /dev/null +++ b/boards/retronix/sparrowhawk_rcar_v4h/sparrowhawk_rcar_v4h_r8a779g0_r52_defconfig @@ -0,0 +1,11 @@ +CONFIG_CLOCK_CONTROL=y + +# UART driver +CONFIG_SERIAL=y +CONFIG_UART_USE_RUNTIME_CONFIGURE=y +CONFIG_UART_INTERRUPT_DRIVEN=n + +# Console +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=n +CONFIG_UART_CONSOLE=y diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 13100d651592d..ea1177c2cd317 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -128,6 +128,7 @@ if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR) zephyr_library_sources(clock_control_renesas_cpg_mssr.c) zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED clock_control_r8a7795_cpg_mssr.c) zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A779F0_CPG_MSSR_ENABLED clock_control_r8a779f0_cpg_mssr.c) + zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A779G0_CPG_MSSR_ENABLED clock_control_r8a779g0_cpg_mssr.c) endif() zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c) diff --git a/drivers/clock_control/clock_control_r8a779g0_cpg_mssr.c b/drivers/clock_control/clock_control_r8a779g0_cpg_mssr.c new file mode 100644 index 0000000000000..7d7e301967215 --- /dev/null +++ b/drivers/clock_control/clock_control_r8a779g0_cpg_mssr.c @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2023 EPAM Systems + * Copyright (c) 2023 IoT.bzh + * Copyright (c) 2025 Renesas Electronics Corporation + * + * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_r8a779g0_cpg_mssr + +#include +#include +#include +#include +#include +#include +#include +#include "clock_control_renesas_cpg_mssr.h" + +#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL +#include +LOG_MODULE_DECLARE(clock_control_rcar); + +#define R8A779G0_CLK_SD0_STOP_BIT 8 +#define R8A779G0_CLK_SD0_DIV_MASK 0x3 +#define R8A779G0_CLK_SD0_DIV_SHIFT 0 + +#define R8A779G0_CLK_SD0H_STOP_BIT 9 +#define R8A779G0_CLK_SD0H_DIV_MASK 0x7 +#define R8A779G0_CLK_SD0H_DIV_SHIFT 2 + +#define R8A779G0_CLK_SDSRC_DIV_MASK 0x3 +#define R8A779G0_CLK_SDSRC_DIV_SHIFT 29 + +struct r8a779g0_cpg_mssr_cfg { + DEVICE_MMIO_ROM; /* Must be first */ +}; + +struct r8a779g0_cpg_mssr_data { + struct rcar_cpg_mssr_data cmn; /* Must be first */ +}; + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779G0_CLK_OSCCLK, + + /* Internal Core Clocks */ + CLK_PLL5, + CLK_SDSRC, +}; + +/* NOTE: the array MUST be sorted by module field */ +static struct cpg_clk_info_table core_props[] = { + RCAR_CORE_CLK_INFO_ITEM(R8A779G0_CLK_S0D6_PER, RCAR_CPG_NONE, RCAR_CPG_NONE, + RCAR_CPG_KHZ(133330)), + RCAR_CORE_CLK_INFO_ITEM(R8A779G0_CLK_S0D12_PER, RCAR_CPG_NONE, RCAR_CPG_NONE, + RCAR_CPG_KHZ(66660)), + RCAR_CORE_CLK_INFO_ITEM(R8A779G0_CLK_CL16M, RCAR_CPG_NONE, RCAR_CPG_NONE, + RCAR_CPG_KHZ(16660)), + RCAR_CORE_CLK_INFO_ITEM(R8A779G0_CLK_SASYNCPERD1, RCAR_CPG_NONE, RCAR_CPG_NONE, 266666666), + + RCAR_CORE_CLK_INFO_ITEM(CLK_PLL5, RCAR_CPG_NONE, RCAR_CPG_NONE, RCAR_CPG_MHZ(3200)), + RCAR_CORE_CLK_INFO_ITEM(CLK_SDSRC, 0x08A4, CLK_PLL5, RCAR_CPG_NONE), +}; + +/* + * List of module stop control register and bit for each module. + * RCAR_MOD_CLK_INFO_ITEM(id, par_id): + * - id = xyz: represented by MSTPCRx bit yz + * - par_id: Clock source ID + */ + +/* NOTE: the array MUST be sorted by module field */ +static struct cpg_clk_info_table mod_props[] = { + RCAR_MOD_CLK_INFO_ITEM(514, R8A779G0_CLK_SASYNCPERD1), /* HSCIF0 */ + RCAR_MOD_CLK_INFO_ITEM(515, R8A779G0_CLK_SASYNCPERD1), /* HSCIF1 */ + RCAR_MOD_CLK_INFO_ITEM(702, R8A779G0_CLK_S0D12_PER), /* SCIF0 */ + RCAR_MOD_CLK_INFO_ITEM(915, R8A779G0_CLK_CL16M), /* GPIO0 group 0 */ + RCAR_MOD_CLK_INFO_ITEM(916, R8A779G0_CLK_CL16M), /* GPIO1 group 0 */ + RCAR_MOD_CLK_INFO_ITEM(917, R8A779G0_CLK_CL16M), /* GPIO2 group 0 */ +}; + +static int r8a779g0_cpg_enable_disable_core(const struct device *dev, + struct cpg_clk_info_table *clk_info, uint32_t enable) +{ + int ret = 0; + uint32_t reg; + + switch (clk_info->module) { + case R8A779G0_CLK_SD0: + reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); + reg &= ~(1 << R8A779G0_CLK_SD0_STOP_BIT); + reg |= (!enable << R8A779G0_CLK_SD0_STOP_BIT); + break; + case R8A779G0_CLK_SD0H: + reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); + reg &= ~(1 << R8A779G0_CLK_SD0H_STOP_BIT); + reg |= (!enable << R8A779G0_CLK_SD0H_STOP_BIT); + break; + default: + ret = -ENOTSUP; + break; + } + + if (!ret) { + rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); + } + return ret; +} + +static int r8a779g0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, + bool enable) +{ + struct cpg_clk_info_table *clk_info; + struct r8a779g0_cpg_mssr_data *data = dev->data; + k_spinlock_key_t key; + + clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); + if (!clk_info) { + return -EINVAL; + } + + if (enable && clk->rate > 0) { + int ret; + uintptr_t rate = clk->rate; + + ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, + (clock_control_subsys_rate_t)rate); + if (ret < 0) { + return ret; + } + } + + key = k_spin_lock(&data->cmn.lock); + r8a779g0_cpg_enable_disable_core(dev, clk_info, enable); + k_spin_unlock(&data->cmn.lock, key); + + return 0; +} + +int r8a779g0_cpg_mssr_start_stop(const struct device *dev, clock_control_subsys_t sys, bool enable) +{ + struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; + int ret; + + if (!dev || !sys) { + return -EINVAL; + } + + if (clk->domain == CPG_MOD) { + struct r8a779g0_cpg_mssr_data *data = dev->data; + k_spinlock_key_t key; + + key = k_spin_lock(&data->cmn.lock); + ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); + k_spin_unlock(&data->cmn.lock, key); + } else if (clk->domain == CPG_CORE) { + ret = r8a779g0_cpg_core_clock_endisable(dev, clk, enable); + } else { + ret = -EINVAL; + } + + return ret; +} + +static uint32_t r8a779g0_get_div_helper(uint32_t reg_val, uint32_t module) +{ + switch (module) { + case R8A779G0_CLK_S0D12_PER: + case R8A779G0_CLK_CL16M: + return 1; + case CLK_SDSRC: + reg_val >>= R8A779G0_CLK_SDSRC_DIV_SHIFT; + reg_val &= R8A779G0_CLK_SDSRC_DIV_MASK; + /* setting of 3 is prohibited */ + if (reg_val < 3) { + /* real divider is in range 4 - 6 */ + return reg_val + 4; + } + + LOG_WRN("SDSRC clock has an incorrect divider value: %u", reg_val); + return RCAR_CPG_NONE; + case R8A779G0_CLK_SD0H: + reg_val >>= R8A779G0_CLK_SD0H_DIV_SHIFT; + reg_val &= R8A779G0_CLK_SD0H_DIV_MASK; + /* setting of value bigger than 4 is prohibited */ + if (reg_val < 5) { + return (1 << reg_val); + } + + LOG_WRN("SD0H clock has an incorrect divider value: %u", reg_val); + return RCAR_CPG_NONE; + case R8A779G0_CLK_SD0: + /* convert only two possible values 0,1 to 2,4 */ + return (1 << ((reg_val & R8A779G0_CLK_SD0_DIV_MASK) + 1)); + default: + return RCAR_CPG_NONE; + } +} + +static int r8a779g0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) +{ + switch (module) { + case CLK_SDSRC: + /* divider has to be in range 4-6 */ + if (*divider > 3 && *divider < 7) { + /* we can write to register value in range 0-2 */ + *divider -= 4; + *divider <<= R8A779G0_CLK_SDSRC_DIV_SHIFT; + *div_mask = R8A779G0_CLK_SDSRC_DIV_MASK << R8A779G0_CLK_SDSRC_DIV_SHIFT; + return 0; + } + return -EINVAL; + case R8A779G0_CLK_SD0: + /* possible to have only 2 or 4 */ + if (*divider == 2 || *divider == 4) { + /* convert 2/4 to 0/1 */ + *divider >>= 2; + *div_mask = R8A779G0_CLK_SD0_DIV_MASK << R8A779G0_CLK_SD0_DIV_SHIFT; + return 0; + } + return -EINVAL; + case R8A779G0_CLK_SD0H: + /* divider should be power of two number and last possible value 16 */ + if (!is_power_of_two(*divider) || *divider > 16) { + return -EINVAL; + } + /* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */ + *divider = (find_lsb_set(*divider) - 1) << R8A779G0_CLK_SD0H_DIV_SHIFT; + *div_mask = R8A779G0_CLK_SD0H_DIV_MASK << R8A779G0_CLK_SD0H_DIV_SHIFT; + return 0; + default: + return -ENOTSUP; + } +} + +static int r8a779g0_cpg_mssr_start(const struct device *dev, clock_control_subsys_t sys) +{ + return r8a779g0_cpg_mssr_start_stop(dev, sys, true); +} + +static int r8a779g0_cpg_mssr_stop(const struct device *dev, clock_control_subsys_t sys) +{ + return r8a779g0_cpg_mssr_start_stop(dev, sys, false); +} + +static int r8a779g0_cpg_mssr_init(const struct device *dev) +{ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + + rcar_cpg_build_clock_relationship(dev); + rcar_cpg_update_all_in_out_freq(dev); + return 0; +} + +static const struct clock_control_driver_api r8a779g0_cpg_mssr_api = { + .on = r8a779g0_cpg_mssr_start, + .off = r8a779g0_cpg_mssr_stop, + .get_rate = rcar_cpg_get_rate, + .set_rate = rcar_cpg_set_rate, +}; + +#define R8A779G0_MSSR_INIT(inst) \ + static struct r8a779g0_cpg_mssr_cfg cpg_mssr##inst##_cfg = { \ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \ + }; \ + \ + static struct r8a779g0_cpg_mssr_data cpg_mssr##inst##_data = { \ + .cmn.clk_info_table[CPG_CORE] = core_props, \ + .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \ + .cmn.clk_info_table[CPG_MOD] = mod_props, \ + .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \ + .cmn.get_div_helper = r8a779g0_get_div_helper, \ + .cmn.set_rate_helper = r8a779g0_set_rate_helper}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &r8a779g0_cpg_mssr_init, NULL, &cpg_mssr##inst##_data, \ + &cpg_mssr##inst##_cfg, PRE_KERNEL_1, \ + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &r8a779g0_cpg_mssr_api); + +DT_INST_FOREACH_STATUS_OKAY(R8A779G0_MSSR_INIT) diff --git a/drivers/pinctrl/renesas/rcar/CMakeLists.txt b/drivers/pinctrl/renesas/rcar/CMakeLists.txt index dcfc36056342f..3de22224b6001 100644 --- a/drivers/pinctrl/renesas/rcar/CMakeLists.txt +++ b/drivers/pinctrl/renesas/rcar/CMakeLists.txt @@ -3,10 +3,12 @@ zephyr_library_sources(pfc_rcar.c) -if (CONFIG_SOC_R8A77951_R7 OR CONFIG_SOC_R8A77951_A57) +if(CONFIG_SOC_R8A77951_R7 OR CONFIG_SOC_R8A77951_A57) zephyr_library_sources(pfc_r8a77951.c) -elseif (CONFIG_SOC_R8A779F0_R52 OR CONFIG_SOC_R8A779F0_A55) +elseif(CONFIG_SOC_R8A779F0_R52 OR CONFIG_SOC_R8A779F0_A55) zephyr_library_sources(pfc_r8a779f0.c) +elseif(CONFIG_SOC_R8A779G0_R52) + zephyr_library_sources(pfc_r8a779g0.c) endif() zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) diff --git a/drivers/pinctrl/renesas/rcar/pfc_r8a779g0.c b/drivers/pinctrl/renesas/rcar/pfc_r8a779g0.c new file mode 100644 index 0000000000000..9cfd1c77c54e5 --- /dev/null +++ b/drivers/pinctrl/renesas/rcar/pfc_r8a779g0.c @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include +#include + +/* Set the size and bit offset of each pin in DRVxCTRLy registers */ +const struct pfc_drive_reg pfc_drive_regs[] = { + /* DRV0CTRL0 */ + { 0x80, { + {RCAR_GP_PIN(0, 7), 28, 3}, /* MSIOF5_SS2 */ + {RCAR_GP_PIN(0, 6), 24, 3}, /* IRQ0 */ + {RCAR_GP_PIN(0, 5), 20, 3}, /* IRQ1 */ + {RCAR_GP_PIN(0, 4), 16, 3}, /* IRQ2 */ + {RCAR_GP_PIN(0, 3), 12, 3}, /* IRQ3 */ + {RCAR_GP_PIN(0, 2), 8, 3}, /* GP0_02 */ + {RCAR_GP_PIN(0, 1), 4, 3}, /* GP0_01 */ + {RCAR_GP_PIN(0, 0), 0, 3}, /* GP0_00 */ + }}, + /* DRV1CTRL0 */ + { 0x84, { + {RCAR_GP_PIN(0, 15), 28, 3}, /* MSIOF2_SYNC */ + {RCAR_GP_PIN(0, 14), 24, 3}, /* MSIOF2_SS1 */ + {RCAR_GP_PIN(0, 13), 20, 3}, /* MSIOF2_SS2 */ + {RCAR_GP_PIN(0, 12), 16, 3}, /* MSIOF5_RXD */ + {RCAR_GP_PIN(0, 11), 12, 3}, /* MSIOF5_SCK */ + {RCAR_GP_PIN(0, 10), 8, 3}, /* MSIOF5_TXD */ + {RCAR_GP_PIN(0, 9), 4, 3}, /* MSIOF5_SYNC */ + {RCAR_GP_PIN(0, 8), 0, 3}, /* MSIOF5_SS1 */ + }}, + /* DRV2CTRL0 */ + { 0x88, { + {RCAR_GP_PIN(0, 18), 8, 3}, /* MSIOF2_RXD */ + {RCAR_GP_PIN(0, 17), 4, 3}, /* MSIOF2_SCK */ + {RCAR_GP_PIN(0, 16), 0, 3}, /* MSIOF2_TXD */ + }}, + /* DRV3CTRL0 is empty */ + /* DRV0CTRL1 */ + { 0x80, { + {RCAR_GP_PIN(1, 7), 28, 3}, /* MSIOF0_SS1 */ + {RCAR_GP_PIN(1, 6), 24, 3}, /* MSIOF0_SS2 */ + {RCAR_GP_PIN(1, 5), 20, 3}, /* MSIOF1_RXD */ + {RCAR_GP_PIN(1, 4), 16, 3}, /* MSIOF1_TXD */ + {RCAR_GP_PIN(1, 3), 12, 3}, /* MSIOF1_SCK */ + {RCAR_GP_PIN(1, 2), 8, 3}, /* MSIOF1_SYNC */ + {RCAR_GP_PIN(1, 1), 4, 3}, /* MSIOF1_SS1 */ + {RCAR_GP_PIN(1, 0), 0, 3}, /* MSIOF1_SS2 */ + }}, + /* DRV1CTRL1 */ + { 0x84, { + {RCAR_GP_PIN(1, 15), 28, 3}, /* HSCK0 */ + {RCAR_GP_PIN(1, 14), 24, 3}, /* HRTS0 */ + {RCAR_GP_PIN(1, 13), 20, 3}, /* HCTS0 */ + {RCAR_GP_PIN(1, 12), 16, 3}, /* HTX0 */ + {RCAR_GP_PIN(1, 11), 12, 3}, /* MSIOF0_RXD */ + {RCAR_GP_PIN(1, 10), 8, 3}, /* MSIOF0_SCK */ + {RCAR_GP_PIN(1, 9), 4, 3}, /* MSIOF0_TXD */ + {RCAR_GP_PIN(1, 8), 0, 3}, /* MSIOF0_SYNC */ + }}, + /* DRV2CTRL1 */ + { 0x88, { + {RCAR_GP_PIN(1, 23), 28, 3}, /* GP1_23 */ + {RCAR_GP_PIN(1, 22), 24, 3}, /* AUDIO_CLKIN */ + {RCAR_GP_PIN(1, 21), 20, 3}, /* AUDIO_CLKOUT */ + {RCAR_GP_PIN(1, 20), 16, 3}, /* SSI_SD */ + {RCAR_GP_PIN(1, 19), 12, 3}, /* SSI_WS */ + {RCAR_GP_PIN(1, 18), 8, 3}, /* SSI_SCK */ + {RCAR_GP_PIN(1, 17), 4, 3}, /* SCIF_CLK */ + {RCAR_GP_PIN(1, 16), 0, 3}, /* HRX0 */ + }}, + /* DRV3CTRL1 */ + { 0x8c, { + {RCAR_GP_PIN(1, 28), 16, 3}, /* HTX3 */ + {RCAR_GP_PIN(1, 27), 12, 3}, /* HCTS3# */ + {RCAR_GP_PIN(1, 26), 8, 3}, /* HRTS3# */ + {RCAR_GP_PIN(1, 25), 4, 3}, /* HSCK3 */ + {RCAR_GP_PIN(1, 24), 0, 3}, /* HRX3 */ + }}, + /* DRV0CTRL2 */ + { 0x80, { + {RCAR_GP_PIN(2, 7), 28, 2}, /* TPU0TO1 */ + {RCAR_GP_PIN(2, 6), 24, 2}, /* FXR_TXDB */ + {RCAR_GP_PIN(2, 5), 20, 2}, /* FXR_TXENB */ + {RCAR_GP_PIN(2, 4), 16, 2}, /* RXDB_EXTFXR */ + {RCAR_GP_PIN(2, 3), 12, 2}, /* CLK_EXTFXR */ + {RCAR_GP_PIN(2, 2), 8, 2}, /* RXDA_EXTFXR */ + {RCAR_GP_PIN(2, 1), 4, 2}, /* FXR_TXENA */ + {RCAR_GP_PIN(2, 0), 0, 2}, /* FXR_TXDA */ + }}, + /* DRV1CTRL2 */ + { 0x84, { + {RCAR_GP_PIN(2, 15), 28, 3}, /* CANFD3_RX */ + {RCAR_GP_PIN(2, 14), 24, 2}, /* CANFD3_TX */ + {RCAR_GP_PIN(2, 13), 20, 2}, /* CANFD2_RX */ + {RCAR_GP_PIN(2, 12), 16, 2}, /* CANFD2_TX */ + {RCAR_GP_PIN(2, 11), 12, 2}, /* CANFD0_RX */ + {RCAR_GP_PIN(2, 10), 8, 2}, /* CANFD0_TX */ + {RCAR_GP_PIN(2, 9), 4, 2}, /* CAN_CLK */ + {RCAR_GP_PIN(2, 8), 0, 2}, /* TPU0TO0 */ + }}, + /* DRV2CTRL2 */ + { 0x88, { + {RCAR_GP_PIN(2, 19), 12, 3}, /* CANFD7_RX */ + {RCAR_GP_PIN(2, 18), 8, 3}, /* CANFD7_TX */ + {RCAR_GP_PIN(2, 17), 4, 3}, /* CANFD4_RX */ + {RCAR_GP_PIN(2, 16), 0, 3}, /* CANFD4_TX */ + }}, + /* DRV3CTRL2 is empty */ + /* DRV0CTRL3 */ + { 0x80, { + {RCAR_GP_PIN(3, 7), 28, 3}, /* MMC_D4 */ + {RCAR_GP_PIN(3, 6), 24, 3}, /* MMC_D5 */ + {RCAR_GP_PIN(3, 5), 20, 3}, /* MMC_SD_D3 */ + {RCAR_GP_PIN(3, 4), 16, 3}, /* MMC_DS */ + {RCAR_GP_PIN(3, 3), 12, 3}, /* MMC_SD_CLK */ + {RCAR_GP_PIN(3, 2), 8, 3}, /* MMC_SD_D2 */ + {RCAR_GP_PIN(3, 1), 4, 3}, /* MMC_SD_D0 */ + {RCAR_GP_PIN(3, 0), 0, 3}, /* MMC_SD_D1 */ + }}, + /* DRV1CTRL3 */ + { 0x84, { + {RCAR_GP_PIN(3, 15), 28, 2}, /* QSPI0_SSL */ + {RCAR_GP_PIN(3, 14), 24, 2}, /* IPC_CLKOUT */ + {RCAR_GP_PIN(3, 13), 20, 2}, /* IPC_CLKIN */ + {RCAR_GP_PIN(3, 12), 16, 3}, /* SD_WP */ + {RCAR_GP_PIN(3, 11), 12, 3}, /* SD_CD */ + {RCAR_GP_PIN(3, 10), 8, 3}, /* MMC_SD_CMD */ + {RCAR_GP_PIN(3, 9), 4, 3}, /* MMC_D6 */ + {RCAR_GP_PIN(3, 8), 0, 3}, /* MMC_D7 */ + }}, + /* DRV2CTRL3 */ + { 0x88, { + {RCAR_GP_PIN(3, 23), 28, 2}, /* QSPI1_MISO_IO1 */ + {RCAR_GP_PIN(3, 22), 24, 2}, /* QSPI1_SPCLK */ + {RCAR_GP_PIN(3, 21), 20, 2}, /* QSPI1_MOSI_IO0 */ + {RCAR_GP_PIN(3, 20), 16, 2}, /* QSPI0_SPCLK */ + {RCAR_GP_PIN(3, 19), 12, 2}, /* QSPI0_MOSI_IO0 */ + {RCAR_GP_PIN(3, 18), 8, 2}, /* QSPI0_MISO_IO1 */ + {RCAR_GP_PIN(3, 17), 4, 2}, /* QSPI0_IO2 */ + {RCAR_GP_PIN(3, 16), 0, 2}, /* QSPI0_IO3 */ + }}, + /* DRV3CTRL3 */ + { 0x8c, { + {RCAR_GP_PIN(3, 29), 20, 2}, /* RPC_INT */ + {RCAR_GP_PIN(3, 28), 16, 2}, /* RPC_WP */ + {RCAR_GP_PIN(3, 27), 12, 2}, /* RPC_RESET */ + {RCAR_GP_PIN(3, 26), 8, 2}, /* QSPI1_IO3 */ + {RCAR_GP_PIN(3, 25), 4, 2}, /* QSPI1_SSL */ + {RCAR_GP_PIN(3, 24), 0, 2}, /* QSPI1_IO2 */ + }}, + /* DRV0CTRL4 */ + { 0x80, { + {RCAR_GP_PIN(4, 7), 28, 3}, /* TSN0_RX_CTL */ + {RCAR_GP_PIN(4, 6), 24, 3}, /* TSN0_AVTP_CAPTURE */ + {RCAR_GP_PIN(4, 5), 20, 3}, /* TSN0_AVTP_MATCH */ + {RCAR_GP_PIN(4, 4), 16, 3}, /* TSN0_LINK */ + {RCAR_GP_PIN(4, 3), 12, 3}, /* TSN0_PHY_INT */ + {RCAR_GP_PIN(4, 2), 8, 3}, /* TSN0_AVTP_PPS1 */ + {RCAR_GP_PIN(4, 1), 4, 3}, /* TSN0_MDC */ + {RCAR_GP_PIN(4, 0), 0, 3}, /* TSN0_MDIO */ + }}, + /* DRV1CTRL4 */ + { 0x84, { + {RCAR_GP_PIN(4, 15), 28, 3}, /* TSN0_TD0 */ + {RCAR_GP_PIN(4, 14), 24, 3}, /* TSN0_TD1 */ + {RCAR_GP_PIN(4, 13), 20, 3}, /* TSN0_RD1 */ + {RCAR_GP_PIN(4, 12), 16, 3}, /* TSN0_TXC */ + {RCAR_GP_PIN(4, 11), 12, 3}, /* TSN0_RXC */ + {RCAR_GP_PIN(4, 10), 8, 3}, /* TSN0_RD0 */ + {RCAR_GP_PIN(4, 9), 4, 3}, /* TSN0_TX_CTL */ + {RCAR_GP_PIN(4, 8), 0, 3}, /* TSN0_AVTP_PPS0 */ + }}, + /* DRV2CTRL4 */ + { 0x88, { + {RCAR_GP_PIN(4, 23), 28, 3}, /* AVS0 */ + {RCAR_GP_PIN(4, 22), 24, 3}, /* PCIE1_CLKREQ */ + {RCAR_GP_PIN(4, 21), 20, 3}, /* PCIE0_CLKREQ */ + {RCAR_GP_PIN(4, 20), 16, 3}, /* TSN0_TXCREFCLK */ + {RCAR_GP_PIN(4, 19), 12, 3}, /* TSN0_TD2 */ + {RCAR_GP_PIN(4, 18), 8, 3}, /* TSN0_TD3 */ + {RCAR_GP_PIN(4, 17), 4, 3}, /* TSN0_RD2 */ + {RCAR_GP_PIN(4, 16), 0, 3}, /* TSN0_RD3 */ + }}, + /* DRV3CTRL4 */ + { 0x8c, { + {RCAR_GP_PIN(4, 24), 0, 3}, /* AVS1 */ + }}, + /* DRV0CTRL5 */ + { 0x80, { + {RCAR_GP_PIN(5, 7), 28, 3}, /* AVB2_TXCREFCLK */ + {RCAR_GP_PIN(5, 6), 24, 3}, /* AVB2_MDC */ + {RCAR_GP_PIN(5, 5), 20, 3}, /* AVB2_MAGIC */ + {RCAR_GP_PIN(5, 4), 16, 3}, /* AVB2_PHY_INT */ + {RCAR_GP_PIN(5, 3), 12, 3}, /* AVB2_LINK */ + {RCAR_GP_PIN(5, 2), 8, 3}, /* AVB2_AVTP_MATCH */ + {RCAR_GP_PIN(5, 1), 4, 3}, /* AVB2_AVTP_CAPTURE */ + {RCAR_GP_PIN(5, 0), 0, 3}, /* AVB2_AVTP_PPS */ + }}, + /* DRV1CTRL5 */ + { 0x84, { + {RCAR_GP_PIN(5, 15), 28, 3}, /* AVB2_TD0 */ + {RCAR_GP_PIN(5, 14), 24, 3}, /* AVB2_RD1 */ + {RCAR_GP_PIN(5, 13), 20, 3}, /* AVB2_RD2 */ + {RCAR_GP_PIN(5, 12), 16, 3}, /* AVB2_TD1 */ + {RCAR_GP_PIN(5, 11), 12, 3}, /* AVB2_TD2 */ + {RCAR_GP_PIN(5, 10), 8, 3}, /* AVB2_MDIO */ + {RCAR_GP_PIN(5, 9), 4, 3}, /* AVB2_RD3 */ + {RCAR_GP_PIN(5, 8), 0, 3}, /* AVB2_TD3 */ + }}, + /* DRV2CTRL5 */ + { 0x88, { + {RCAR_GP_PIN(5, 20), 16, 3}, /* AVB2_RX_CTL */ + {RCAR_GP_PIN(5, 19), 12, 3}, /* AVB2_TX_CTL */ + {RCAR_GP_PIN(5, 18), 8, 3}, /* AVB2_RXC */ + {RCAR_GP_PIN(5, 17), 4, 3}, /* AVB2_RD0 */ + {RCAR_GP_PIN(5, 16), 0, 3}, /* AVB2_TXC */ + }}, + /* DRV3CTRL5 is empty */ + /* DRV0CTRL6 */ + { 0x80, { + {RCAR_GP_PIN(6, 7), 28, 3}, /* AVB1_TX_CTL */ + {RCAR_GP_PIN(6, 6), 24, 3}, /* AVB1_TXC */ + {RCAR_GP_PIN(6, 5), 20, 3}, /* AVB1_AVTP_MATCH */ + {RCAR_GP_PIN(6, 4), 16, 3}, /* AVB1_LINK */ + {RCAR_GP_PIN(6, 3), 12, 3}, /* AVB1_PHY_INT */ + {RCAR_GP_PIN(6, 2), 8, 3}, /* AVB1_MDC */ + {RCAR_GP_PIN(6, 1), 4, 3}, /* AVB1_MAGIC */ + {RCAR_GP_PIN(6, 0), 0, 3}, /* AVB1_MDIO */ + }}, + /* DRV1CTRL6 */ + { 0x84, { + {RCAR_GP_PIN(6, 15), 28, 3}, /* AVB1_RD0 */ + {RCAR_GP_PIN(6, 14), 24, 3}, /* AVB1_RD1 */ + {RCAR_GP_PIN(6, 13), 20, 3}, /* AVB1_TD0 */ + {RCAR_GP_PIN(6, 12), 16, 3}, /* AVB1_TD1 */ + {RCAR_GP_PIN(6, 11), 12, 3}, /* AVB1_AVTP_CAPTURE */ + {RCAR_GP_PIN(6, 10), 8, 3}, /* AVB1_AVTP_PPS */ + {RCAR_GP_PIN(6, 9), 4, 3}, /* AVB1_RX_CTL */ + {RCAR_GP_PIN(6, 8), 0, 3}, /* AVB1_RXC */ + }}, + /* DRV2CTRL6 */ + { 0x88, { + {RCAR_GP_PIN(6, 20), 16, 3}, /* AVB1_TXCREFCLK */ + {RCAR_GP_PIN(6, 19), 12, 3}, /* AVB1_RD3 */ + {RCAR_GP_PIN(6, 18), 8, 3}, /* AVB1_TD3 */ + {RCAR_GP_PIN(6, 17), 4, 3}, /* AVB1_RD2 */ + {RCAR_GP_PIN(6, 16), 0, 3}, /* AVB1_TD2 */ + }}, + /* DRV0CTRL7 */ + { 0x80, { + {RCAR_GP_PIN(7, 7), 28, 3}, /* AVB0_TD1 */ + {RCAR_GP_PIN(7, 6), 24, 3}, /* AVB0_TD2 */ + {RCAR_GP_PIN(7, 5), 20, 3}, /* AVB0_PHY_INT */ + {RCAR_GP_PIN(7, 4), 16, 3}, /* AVB0_LINK */ + {RCAR_GP_PIN(7, 3), 12, 3}, /* AVB0_TD3 */ + {RCAR_GP_PIN(7, 2), 8, 3}, /* AVB0_AVTP_MATCH */ + {RCAR_GP_PIN(7, 1), 4, 3}, /* AVB0_AVTP_CAPTURE */ + {RCAR_GP_PIN(7, 0), 0, 3}, /* AVB0_AVTP_PPS */ + }}, + /* DRV1CTRL7 */ + { 0x84, { + {RCAR_GP_PIN(7, 15), 28, 3}, /* AVB0_TXC */ + {RCAR_GP_PIN(7, 14), 24, 3}, /* AVB0_MDIO */ + {RCAR_GP_PIN(7, 13), 20, 3}, /* AVB0_MDC */ + {RCAR_GP_PIN(7, 12), 16, 3}, /* AVB0_RD2 */ + {RCAR_GP_PIN(7, 11), 12, 3}, /* AVB0_TD0 */ + {RCAR_GP_PIN(7, 10), 8, 3}, /* AVB0_MAGIC */ + {RCAR_GP_PIN(7, 9), 4, 3}, /* AVB0_TXCREFCLK */ + {RCAR_GP_PIN(7, 8), 0, 3}, /* AVB0_RD3 */ + }}, + /* DRV2CTRL7 */ + { 0x88, { + {RCAR_GP_PIN(7, 20), 16, 3}, /* AVB0_RX_CTL */ + {RCAR_GP_PIN(7, 19), 12, 3}, /* AVB0_RXC */ + {RCAR_GP_PIN(7, 18), 8, 3}, /* AVB0_RD0 */ + {RCAR_GP_PIN(7, 17), 4, 3}, /* AVB0_RD1 */ + {RCAR_GP_PIN(7, 16), 0, 3}, /* AVB0_TX_CTL */ + }}, + /* DRV0CTRL8 */ + { 0x80, { + {RCAR_GP_PIN(8, 7), 28, 3}, /* SDA3 */ + {RCAR_GP_PIN(8, 6), 24, 3}, /* SCL3 */ + {RCAR_GP_PIN(8, 5), 20, 3}, /* SDA2 */ + {RCAR_GP_PIN(8, 4), 16, 3}, /* SCL2 */ + {RCAR_GP_PIN(8, 3), 12, 3}, /* SDA1 */ + {RCAR_GP_PIN(8, 2), 8, 3}, /* SCL1 */ + {RCAR_GP_PIN(8, 1), 4, 3}, /* SDA0 */ + {RCAR_GP_PIN(8, 0), 0, 3}, /* SCL0 */ + }}, + /* DRV1CTRL8 */ + { 0x84, { + {RCAR_GP_PIN(8, 13), 20, 3}, /* GP8_13 */ + {RCAR_GP_PIN(8, 12), 16, 3}, /* GP8_12 */ + {RCAR_GP_PIN(8, 11), 12, 3}, /* SDA5 */ + {RCAR_GP_PIN(8, 10), 8, 3}, /* SCL5 */ + {RCAR_GP_PIN(8, 9), 4, 3}, /* SDA4 */ + {RCAR_GP_PIN(8, 8), 0, 3}, /* SCL4 */ + }}, + /* DRV0CTRLSYS */ + { 0x80, { + {RCAR_GP_PIN(8, 0), 0, 3}, /* PRESETOUT0# */ + }}, + /* DRV1CTRLSYS */ + { 0x84, { + {PIN_NONE, 12, 2}, /* DCURDY#_LPDCLKOUT */ + {PIN_NONE, 8, 2}, /* DCUTDO_LPDO */ + {PIN_NONE, 0, 2}, /* DCUTMS */ + }}, + {}, +}; + +#define PFC_BIAS_REG(r1, r2) .puen = r1, .pud = r2, .pins = + +/* Set the bit position of a pin in PUENn, PUDn registers */ +const struct pfc_bias_reg pfc_bias_regs[] = { + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN0, PUD0 */ + [0] = RCAR_GP_PIN(0, 0), /* GP0_00 */ + [1] = RCAR_GP_PIN(0, 1), /* GP0_01 */ + [2] = RCAR_GP_PIN(0, 2), /* GP0_02 */ + [3] = RCAR_GP_PIN(0, 3), /* IRQ3 */ + [4] = RCAR_GP_PIN(0, 4), /* IRQ2 */ + [5] = RCAR_GP_PIN(0, 5), /* IRQ1 */ + [6] = RCAR_GP_PIN(0, 6), /* IRQ0 */ + [7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */ + [8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */ + [9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */ + [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */ + [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */ + [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */ + [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */ + [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */ + [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */ + [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */ + [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */ + [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */ + [19] = PIN_NONE, [20] = PIN_NONE, [21] = PIN_NONE, [22] = PIN_NONE, + [23] = PIN_NONE, [24] = PIN_NONE, [25] = PIN_NONE, [26] = PIN_NONE, + [27] = PIN_NONE, [28] = PIN_NONE, [29] = PIN_NONE, [30] = PIN_NONE, + [31] = PIN_NONE, + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN1, PUD1 */ + [0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */ + [1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */ + [2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */ + [3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */ + [4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */ + [5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */ + [6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */ + [7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */ + [8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */ + [9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */ + [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */ + [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */ + [12] = RCAR_GP_PIN(1, 12), /* HTX0 */ + [13] = RCAR_GP_PIN(1, 13), /* HCTS0# */ + [14] = RCAR_GP_PIN(1, 14), /* HRTS0# */ + [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */ + [16] = RCAR_GP_PIN(1, 16), /* HRX0 */ + [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */ + [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */ + [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */ + [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */ + [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */ + [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */ + [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */ + [24] = RCAR_GP_PIN(1, 24), /* HRX3 */ + [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */ + [26] = RCAR_GP_PIN(1, 26), /* HRTS3# */ + [27] = RCAR_GP_PIN(1, 27), /* HCTS3# */ + [28] = RCAR_GP_PIN(1, 28), /* HTX3 */ + [29] = PIN_NONE, [30] = PIN_NONE, [31] = PIN_NONE, + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN2, PUD2 */ + [0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */ + [1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA# */ + [2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */ + [3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */ + [4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */ + [5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB# */ + [6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */ + [7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */ + [8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */ + [9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */ + [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */ + [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */ + [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */ + [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */ + [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */ + [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */ + [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */ + [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */ + [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */ + [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */ + [20] = RCAR_GP_PIN(2, 20), /* - */ + [21] = RCAR_GP_PIN(2, 21), /* - */ + [22] = RCAR_GP_PIN(2, 22), /* - */ + [23] = RCAR_GP_PIN(2, 23), /* - */ + [24] = RCAR_GP_PIN(2, 24), /* - */ + [25] = RCAR_GP_PIN(2, 25), /* - */ + [26] = RCAR_GP_PIN(2, 26), /* - */ + [27] = RCAR_GP_PIN(2, 27), /* - */ + [28] = RCAR_GP_PIN(2, 28), /* - */ + [29] = RCAR_GP_PIN(2, 29), /* - */ + [30] = RCAR_GP_PIN(2, 30), /* - */ + [31] = RCAR_GP_PIN(2, 31), /* - */ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN3, PUD3 */ + [0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */ + [1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */ + [2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */ + [3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */ + [4] = RCAR_GP_PIN(3, 4), /* MMC_DS */ + [5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */ + [6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */ + [7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */ + [8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */ + [9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */ + [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */ + [11] = RCAR_GP_PIN(3, 11), /* SD_CD */ + [12] = RCAR_GP_PIN(3, 12), /* SD_WP */ + [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */ + [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */ + [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */ + [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */ + [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */ + [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */ + [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */ + [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */ + [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */ + [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */ + [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */ + [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */ + [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */ + [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */ + [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET# */ + [28] = RCAR_GP_PIN(3, 28), /* RPC_WP# */ + [29] = RCAR_GP_PIN(3, 29), /* RPC_INT# */ + [30] = PIN_NONE, /* - */ + [31] = PIN_NONE, /* - */ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN4, PUD4 */ + [0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO*/ + [1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC*/ + [2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1*/ + [3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT*/ + [4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK*/ + [5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH*/ + [6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE*/ + [7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL*/ + [8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0*/ + [9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL*/ + [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0*/ + [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC*/ + [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC*/ + [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1*/ + [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1*/ + [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0*/ + [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3*/ + [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2*/ + [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3*/ + [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2*/ + [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK*/ + [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ#*/ + [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ#*/ + [23] = RCAR_GP_PIN(4, 23), /* AVS0*/ + [24] = RCAR_GP_PIN(4, 24), /* AVS1*/ + [25] = PIN_NONE, /* -*/ + [26] = PIN_NONE, /* -*/ + [27] = PIN_NONE, /* -*/ + [28] = PIN_NONE, /* -*/ + [29] = PIN_NONE, /* -*/ + [30] = PIN_NONE, /* -*/ + [31] = PIN_NONE /* -*/ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN5, PUD5 */ + [0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS*/ + [1] = RCAR_GP_PIN(5, 1), /* AVB2_AVTP_CAPTURE*/ + [2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH*/ + [3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK*/ + [4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT*/ + [5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC*/ + [6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC*/ + [7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK*/ + [8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3*/ + [9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3*/ + [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO*/ + [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2*/ + [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1*/ + [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2*/ + [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1*/ + [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0*/ + [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC*/ + [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0*/ + [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC*/ + [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL*/ + [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL*/ + [21] = PIN_NONE, /* -*/ + [22] = PIN_NONE, /* -*/ + [23] = PIN_NONE, /* -*/ + [24] = PIN_NONE, /* -*/ + [25] = PIN_NONE, /* -*/ + [26] = PIN_NONE, /* -*/ + [27] = PIN_NONE, /* -*/ + [28] = PIN_NONE, /* -*/ + [29] = PIN_NONE, /* -*/ + [30] = PIN_NONE, /* -*/ + [31] = PIN_NONE /* -*/ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN6, PUD6 */ + [0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */ + [1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */ + [2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */ + [3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */ + [4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */ + [5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */ + [6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */ + [7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */ + [8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */ + [9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */ + [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */ + [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */ + [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */ + [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */ + [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1 */ + [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */ + [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */ + [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */ + [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */ + [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */ + [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */ + [21] = PIN_NONE, /* - */ + [22] = PIN_NONE, /* - */ + [23] = PIN_NONE, /* - */ + [24] = PIN_NONE, /* - */ + [25] = PIN_NONE, /* - */ + [26] = PIN_NONE, /* - */ + [27] = PIN_NONE, /* - */ + [28] = PIN_NONE, /* - */ + [29] = PIN_NONE, /* - */ + [30] = PIN_NONE, /* - */ + [31] = PIN_NONE, /* - */ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN7, PUD7 */ + [0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */ + [1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */ + [2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */ + [3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */ + [4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */ + [5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */ + [6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */ + [7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */ + [8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */ + [9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */ + [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */ + [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */ + [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */ + [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */ + [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */ + [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */ + [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */ + [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */ + [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */ + [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */ + [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */ + [21] = PIN_NONE, /* - */ + [22] = PIN_NONE, /* - */ + [23] = PIN_NONE, /* - */ + [24] = PIN_NONE, /* - */ + [25] = PIN_NONE, /* - */ + [26] = PIN_NONE, /* - */ + [27] = PIN_NONE, /* - */ + [28] = PIN_NONE, /* - */ + [29] = PIN_NONE, /* - */ + [30] = PIN_NONE, /* - */ + [31] = PIN_NONE, /* - */ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUEN8, PUD8 */ + [0] = RCAR_GP_PIN(8, 0), /* SCL0 */ + [1] = RCAR_GP_PIN(8, 1), /* SDA0 */ + [2] = RCAR_GP_PIN(8, 2), /* SCL1 */ + [3] = RCAR_GP_PIN(8, 3), /* SDA1 */ + [4] = RCAR_GP_PIN(8, 4), /* SCL2 */ + [5] = RCAR_GP_PIN(8, 5), /* SDA2 */ + [6] = RCAR_GP_PIN(8, 6), /* SCL3 */ + [7] = RCAR_GP_PIN(8, 7), /* SDA3 */ + [8] = RCAR_GP_PIN(8, 8), /* SCL4 */ + [9] = RCAR_GP_PIN(8, 9), /* SDA4 */ + [10] = RCAR_GP_PIN(8, 10), /* SCL5 */ + [11] = RCAR_GP_PIN(8, 11), /* SDA5 */ + [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */ + [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */ + [14] = PIN_NONE, /* - */ + [15] = PIN_NONE, /* - */ + [16] = PIN_NONE, /* - */ + [17] = PIN_NONE, /* - */ + [18] = PIN_NONE, /* - */ + [19] = PIN_NONE, /* - */ + [20] = PIN_NONE, /* - */ + [21] = PIN_NONE, /* - */ + [22] = PIN_NONE, /* - */ + [23] = PIN_NONE, /* - */ + [24] = PIN_NONE, /* - */ + [25] = PIN_NONE, /* - */ + [26] = PIN_NONE, /* - */ + [27] = PIN_NONE, /* - */ + [28] = PIN_NONE, /* - */ + [29] = PIN_NONE, /* - */ + [30] = PIN_NONE, /* - */ + [31] = PIN_NONE, /* - */ + }}, + {PFC_BIAS_REG(0xc0, 0xe0) { + /* PUENsys, PUDsys */ + [0] = PIN_NONE, /* PRESETOUT_N */ + [1] = PIN_NONE, /* - */ + [2] = PIN_NONE, /* - */ + [3] = PIN_NONE, /* - */ + [4] = PIN_NONE, /* EXTALR */ + [5] = PIN_NONE, /* - */ + [6] = PIN_NONE, /* DCUTRST_N_LPDRST_N */ + [7] = PIN_NONE, /* DCUTCK_LPDCLK */ + [8] = PIN_NONE, /* DCUTMS */ + [9] = PIN_NONE, /* DCUTDI_LPDI */ + [10] = PIN_NONE, /* - */ + [11] = PIN_NONE, /* - */ + [12] = PIN_NONE, /* - */ + [13] = PIN_NONE, /* - */ + [14] = PIN_NONE, /* - */ + [15] = PIN_NONE, /* - */ + [16] = PIN_NONE, /* - */ + [17] = PIN_NONE, /* - */ + [18] = PIN_NONE, /* - */ + [19] = PIN_NONE, /* - */ + [20] = PIN_NONE, /* - */ + [21] = PIN_NONE, /* - */ + [22] = PIN_NONE, /* - */ + [23] = PIN_NONE, /* - */ + [24] = PIN_NONE, /* - */ + [25] = PIN_NONE, /* - */ + [26] = PIN_NONE, /* - */ + [27] = PIN_NONE, /* - */ + [28] = PIN_NONE, /* - */ + [29] = PIN_NONE, /* - */ + [30] = PIN_NONE, /* - */ + [31] = PIN_NONE, /* - */ + }}, + {/* sentinel */}, +}; + +const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) +{ + return pfc_bias_regs; +} + +const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) +{ + return pfc_drive_regs; +} + +int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index) +{ + if (RCAR_IS_GP_PIN(pin) == false) { + return -EINVAL; + } + + *reg_index = pin / 32; + + return 0; +} diff --git a/dts/arm/renesas/rcar/gen4/r8a779g0.dtsi b/dts/arm/renesas/rcar/gen4/r8a779g0.dtsi new file mode 100644 index 0000000000000..d80c245065ad1 --- /dev/null +++ b/dts/arm/renesas/rcar/gen4/r8a779g0.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + pfc: pin-controller@e6050000 { + compatible = "renesas,rcar-pfc"; + reg = <0xe6050000 0x1d8>, <0xe6050800 0x1d8>, + <0xe6058000 0x1d8>, <0xe6058800 0x1d8>, + <0xe6060000 0x1d8>, <0xe6060800 0x1d8>, + <0xe6061000 0x1d8>, <0xe6061800 0x1d8>, + <0xe6068000 0x1d8>, <0xe6078000 0x0e8>; + }; + + /* Using domain 0 */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779g0-cpg-mssr"; + reg = <0xe6150000 0x2e78>; + #clock-cells = <2>; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,rcar-gpio"; + reg = <0xe6050000 0x1D8>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + status = "disabled"; + }; + + gpio1: gpio@e6050800 { + compatible = "renesas,rcar-gpio"; + reg = <0xe6050800 0x1D8>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + interrupts = ; + clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>; + }; + + hscif1: serial@e6550000 { + interrupts = ; + clocks = <&cpg CPG_MOD 515>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>; + }; + }; +}; diff --git a/dts/arm/renesas/rcar/gen4/rcar_gen4_v4h_cr52.dtsi b/dts/arm/renesas/rcar/gen4/rcar_gen4_v4h_cr52.dtsi new file mode 100644 index 0000000000000..f530893065973 --- /dev/null +++ b/dts/arm/renesas/rcar/gen4/rcar_gen4_v4h_cr52.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <16666667>; + }; + + soc { + interrupt-parent = <&gic>; + + sram0: memory@40040000 { + compatible = "mmio-sram"; + reg = <0x40040000 0x400000>; + }; + + gic: interrupt-controller@f0000000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0xf0000000 0x1000>, + <0xf0100000 0x20000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,rcar-hscif"; + reg = <0xe6540000 0x64>; + current-speed = <921600>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,rcar-hscif"; + reg = <0xe6550000 0x64>; + current-speed = <921600>; + status = "disabled"; + }; + }; +}; diff --git a/dts/bindings/clock/renesas,r8a779g0-cpg-mssr.yaml b/dts/bindings/clock/renesas,r8a779g0-cpg-mssr.yaml new file mode 100644 index 0000000000000..615fd905c83d9 --- /dev/null +++ b/dts/bindings/clock/renesas,r8a779g0-cpg-mssr.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas R8A779G0 SoC Clock Pulse Generator / Module Standby and Software Reset + +compatible: "renesas,r8a779g0-cpg-mssr" + +include: renesas,rcar-cpg-mssr.yaml diff --git a/dts/bindings/timer/arm,armv8-timer.yaml b/dts/bindings/timer/arm,armv8-timer.yaml index 6b8400c4616e4..62f93299e3f7a 100644 --- a/dts/bindings/timer/arm,armv8-timer.yaml +++ b/dts/bindings/timer/arm,armv8-timer.yaml @@ -7,3 +7,5 @@ include: base.yaml properties: interrupts: required: true + clock-frequency: + type: int diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index f9b987895f8c0..5d103613eaa89 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -578,6 +578,7 @@ remarkable reMarkable AS renesas Renesas Electronics Corporation renode Antmicro's open source simulation and virtual development framework rervision Shenzhen Rervision Technology Co., Ltd. +retronix Retronix Technology Inc. revotics Revolution Robotics, Inc. (Revotics) rex iMX6 Rex Project reyax Reyax Technology Co., Ltd. diff --git a/include/zephyr/dt-bindings/clock/r8a779g0_cpg_mssr.h b/include/zephyr/dt-bindings/clock/r8a779g0_cpg_mssr.h new file mode 100644 index 0000000000000..7e16a0aef230c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/r8a779g0_cpg_mssr.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_ + +#include "renesas_cpg_mssr.h" + +/* r8a779g0 CPG Core Clocks */ +#define R8A779G0_CLK_Z0 0 +#define R8A779G0_CLK_Z1 1 +#define R8A779G0_CLK_Z2 2 +#define R8A779G0_CLK_ZG 3 +#define R8A779G0_CLK_ZR 4 +#define R8A779G0_CLK_ZX 5 +#define R8A779G0_CLK_ZS 6 +#define R8A779G0_CLK_ZT 7 +#define R8A779G0_CLK_ZTR 8 + +#define R8A779G0_CLK_S0 9 +#define R8A779G0_CLK_S0D2 10 +#define R8A779G0_CLK_S0D3 11 +#define R8A779G0_CLK_S0D4 12 + +#define R8A779G0_CLK_S0VIO 13 +#define R8A779G0_CLK_S0D1_VIO 14 +#define R8A779G0_CLK_S0D2_VIO 15 +#define R8A779G0_CLK_S0D4_VIO 16 +#define R8A779G0_CLK_S0D8_VIO 17 + +#define R8A779G0_CLK_S0VC 18 +#define R8A779G0_CLK_S0D1_VC 19 +#define R8A779G0_CLK_S0D2_VC 20 +#define R8A779G0_CLK_S0D4_VC 21 + +#define R8A779G0_CLK_S0D2_MM 22 +#define R8A779G0_CLK_S0D4_MM 23 + +#define R8A779G0_CLK_S0D2_U3DG 24 +#define R8A779G0_CLK_S0D4_U3DG 25 + +#define R8A779G0_CLK_S0D2_RT 26 +#define R8A779G0_CLK_S0D3_RT 27 +#define R8A779G0_CLK_S0D4_RT 28 +#define R8A779G0_CLK_S0D6_RT 29 +#define R8A779G0_CLK_S0D24_RT 30 + +#define R8A779G0_CLK_S0D2_PER 31 +#define R8A779G0_CLK_S0D3_PER 32 +#define R8A779G0_CLK_S0D4_PER 33 +#define R8A779G0_CLK_S0D6_PER 34 +#define R8A779G0_CLK_S0D12_PER 35 +#define R8A779G0_CLK_S0D24_PER 36 + +#define R8A779G0_CLK_S0_HSC 37 +#define R8A779G0_CLK_S0D1_HSC 38 +#define R8A779G0_CLK_S0D2_HSC 39 +#define R8A779G0_CLK_S0D4_HSC 40 +#define R8A779G0_CLK_S0D8_HSC 41 + +#define R8A779G0_CLK_S0D2_CC 42 +#define R8A779G0_CLK_SV_IR 43 +#define R8A779G0_CLK_SVD1_IR 44 +#define R8A779G0_CLK_SVD2_IR 45 +#define R8A779G0_CLK_IMPA0 46 +#define R8A779G0_CLK_SV_VIP 47 +#define R8A779G0_CLK_SVD1_VIP 48 +#define R8A779G0_CLK_SVD2_VIP 49 + +#define R8A779G0_CLK_CL 50 +#define R8A779G0_CLK_CL16M 51 +#define R8A779G0_CLK_CL16M_MM 52 +#define R8A779G0_CLK_CL16M_RT 53 +#define R8A779G0_CLK_CL16M_PER 54 +#define R8A779G0_CLK_CL16M_HSC 55 + +#define R8A779G0_CLK_ZB3 56 +#define R8A779G0_CLK_ZB3D2 57 +#define R8A779G0_CLK_ZB3D4 58 + +#define R8A779G0_CLK_SDSRC 59 +#define R8A779G0_CLK_SD0H 60 +#define R8A779G0_CLK_SD0 61 +#define R8A779G0_CLK_RPC 62 +#define R8A779G0_CLK_RPCD2 63 +#define R8A779G0_CLK_MSO 64 +#define R8A779G0_CLK_CANFD 65 +#define R8A779G0_CLK_CSI 66 +#define R8A779G0_CLK_FRAY 67 +#define R8A779G0_CLK_IPC 68 +#define R8A779G0_CLK_POST2 69 +#define R8A779G0_CLK_POST3 70 +#define R8A779G0_CLK_POST4 71 +#define R8A779G0_CLK_POST 72 + +#define R8A779G0_CLK_SASYNCRT 73 +#define R8A779G0_CLK_SASYNCPERD1 74 +#define R8A779G0_CLK_SASYNCPERD2 75 +#define R8A779G0_CLK_SASYNCPERD4 76 + +#define R8A779G0_CLK_VIOBUS 77 +#define R8A779G0_CLK_VIOBUSD2 78 +#define R8A779G0_CLK_VCBUS 79 +#define R8A779G0_CLK_VCBUSD2 80 +#define R8A779G0_CLK_IMPA1 81 +#define R8A779G0_CLK_DSIREF 82 +#define R8A779G0_CLK_ADGH 83 + +#define R8A779G0_CLK_OSCCLK 84 +#define R8A779G0_CLK_IMPA 85 +#define R8A779G0_CLK_IMPAD4 86 +#define R8A779G0_CLK_CPEX 87 +#define R8A779G0_CLK_CP 88 +#define R8A779G0_CLK_CBFUSA 89 +#define R8A779G0_CLK_RCLK 90 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779g0.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779g0.h new file mode 100644 index 0000000000000..31d253685a6ea --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779g0.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779G0_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779G0_H_ + +#include "pinctrl-rcar-common.h" + +/* Pins declaration */ +#define PIN_NONE -1 + +#define PIN_GP0_00 RCAR_GP_PIN(0, 0) +#define PIN_GP0_01 RCAR_GP_PIN(0, 1) +#define PIN_GP0_02 RCAR_GP_PIN(0, 2) +#define PIN_IRQ3 RCAR_GP_PIN(0, 3) +#define PIN_IRQ2 RCAR_GP_PIN(0, 4) +#define PIN_IRQ1 RCAR_GP_PIN(0, 5) +#define PIN_IRQ0 RCAR_GP_PIN(0, 6) +#define PIN_MSIOF5_SS2 RCAR_GP_PIN(0, 7) +#define PIN_MSIOF5_SS1 RCAR_GP_PIN(0, 8) +#define PIN_MSIOF5_SYNC RCAR_GP_PIN(0, 9) +#define PIN_MSIOF5_TXD RCAR_GP_PIN(0, 10) +#define PIN_MSIOF5_SCK RCAR_GP_PIN(0, 11) +#define PIN_MSIOF5_RXD RCAR_GP_PIN(0, 12) +#define PIN_MSIOF2_SS2 RCAR_GP_PIN(0, 13) +#define PIN_MSIOF2_SS1 RCAR_GP_PIN(0, 14) +#define PIN_MSIOF2_SYNC RCAR_GP_PIN(0, 15) +#define PIN_MSIOF2_TXD RCAR_GP_PIN(0, 16) +#define PIN_MSIOF2_SCK RCAR_GP_PIN(0, 17) +#define PIN_MSIOF2_RXD RCAR_GP_PIN(0, 18) + +#define PIN_MSIOF1_SS2 RCAR_GP_PIN(1, 0) +#define PIN_MSIOF1_SS1 RCAR_GP_PIN(1, 1) +#define PIN_MSIOF1_SYNC RCAR_GP_PIN(1, 2) +#define PIN_MSIOF1_SCK RCAR_GP_PIN(1, 3) +#define PIN_MSIOF1_TXD RCAR_GP_PIN(1, 4) +#define PIN_MSIOF1_RXD RCAR_GP_PIN(1, 5) +#define PIN_MSIOF0_SS2 RCAR_GP_PIN(1, 6) +#define PIN_MSIOF0_SS1 RCAR_GP_PIN(1, 7) +#define PIN_MSIOF0_SYNC RCAR_GP_PIN(1, 8) +#define PIN_MSIOF0_TXD RCAR_GP_PIN(1, 9) +#define PIN_MSIOF0_SCK RCAR_GP_PIN(1, 10) +#define PIN_MSIOF0_RXD RCAR_GP_PIN(1, 11) +#define PIN_HTX0 RCAR_GP_PIN(1, 12) +#define PIN_HCTS0_N RCAR_GP_PIN(1, 13) +#define PIN_HRTS0_N RCAR_GP_PIN(1, 14) +#define PIN_HSCK0 RCAR_GP_PIN(1, 15) +#define PIN_HRX0 RCAR_GP_PIN(1, 16) +#define PIN_SCIF_CLK RCAR_GP_PIN(1, 17) +#define PIN_SSI_SCK RCAR_GP_PIN(1, 18) +#define PIN_SSI_WS RCAR_GP_PIN(1, 19) +#define PIN_SSI_SD RCAR_GP_PIN(1, 20) +#define PIN_AUDIO_CLKOUT RCAR_GP_PIN(1, 21) +#define PIN_AUDIO_CLKIN RCAR_GP_PIN(1, 22) +#define PIN_GP1_23 RCAR_GP_PIN(1, 23) +#define PIN_HRX3 RCAR_GP_PIN(1, 24) +#define PIN_HSCK3 RCAR_GP_PIN(1, 25) +#define PIN_HRTS3_N RCAR_GP_PIN(1, 26) +#define PIN_HCTS3_N RCAR_GP_PIN(1, 27) +#define PIN_HTX3 RCAR_GP_PIN(1, 28) + +#define PIN_FXR_TXDA RCAR_GP_PIN(2, 0) +#define PIN_FXR_TXENA_N RCAR_GP_PIN(2, 1) +#define PIN_RXDA_EXTFXR RCAR_GP_PIN(2, 2) +#define PIN_CLK_EXTFXR RCAR_GP_PIN(2, 3) +#define PIN_RXDB_EXTFXR RCAR_GP_PIN(2, 4) +#define PIN_FXR_TXENB_N RCAR_GP_PIN(2, 5) +#define PIN_FXR_TXDB RCAR_GP_PIN(2, 6) +#define PIN_TPU0T01 RCAR_GP_PIN(2, 7) +#define PIN_TPU0T00 RCAR_GP_PIN(2, 8) +#define PIN_CAN_CLK RCAR_GP_PIN(2, 9) +#define PIN_CANFD0_TX RCAR_GP_PIN(2, 10) +#define PIN_CANFD0_RX RCAR_GP_PIN(2, 11) +#define PIN_CANFD2_TX RCAR_GP_PIN(2, 12) +#define PIN_CANFD2_RX RCAR_GP_PIN(2, 13) +#define PIN_CANFD3_TX RCAR_GP_PIN(2, 14) +#define PIN_CANFD3_RX RCAR_GP_PIN(2, 15) +#define PIN_CANFD4_TX RCAR_GP_PIN(2, 16) +#define PIN_CANFD4_RX RCAR_GP_PIN(2, 17) +#define PIN_CANFD7_TX RCAR_GP_PIN(2, 18) +#define PIN_CANFD7_RX RCAR_GP_PIN(2, 19) + +#define PIN_MMC_SD_D1 RCAR_GP_PIN(3, 0) +#define PIN_MMC_SD_D0 RCAR_GP_PIN(3, 1) +#define PIN_MMC_SD_D2 RCAR_GP_PIN(3, 2) +#define PIN_MMC_SD_CLK RCAR_GP_PIN(3, 3) +#define PIN_MMC_DS RCAR_GP_PIN(3, 4) +#define PIN_MMC_SD_D3 RCAR_GP_PIN(3, 5) +#define PIN_MMC_D5 RCAR_GP_PIN(3, 6) +#define PIN_MMC_D4 RCAR_GP_PIN(3, 7) +#define PIN_MMC_D7 RCAR_GP_PIN(3, 8) +#define PIN_MMC_D6 RCAR_GP_PIN(3, 9) +#define PIN_MMC_SD_CMD RCAR_GP_PIN(3, 10) +#define PIN_SD_CD RCAR_GP_PIN(3, 11) +#define PIN_SD_WP RCAR_GP_PIN(3, 12) +#define PIN_IPC_CLKIN RCAR_GP_PIN(3, 13) +#define PIN_IPC_CLKOUT RCAR_GP_PIN(3, 14) +#define PIN_QSPI0_SSL RCAR_GP_PIN(3, 15) +#define PIN_QSPI0_IO3 RCAR_GP_PIN(3, 16) +#define PIN_QSPI0_IO2 RCAR_GP_PIN(3, 17) +#define PIN_QSPI0_MISO_IO1 RCAR_GP_PIN(3, 18) +#define PIN_QSPI0_MOSI_IO0 RCAR_GP_PIN(3, 19) +#define PIN_QSPI0_SPCLK RCAR_GP_PIN(3, 20) +#define PIN_QSPI1_MOSI_IO0 RCAR_GP_PIN(3, 21) +#define PIN_QSPI1_SPCLK RCAR_GP_PIN(3, 22) +#define PIN_QSPI1_MISO_IO1 RCAR_GP_PIN(3, 23) +#define PIN_QSPI1_IO2 RCAR_GP_PIN(3, 24) +#define PIN_QSPI1_SSL RCAR_GP_PIN(3, 25) +#define PIN_QSPI1_IO3 RCAR_GP_PIN(3, 26) +#define PIN_RPC_RESET_N RCAR_GP_PIN(3, 27) +#define PIN_RPC_WP_N RCAR_GP_PIN(3, 28) +#define PIN_RPC_INT_N RCAR_GP_PIN(3, 29) + +#define PIN_TSN0_MDIO RCAR_GP_PIN(4, 0) +#define PIN_TSN0_MDC RCAR_GP_PIN(4, 1) +#define PIN_TSN0_AVTP_PPS1 RCAR_GP_PIN(4, 2) +#define PIN_TSN0_PHY_INT RCAR_GP_PIN(4, 3) +#define PIN_TSN0_LINK RCAR_GP_PIN(4, 4) +#define PIN_TSN0_AVTP_MATCH RCAR_GP_PIN(4, 5) +#define PIN_TSN0_AVTP_CAPTURE RCAR_GP_PIN(4, 6) +#define PIN_TSN0_RX_CTL RCAR_GP_PIN(4, 7) +#define PIN_TSN0_AVTP_PPS0 RCAR_GP_PIN(4, 8) +#define PIN_TSN0_TX_CTL RCAR_GP_PIN(4, 9) +#define PIN_TSN0_RD0 RCAR_GP_PIN(4, 10) +#define PIN_TSN0_RXC RCAR_GP_PIN(4, 11) +#define PIN_TSN0_TXC RCAR_GP_PIN(4, 12) +#define PIN_TSN0_RD1 RCAR_GP_PIN(4, 13) +#define PIN_TSN0_TD1 RCAR_GP_PIN(4, 14) +#define PIN_TSN0_TD0 RCAR_GP_PIN(4, 15) +#define PIN_TSN0_RD3 RCAR_GP_PIN(4, 16) +#define PIN_TSN0_RD2 RCAR_GP_PIN(4, 17) +#define PIN_TSN0_TD3 RCAR_GP_PIN(4, 18) +#define PIN_TSN0_TD2 RCAR_GP_PIN(4, 19) +#define PIN_TSN0_TXCREFCLK RCAR_GP_PIN(4, 20) +#define PIN_PCIE0_CLKREQ_N RCAR_GP_PIN(4, 21) +#define PIN_PCIE1_CLKREQ_N RCAR_GP_PIN(4, 22) +#define PIN_AVS0 RCAR_GP_PIN(4, 23) +#define PIN_AVS1 RCAR_GP_PIN(4, 24) + +#define PIN_AVB2_AVTP_PPS RCAR_GP_PIN(5, 0) +#define PIN_AVB2_AVTP_CAPTURE RCAR_GP_PIN(5, 1) +#define PIN_AVB2_AVTP_MATCH RCAR_GP_PIN(5, 2) +#define PIN_AVB2_LINK RCAR_GP_PIN(5, 3) +#define PIN_AVB2_PHY_INT RCAR_GP_PIN(5, 4) +#define PIN_AVB2_MAGIC RCAR_GP_PIN(5, 5) +#define PIN_AVB2_MDC RCAR_GP_PIN(5, 6) +#define PIN_AVB2_TXCREFCLK RCAR_GP_PIN(5, 7) +#define PIN_AVB2_TD3 RCAR_GP_PIN(5, 8) +#define PIN_AVB2_RD3 RCAR_GP_PIN(5, 9) +#define PIN_AVB2_MDIO RCAR_GP_PIN(5, 10) +#define PIN_AVB2_TD2 RCAR_GP_PIN(5, 11) +#define PIN_AVB2_TD1 RCAR_GP_PIN(5, 12) +#define PIN_AVB2_RD1 RCAR_GP_PIN(5, 13) +#define PIN_AVB2_RD2 RCAR_GP_PIN(5, 14) +#define PIN_AVB2_TD0 RCAR_GP_PIN(5, 15) +#define PIN_AVB2_TXC RCAR_GP_PIN(5, 16) +#define PIN_AVB2_RD0 RCAR_GP_PIN(5, 17) +#define PIN_AVB2_RXC RCAR_GP_PIN(5, 18) +#define PIN_AVB2_TX_CTL RCAR_GP_PIN(5, 19) +#define PIN_AVB2_RX_CTL RCAR_GP_PIN(5, 20) + +#define PIN_SCL0 RCAR_GP_PIN(8, 0) +#define PIN_SDA0 RCAR_GP_PIN(8, 1) +#define PIN_SCL1 RCAR_GP_PIN(8, 2) +#define PIN_SDA1 RCAR_GP_PIN(8, 3) +#define PIN_SCL2 RCAR_GP_PIN(8, 4) +#define PIN_SDA2 RCAR_GP_PIN(8, 5) +#define PIN_SCL3 RCAR_GP_PIN(8, 6) +#define PIN_SDA3 RCAR_GP_PIN(8, 7) +#define PIN_SCL4 RCAR_GP_PIN(8, 8) +#define PIN_SDA4 RCAR_GP_PIN(8, 9) +#define PIN_SCL5 RCAR_GP_PIN(8, 10) +#define PIN_SDA5 RCAR_GP_PIN(8, 11) +#define PIN_GP8_12 RCAR_GP_PIN(8, 12) +#define PIN_GP8_13 RCAR_GP_PIN(8, 13) + +/* Pinmux function declarations */ +#define FUNC_HTX1 IP1SR0(24, 0x1) +#define FUNC_HRX1 IP1SR0(28, 0x1) +#define FUNC_HCTS1 IP2SR0(0, 0x1) +#define FUNC_HRTS1 IP2SR0(4, 0x1) +#define FUNC_MSIOF1_SYNC IP0SR1(8, 0x0) +#define FUNC_MSIOF1_SCK IP0SR1(12, 0x0) +#define FUNC_MSIOF1_TXD IP0SR1(16, 0x0) +#define FUNC_MSIOF1_RXD IP0SR1(20, 0x0) +#define FUNC_MSIOF0_SS1 IP0SR1(28, 0x0) +#define FUNC_MSIOF0_SYNC IP1SR1(0, 0x0) +#define FUNC_MSIOF0_TXD IP1SR1(4, 0x0) +#define FUNC_MSIOF0_SCK IP1SR1(8, 0x0) +#define FUNC_MSIOF0_RXD IP1SR1(12, 0x0) +#define FUNC_TX0 IP1SR1(16, 0x1) +#define FUNC_HTX0 IP1SR1(16, 0x0) +#define FUNC_HCTS0 IP1SR1(20, 0x1) +#define FUNC_HRTS0 IP1SR1(24, 0x1) +#define FUNC_PWM0 IP1SR1(28, 0x2) +#define FUNC_HRX0 IP2SR1(0, 0x0) +#define FUNC_RX0 IP2SR1(0, 0x1) +#define FUNC_SCIF_CLK IP2SR1(4, 0x0) +#define FUNC_AUDIO_CLKOUT IP2SR1(20, 0x0) +#define FUNC_TPU0TO0 IP3SR1(4, 0x3) +#define FUNC_TPU0TO1 IP3SR1(8, 0x3) +#define FUNC_CAN_CLK IP1SR2(4, 0x0) +#define FUNC_CANFD3_TX IP1SR2(24, 0x0) +#define FUNC_CANFD3_RX IP1SR2(28, 0x0) +#define FUNC_CANFD4_TX IP2SR2(0, 0x0) +#define FUNC_CANFD4_RX IP2SR2(4, 0x0) +#define FUNC_MMC_SD_D1 IP0SR3(0, 0x0) +#define FUNC_MMC_SD_D0 IP0SR3(4, 0x0) +#define FUNC_MMC_SD_D2 IP0SR3(8, 0x0) +#define FUNC_MMC_SD_CLK IP0SR3(12, 0x0) +#define FUNC_MMC_DS IP0SR3(16, 0x0) +#define FUNC_MMC_SD_D3 IP0SR3(20, 0x0) +#define FUNC_MMC_D5 IP0SR3(24, 0x0) +#define FUNC_MMC_D4 IP0SR3(28, 0x0) +#define FUNC_MMC_D7 IP1SR3(0, 0x0) +#define FUNC_MMC_D6 IP1SR3(4, 0x0) +#define FUNC_MMC_SD_CMD IP1SR3(8, 0x0) +#define FUNC_SD_CD IP1SR3(12, 0x0) +#define FUNC_SD_WP IP1SR3(16, 0x0) +#define FUNC_QSPI0_SSL IP1SR3(28, 0x0) +#define FUNC_QSPI0_IO3 IP2SR3(0, 0x0) +#define FUNC_QSPI0_IO2 IP2SR3(4, 0x0) +#define FUNC_QSPI0_MISO_IO1 IP2SR3(8, 0x0) +#define FUNC_QSPI0_MOSI_IO0 IP2SR3(12, 0x0) +#define FUNC_QSPI0_SPCLK IP2SR3(16, 0x0) +#define FUNC_QSPI1_MOSI_IO0 IP2SR3(20, 0x0) +#define FUNC_QSPI1_SPCLK IP2SR3(24, 0x0) +#define FUNC_QSPI1_MISO_IO1 IP2SR3(28, 0x0) +#define FUNC_QSPI1_IO2 IP3SR3(0, 0x0) +#define FUNC_QSPI1_SSL IP3SR3(4, 0x0) +#define FUNC_QSPI1_IO3 IP3SR3(8, 0x0) +#define FUNC_RPC_RESET IP3SR3(12, 0x0) +#define FUNC_RPC_WP IP3SR3(16, 0x0) +#define FUNC_RPC_INT IP3SR3(20, 0x0) +#define FUNC_PCIE0_CLKREQ IP2SR4(20, 0x0) +#define FUNC_PCIE1_CLKREQ IP2SR4(24, 0x0) +#define FUNC_AVS0 IP2SR4(28, 0x0) +#define FUNC_AVS1 IP3SR4(0, 0x0) +#define FUNC_AVB0_AVTP_PPS IP0SR7(0, 0x0) +#define FUNC_AVB0_AVTP_CAPTURE IP0SR7(4, 0x0) +#define FUNC_AVB0_AVTP_MATCH IP0SR7(8, 0x0) +#define FUNC_AVB0_TD3 IP0SR7(12, 0x0) +#define FUNC_AVB0_LINK IP0SR7(16, 0x0) +#define FUNC_AVB0_PHY_INT IP0SR7(20, 0x0) +#define FUNC_AVB0_TD2 IP0SR7(24, 0x0) +#define FUNC_AVB0_TD1 IP0SR7(28, 0x0) +#define FUNC_AVB0_RD3 IP1SR7(0, 0x0) +#define FUNC_AVB0_TXCREFCLK IP1SR7(4, 0x0) +#define FUNC_AVB0_MAGIC IP1SR7(8, 0x0) +#define FUNC_AVB0_TD0 IP1SR7(12, 0x0) +#define FUNC_AVB0_RD2 IP1SR7(16, 0x0) +#define FUNC_AVB0_MDC IP1SR7(20, 0x0) +#define FUNC_AVB0_MDIO IP1SR7(24, 0x0) +#define FUNC_AVB0_TXC IP1SR7(28, 0x0) +#define FUNC_AVB0_TX_CTL IP2SR7(0, 0x0) +#define FUNC_AVB0_RD1 IP2SR7(4, 0x0) +#define FUNC_AVB0_RD0 IP2SR7(8, 0x0) +#define FUNC_AVB0_RXC IP2SR7(12, 0x0) +#define FUNC_AVB0_RX_CTL IP2SR7(16, 0x0) +#define FUNC_SCL0 IP0SR8(0, 0x0) +#define FUNC_SDA0 IP0SR8(4, 0x0) +#define FUNC_SCL1 IP0SR8(8, 0x0) +#define FUNC_SDA1 IP0SR8(12, 0x0) +#define FUNC_SCL2 IP0SR8(16, 0x0) +#define FUNC_SDA2 IP0SR8(20, 0x0) +#define FUNC_SCL3 IP0SR8(24, 0x0) +#define FUNC_SDA3 IP0SR8(28, 0x0) +#define FUNC_SCL4 IP1SR8(0, 0x0) +#define FUNC_SDA4 IP1SR8(4, 0x0) +#define FUNC_SCL5 IP1SR8(8, 0x0) +#define FUNC_SDA5 IP1SR8(12, 0x0) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779G0_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h index 44669cc4644ff..a005146def81f 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2021-2023 IoT.bzh + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -81,6 +82,10 @@ #define IP1SR7(shift, func) IPnSR(1, 7, shift, func) #define IP2SR7(shift, func) IPnSR(2, 7, shift, func) #define IP3SR7(shift, func) IPnSR(3, 7, shift, func) +#define IP0SR8(shift, func) IPnSR(0, 8, shift, func) +#define IP1SR8(shift, func) IPnSR(1, 8, shift, func) +#define IP2SR8(shift, func) IPnSR(2, 8, shift, func) +#define IP3SR8(shift, func) IPnSR(3, 8, shift, func) /** * @brief Macro to define a dummy IPSR flag for a pin diff --git a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt index 17936ad303bb8..39a1f19594382 100644 --- a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt +++ b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt @@ -1,4 +1,5 @@ # Copyright (c) 2023 IoT.bzh +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 if(CONFIG_SOC_R8A779F0_R52) @@ -8,4 +9,7 @@ elseif(CONFIG_SOC_R8A779F0_A55) zephyr_include_directories(a55) zephyr_library_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_R8A779G0_R52) + zephyr_include_directories(r52) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") endif() diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig b/soc/renesas/rcar/rcar_gen4/Kconfig index fb05e3c06c8d8..445abe35bb787 100644 --- a/soc/renesas/rcar/rcar_gen4/Kconfig +++ b/soc/renesas/rcar/rcar_gen4/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2023 IoT.bzh +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config SOC_R8A779F0_R52 @@ -13,3 +14,9 @@ config SOC_R8A779F0_A55 select CPU_CORTEX_A55 select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL select ARM_ARCH_TIMER + +config SOC_R8A779G0_R52 + select ARM + select CPU_CORTEX_R52 + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + select ARM_ARCH_TIMER diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 index 93cfd5c9839ff..1acc21afaa411 100644 --- a/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 @@ -1,9 +1,10 @@ # Copyright (c) 2023 IoT.bzh +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_RCAR_GEN4 +if SOC_R8A779F0_R52 || SOC_R8A779F0_A55 config NUM_IRQS default 1216 #960 SPI + 256 LPI -endif # SOC_SERIES_RCAR_GEN4 +endif # SOC_R8A779F0_R52 || SOC_R8A779F0_A55 diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779g0 b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779g0 new file mode 100644 index 0000000000000..8f32bb0b45bc6 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779g0 @@ -0,0 +1,18 @@ +# Copyright (c) 2023 IoT.bzh +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_R8A779G0_R52 + +config NUM_IRQS + default 991 + +# Arm Generic Timer frequency (Hz) +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/timer,clock-frequency) + +# Clock Pulse Generator +config CLOCK_CONTROL + default y + +endif # SOC_R8A779G0_R52 diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.soc b/soc/renesas/rcar/rcar_gen4/Kconfig.soc index fa99fed24824f..97a16597d2e57 100644 --- a/soc/renesas/rcar/rcar_gen4/Kconfig.soc +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.soc @@ -1,4 +1,5 @@ # Copyright (c) 2023 IoT.bzh +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config SOC_SERIES_RCAR_GEN4 @@ -17,8 +18,15 @@ config SOC_R8A779F0_A55 help r8a779f0 a55 +config SOC_R8A779G0_R52 + bool + select SOC_SERIES_RCAR_GEN4 + help + r8a779g0 r52 + config SOC_SERIES default "rcar_gen4" if SOC_SERIES_RCAR_GEN4 config SOC + default "r8a779g0" if SOC_R8A779G0_R52 default "r8a779f0" if SOC_R8A779F0_R52 || SOC_R8A779F0_A55 diff --git a/soc/renesas/rcar/soc.yml b/soc/renesas/rcar/soc.yml index 17d2f87092816..31e58f58ff660 100644 --- a/soc/renesas/rcar/soc.yml +++ b/soc/renesas/rcar/soc.yml @@ -14,3 +14,6 @@ family: cpuclusters: - name: r52 - name: a55 + - name: r8a779g0 + cpuclusters: + - name: r52