diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/Kconfig.pic32cz_ca80_cult b/boards/microchip/pic32c/pic32cz_ca80_cult/Kconfig.pic32cz_ca80_cult new file mode 100644 index 0000000000000..a8df482431f52 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/Kconfig.pic32cz_ca80_cult @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PIC32CZ_CA80_CULT + select SOC_PIC32CZ8110CA80208 diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/board.cmake b/boards/microchip/pic32c/pic32cz_ca80_cult/board.cmake new file mode 100644 index 0000000000000..d76c72d4806b5 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=PIC32CZ8110CA80" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/board.yml b/boards/microchip/pic32c/pic32cz_ca80_cult/board.yml new file mode 100644 index 0000000000000..d26381cc32115 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: pic32cz_ca80_cult + full_name: PIC32CZ CA80 Curiosity Ultra + vendor: microchip + socs: + - name: pic32cz8110ca80208 diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/doc/img/pic32cz_ca80_cult.webp b/boards/microchip/pic32c/pic32cz_ca80_cult/doc/img/pic32cz_ca80_cult.webp new file mode 100644 index 0000000000000..120e69cf3a0d6 Binary files /dev/null and b/boards/microchip/pic32c/pic32cz_ca80_cult/doc/img/pic32cz_ca80_cult.webp differ diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/doc/index.rst b/boards/microchip/pic32c/pic32cz_ca80_cult/doc/index.rst new file mode 100644 index 0000000000000..171bbe01ae347 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/doc/index.rst @@ -0,0 +1,97 @@ +.. zephyr:board:: pic32cz_ca80_cult + +Overview +******** + +The PIC32CZ CA80 Curiosity Ultra development board is a hardware platform +to evaluate the Microchip PIC32CZ CA80 microcontroller, and the +development board part number is EV51S73A. The development board offers a +set of features that enables the PIC32CZ CA80 users to get started with +the PIC32CZ CA80 peripherals, and to obtain an understanding of how to +integrate the device in their own design. + +Hardware +******** + +- 208-Pin TFBGA PIC32CZ8110 CA80 microcontroller +- 32.768 kHz crystal oscillator +- 8M flash memory and 1M of RAM +- Xplained pro extension compatible interface +- Two yellow user LEDs +- Two mechanical user push button +- One reset button +- Virtual COM port (VCOM) +- Programming and debugging of on-board PIC32CZ CA80 through Serial Wire Debug (SWD) +- Arduino uno R3 compatible interface +- MikroBus Socket +- On-board temperature sensor +- Graphics interface +- G-bit Ethernet +- 2 high-speed USB (Type-C and Micro A/B) + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `PIC32CZ CA80 Curiosity Ultra User Guide`_ has detailed information about board connections. + +Programming & Debugging +*********************** + +.. zephyr:board-supported-runners:: + +Flash Using J-Link +================== + +To flash the board using the J-Link debugger, follow the steps below: + +1. Install J-Link Software + + - Download and install the `J-Link software `_ tools from Segger. + - Make sure the installed J-Link executables (e.g., ``JLink``, ``JLinkGDBServer``) are available in your system's PATH. + +2. Connect the Board + + - Connect the `J32 Debug Probe `_ to the board's **CORTEX DEBUG** header. + - Connect the other end of the J32 Debug Probe to your **host machine (PC)** via USB. + - Connect the DEBUG USB port on the board to your host machine to **power up the board**. + +3. Build the Application + + You can build a sample Zephyr application, such as **Blinky**, using the ``west`` tool. Run the following commands from your Zephyr workspace: + + .. code-block:: console + + west build -b pic32cz_ca80_cult -p -s samples/basic/blinky + + This will build the Blinky application for the ``pic32cz_ca80_cult`` board. + +4. Flash the Device + + Once the build completes, flash the firmware using: + + .. code-block:: console + + west flash + + This uses the default ``jlink`` runner to flash the application to the board. + +5. Observe the Result + + After flashing, **LED0** on the board should start **blinking**, indicating that the application is running successfully. + +References +********** + +PIC32CZ CA80 Product Page: + https://www.microchip.com/en-us/product/PIC32CZ8110CA80208 + +PIC32CZ CA80 Curiosity Ultra Development Board Page: + https://www.microchip.com/en-us/development-tool/ev51s73a + +.. _PIC32CZ CA80 Curiosity Ultra User Guide: + https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/UserGuides/PIC32CZ-CA80-CA90-Curiosity-Ultra-User-Guide-DS70005522.pdf diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.dts b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.dts new file mode 100644 index 0000000000000..e9c286460625d --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "PIC32CZ CA80 Curiosity Ultra"; + compatible = "pic32cz_ca80,cult", "microchip,pic32cz8110ca80208", "microchip,pic32cz"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&portb 21 GPIO_ACTIVE_LOW>; + label = "User LED 0"; + }; + + led1: led_1 { + gpios = <&portb 22 GPIO_ACTIVE_LOW>; + label = "User LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&portb 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&portc 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1"; + zephyr,code = ; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@7fc000 { + label = "storage"; + reg = <0x0007fc000 0x4000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&portb { + status = "okay"; +}; + +&portc { + status = "okay"; +}; diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.yaml b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.yaml new file mode 100644 index 0000000000000..e1e62f62ee721 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: pic32cz_ca80_cult +name: PIC32CZ CA80 Curiosity Ultra +type: mcu +arch: arm +toolchain: + - zephyr +flash: 8192 +ram: 1024 +supported: + - gpio +vendor: microchip diff --git a/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult_defconfig b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult_defconfig new file mode 100644 index 0000000000000..912a8e1042370 --- /dev/null +++ b/boards/microchip/pic32c/pic32cz_ca80_cult/pic32cz_ca80_cult_defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_ARM_MPU=y diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_1051_ca.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_1051_ca.dtsi new file mode 100644 index 0000000000000..91334645d5464 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_1051_ca.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_M(1)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(512)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_2051_ca.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_2051_ca.dtsi new file mode 100644 index 0000000000000..01cad81f1a375 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_2051_ca.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_M(2)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(512)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_4010_ca.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_4010_ca.dtsi new file mode 100644 index 0000000000000..ef0c4115ee646 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_4010_ca.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_M(4)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_M(1)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_8110_ca.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_8110_ca.dtsi new file mode 100644 index 0000000000000..f592d9bcdbfcc --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_8110_ca.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_M(8)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_M(1)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi new file mode 100644 index 0000000000000..9fdaef3a8f95e --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m7"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + write-block-size = <8>; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + porta: gpio@44840000 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840000 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portb: gpio@44840080 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840080 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portc: gpio@44840100 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840100 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portd: gpio@44840180 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840180 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_100.dtsi new file mode 100644 index 0000000000000..ffc24df06c27f --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_100.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_144.dtsi new file mode 100644 index 0000000000000..ffc24df06c27f --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_144.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_176.dtsi new file mode 100644 index 0000000000000..d8d8e4f8c44c3 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_176.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + porte: gpio@44840200 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840200 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portf: gpio@44840280 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840280 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portg: gpio@44840300 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840300 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_208.dtsi new file mode 100644 index 0000000000000..d8d8e4f8c44c3 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_208.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + porte: gpio@44840200 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840200 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portf: gpio@44840280 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840280 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portg: gpio@44840300 { + status = "disabled"; + compatible = "microchip,port-g1-gpio"; + reg = <0x44840300 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80100.dtsi new file mode 100644 index 0000000000000..2f635a4b33689 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80144.dtsi new file mode 100644 index 0000000000000..29f60b2194bd9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80176.dtsi new file mode 100644 index 0000000000000..db11ef5defafe --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80208.dtsi new file mode 100644 index 0000000000000..fcde5e4923a91 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80100.dtsi new file mode 100644 index 0000000000000..1531dbb0beb63 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80144.dtsi new file mode 100644 index 0000000000000..8ca3da5228e35 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80176.dtsi new file mode 100644 index 0000000000000..8ebcc3dc3d1e4 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80208.dtsi new file mode 100644 index 0000000000000..7dd5bac8da05c --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz4010ca80208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80100.dtsi new file mode 100644 index 0000000000000..c20876e390487 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80144.dtsi new file mode 100644 index 0000000000000..55cb09f063df4 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80176.dtsi new file mode 100644 index 0000000000000..b75f0715ca1d5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80208.dtsi new file mode 100644 index 0000000000000..cac3e7ea75d63 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz8110ca80208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90100.dtsi new file mode 100644 index 0000000000000..2f635a4b33689 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90144.dtsi new file mode 100644 index 0000000000000..29f60b2194bd9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90176.dtsi new file mode 100644 index 0000000000000..db11ef5defafe --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90208.dtsi new file mode 100644 index 0000000000000..fcde5e4923a91 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz2051ca90208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90100.dtsi new file mode 100644 index 0000000000000..1531dbb0beb63 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90144.dtsi new file mode 100644 index 0000000000000..8ca3da5228e35 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90176.dtsi new file mode 100644 index 0000000000000..8ebcc3dc3d1e4 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90208.dtsi new file mode 100644 index 0000000000000..7dd5bac8da05c --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz4010ca90208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90100.dtsi new file mode 100644 index 0000000000000..c20876e390487 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90144.dtsi new file mode 100644 index 0000000000000..55cb09f063df4 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90176.dtsi new file mode 100644 index 0000000000000..b75f0715ca1d5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90208.dtsi new file mode 100644 index 0000000000000..cac3e7ea75d63 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca90/pic32cz8110ca90208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91100.dtsi new file mode 100644 index 0000000000000..2f635a4b33689 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91144.dtsi new file mode 100644 index 0000000000000..29f60b2194bd9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91176.dtsi new file mode 100644 index 0000000000000..db11ef5defafe --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz2051ca91176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91100.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91100.dtsi new file mode 100644 index 0000000000000..1531dbb0beb63 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91144.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91144.dtsi new file mode 100644 index 0000000000000..8ca3da5228e35 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91144.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91176.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91176.dtsi new file mode 100644 index 0000000000000..8ebcc3dc3d1e4 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91176.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91208.dtsi b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91208.dtsi new file mode 100644 index 0000000000000..7dd5bac8da05c --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca91/pic32cz4010ca91208.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/soc/microchip/pic32c/pic32cz_ca/CMakeLists.txt b/soc/microchip/pic32c/pic32cz_ca/CMakeLists.txt new file mode 100644 index 0000000000000..e01d600d17e54 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${SOC_SERIES}) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/pic32c/pic32cz_ca/Kconfig b/soc/microchip/pic32c/pic32cz_ca/Kconfig new file mode 100644 index 0000000000000..a295acedd0be2 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_PIC32CZ_CA + select ARM + select MICROCHIP_PIC32C + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ARCH_HW_AT_BOOT + select HAS_SWO + select XIP + select HAS_POWEROFF diff --git a/soc/microchip/pic32c/pic32cz_ca/Kconfig.defconfig b/soc/microchip/pic32c/pic32cz_ca/Kconfig.defconfig new file mode 100644 index 0000000000000..b2ba9a7d3e1ec --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_PIC32CZ_CA + +config NUM_IRQS + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_FAMILY_MICROCHIP_PIC32CZ_CA diff --git a/soc/microchip/pic32c/pic32cz_ca/Kconfig.soc b/soc/microchip/pic32c/pic32cz_ca/Kconfig.soc new file mode 100644 index 0000000000000..945639b777ec5 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_PIC32CZ_CA + bool + +config SOC_FAMILY + default "microchip_pic32cz_ca" if SOC_FAMILY_MICROCHIP_PIC32CZ_CA + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/Kconfig.soc b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/Kconfig.soc new file mode 100644 index 0000000000000..51de482bf882c --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/Kconfig.soc @@ -0,0 +1,73 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC32CZ_CA80 + bool + select SOC_FAMILY_MICROCHIP_PIC32CZ_CA + help + Enable support for Microchip PIC32CZ CA80 Cortex-M7 microcontrollers. + +config SOC_SERIES + default "pic32cz_ca80" if SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ2051CA80100 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ2051CA80144 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ2051CA80176 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ2051CA80208 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ4010CA80100 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ4010CA80144 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ4010CA80176 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ4010CA80208 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ8110CA80100 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ8110CA80144 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ8110CA80176 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC_PIC32CZ8110CA80208 + bool + select SOC_SERIES_PIC32CZ_CA80 + +config SOC + default "pic32cz2051ca80100" if SOC_PIC32CZ2051CA80100 + default "pic32cz2051ca80144" if SOC_PIC32CZ2051CA80144 + default "pic32cz2051ca80176" if SOC_PIC32CZ2051CA80176 + default "pic32cz2051ca80208" if SOC_PIC32CZ2051CA80208 + default "pic32cz4010ca80100" if SOC_PIC32CZ4010CA80100 + default "pic32cz4010ca80144" if SOC_PIC32CZ4010CA80144 + default "pic32cz4010ca80176" if SOC_PIC32CZ4010CA80176 + default "pic32cz4010ca80208" if SOC_PIC32CZ4010CA80208 + default "pic32cz8110ca80100" if SOC_PIC32CZ8110CA80100 + default "pic32cz8110ca80144" if SOC_PIC32CZ8110CA80144 + default "pic32cz8110ca80176" if SOC_PIC32CZ8110CA80176 + default "pic32cz8110ca80208" if SOC_PIC32CZ8110CA80208 diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/soc.h b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/soc.h new file mode 100644 index 0000000000000..6b35483c83037 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca80/soc.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_MICROCHIP_PIC32CZ_CA80_SOC_H_ +#define SOC_MICROCHIP_PIC32CZ_CA80_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#if defined(CONFIG_SOC_PIC32CZ2051CA80100) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA80144) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA80176) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA80208) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA80100) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA80144) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA80176) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA80208) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA80100) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA80144) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA80176) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA80208) +#include +#else +#error "Library does not support the specified device." +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* SOC_MICROCHIP_PIC32CZ_CA80_SOC_H_ */ diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/Kconfig.soc b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/Kconfig.soc new file mode 100644 index 0000000000000..13caeaf7f75a4 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/Kconfig.soc @@ -0,0 +1,73 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC32CZ_CA90 + bool + select SOC_FAMILY_MICROCHIP_PIC32CZ_CA + help + Enable support for Microchip PIC32CZ CA90 Cortex-M7 microcontrollers. + +config SOC_SERIES + default "pic32cz_ca90" if SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ2051CA90100 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ2051CA90144 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ2051CA90176 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ2051CA90208 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ4010CA90100 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ4010CA90144 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ4010CA90176 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ4010CA90208 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ8110CA90100 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ8110CA90144 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ8110CA90176 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC_PIC32CZ8110CA90208 + bool + select SOC_SERIES_PIC32CZ_CA90 + +config SOC + default "pic32cz2051ca90100" if SOC_PIC32CZ2051CA90100 + default "pic32cz2051ca90144" if SOC_PIC32CZ2051CA90144 + default "pic32cz2051ca90176" if SOC_PIC32CZ2051CA90176 + default "pic32cz2051ca90208" if SOC_PIC32CZ2051CA90208 + default "pic32cz4010ca90100" if SOC_PIC32CZ4010CA90100 + default "pic32cz4010ca90144" if SOC_PIC32CZ4010CA90144 + default "pic32cz4010ca90176" if SOC_PIC32CZ4010CA90176 + default "pic32cz4010ca90208" if SOC_PIC32CZ4010CA90208 + default "pic32cz8110ca90100" if SOC_PIC32CZ8110CA90100 + default "pic32cz8110ca90144" if SOC_PIC32CZ8110CA90144 + default "pic32cz8110ca90176" if SOC_PIC32CZ8110CA90176 + default "pic32cz8110ca90208" if SOC_PIC32CZ8110CA90208 diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/soc.h b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/soc.h new file mode 100644 index 0000000000000..1db0748b46794 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca90/soc.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_MICROCHIP_PIC32CZ_CA90_SOC_H_ +#define SOC_MICROCHIP_PIC32CZ_CA90_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#if defined(CONFIG_SOC_PIC32CZ2051CA90100) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA90144) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA90176) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA90208) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA90100) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA90144) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA90176) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA90208) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA90100) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA90144) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA90176) +#include +#elif defined(CONFIG_SOC_PIC32CZ8110CA90208) +#include +#else +#error "Library does not support the specified device." +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* SOC_MICROCHIP_PIC32CZ_CA90_SOC_H_ */ diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/Kconfig.soc b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/Kconfig.soc new file mode 100644 index 0000000000000..d6a59d595e372 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/Kconfig.soc @@ -0,0 +1,48 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC32CZ_CA91 + bool + select SOC_FAMILY_MICROCHIP_PIC32CZ_CA + help + Enable support for Microchip PIC32CZ CA91 Cortex-M7 microcontrollers. + +config SOC_SERIES + default "pic32cz_ca91" if SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ2051CA91100 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ2051CA91144 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ2051CA91176 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ4010CA91100 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ4010CA91144 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ4010CA91176 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC_PIC32CZ4010CA91208 + bool + select SOC_SERIES_PIC32CZ_CA91 + +config SOC + default "pic32cz2051ca91100" if SOC_PIC32CZ2051CA91100 + default "pic32cz2051ca91144" if SOC_PIC32CZ2051CA91144 + default "pic32cz2051ca91176" if SOC_PIC32CZ2051CA91176 + default "pic32cz4010ca91100" if SOC_PIC32CZ4010CA91100 + default "pic32cz4010ca91144" if SOC_PIC32CZ4010CA91144 + default "pic32cz4010ca91176" if SOC_PIC32CZ4010CA91176 + default "pic32cz4010ca91208" if SOC_PIC32CZ4010CA91208 diff --git a/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/soc.h b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/soc.h new file mode 100644 index 0000000000000..f5e9829da6d1d --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/pic32cz_ca91/soc.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_MICROCHIP_PIC32CZ_CA91_SOC_H_ +#define SOC_MICROCHIP_PIC32CZ_CA91_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#if defined(CONFIG_SOC_PIC32CZ2051CA91100) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA91144) +#include +#elif defined(CONFIG_SOC_PIC32CZ2051CA91176) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA91100) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA91144) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA91176) +#include +#elif defined(CONFIG_SOC_PIC32CZ4010CA91208) +#include +#else +#error "Library does not support the specified device." +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* SOC_MICROCHIP_PIC32CZ_CA91_SOC_H_ */ diff --git a/soc/microchip/pic32c/pic32cz_ca/soc.yml b/soc/microchip/pic32c/pic32cz_ca/soc.yml new file mode 100644 index 0000000000000..f3b620c660b54 --- /dev/null +++ b/soc/microchip/pic32c/pic32cz_ca/soc.yml @@ -0,0 +1,43 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +family: +- name: microchip_pic32cz_ca + series: + - name: pic32cz_ca80 + socs: + - name: pic32cz2051ca80100 + - name: pic32cz2051ca80144 + - name: pic32cz2051ca80176 + - name: pic32cz2051ca80208 + - name: pic32cz4010ca80100 + - name: pic32cz4010ca80144 + - name: pic32cz4010ca80176 + - name: pic32cz4010ca80208 + - name: pic32cz8110ca80100 + - name: pic32cz8110ca80144 + - name: pic32cz8110ca80176 + - name: pic32cz8110ca80208 + - name: pic32cz_ca90 + socs: + - name: pic32cz2051ca90100 + - name: pic32cz2051ca90144 + - name: pic32cz2051ca90176 + - name: pic32cz2051ca90208 + - name: pic32cz4010ca90100 + - name: pic32cz4010ca90144 + - name: pic32cz4010ca90176 + - name: pic32cz4010ca90208 + - name: pic32cz8110ca90100 + - name: pic32cz8110ca90144 + - name: pic32cz8110ca90176 + - name: pic32cz8110ca90208 + - name: pic32cz_ca91 + socs: + - name: pic32cz2051ca91100 + - name: pic32cz2051ca91144 + - name: pic32cz2051ca91176 + - name: pic32cz4010ca91100 + - name: pic32cz4010ca91144 + - name: pic32cz4010ca91176 + - name: pic32cz4010ca91208