From 45fd8f0611ef625168af23bef097780d4fd8cfed Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 5 Mar 2025 12:35:06 +0700 Subject: [PATCH 01/25] manifest: update rev of hal_renesas to latest Update rev of hal_renesas to latest Signed-off-by: Khoa Tran --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 744a097602ba8..e29994ac314e8 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 8c5505d957db35816f3f2ddc93f6805fd648a90c + revision: f6950ff142a5a28950c97d818d5b8ec1d3c85ba5 groups: - hal - name: hal_rpi_pico From c346c5fcfaec5d56a96f914e461b75f2dc1be579 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Thu, 28 Aug 2025 13:09:27 +0700 Subject: [PATCH 02/25] soc: renesas: ra: Add support Renesas RA8D2 SoC Add support Renesas RA8D2 SoC Signed-off-by: Khoa Tran Signed-off-by: Khoa Nguyen --- soc/renesas/ra/ra8d2/CMakeLists.txt | 17 ++++ soc/renesas/ra/ra8d2/Kconfig | 25 ++++++ soc/renesas/ra/ra8d2/Kconfig.defconfig | 42 ++++++++++ soc/renesas/ra/ra8d2/Kconfig.soc | 28 +++++++ soc/renesas/ra/ra8d2/power.c | 96 ++++++++++++++++++++++ soc/renesas/ra/ra8d2/ram_sections.ld | 16 ++++ soc/renesas/ra/ra8d2/sections.ld | 70 ++++++++++++++++ soc/renesas/ra/ra8d2/soc.c | 106 +++++++++++++++++++++++++ soc/renesas/ra/ra8d2/soc.h | 16 ++++ 9 files changed, 416 insertions(+) create mode 100644 soc/renesas/ra/ra8d2/CMakeLists.txt create mode 100644 soc/renesas/ra/ra8d2/Kconfig create mode 100644 soc/renesas/ra/ra8d2/Kconfig.defconfig create mode 100644 soc/renesas/ra/ra8d2/Kconfig.soc create mode 100644 soc/renesas/ra/ra8d2/power.c create mode 100644 soc/renesas/ra/ra8d2/ram_sections.ld create mode 100644 soc/renesas/ra/ra8d2/sections.ld create mode 100644 soc/renesas/ra/ra8d2/soc.c create mode 100644 soc/renesas/ra/ra8d2/soc.h diff --git a/soc/renesas/ra/ra8d2/CMakeLists.txt b/soc/renesas/ra/ra8d2/CMakeLists.txt new file mode 100644 index 0000000000000..7f3c66c46e472 --- /dev/null +++ b/soc/renesas/ra/ra8d2/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_sources_ifdef(CONFIG_PM + power.c +) + +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8d2/Kconfig b/soc/renesas/ra/ra8d2/Kconfig new file mode 100644 index 0000000000000..9591ad7e5e945 --- /dev/null +++ b/soc/renesas/ra/ra8d2/Kconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA8D2 + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select FPU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select HAS_SWO + select XIP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select HAS_RENESAS_RA_FSP + select SOC_EARLY_INIT_HOOK + select HAS_PM + +config SOC_R7KA8D2KFLCAC_CM85 + select CPU_CORTEX_M85 + select GPIO_RA_HAS_VBTICTLR + +config SOC_R7KA8D2KFLCAC_CM33 + select CPU_CORTEX_M33 + select SOC_RA_SECOND_CORE_BUILD diff --git a/soc/renesas/ra/ra8d2/Kconfig.defconfig b/soc/renesas/ra/ra8d2/Kconfig.defconfig new file mode 100644 index 0000000000000..1102d1df01d1a --- /dev/null +++ b/soc/renesas/ra/ra8d2/Kconfig.defconfig @@ -0,0 +1,42 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA8D2 + +config NUM_IRQS + default 96 + +DT_CPUCLK0_PATH := $(dt_nodelabel_path,cpuclk0) +DT_CPUCLK1_PATH := $(dt_nodelabel_path,cpuclk1) +DT_LOCO_PATH := $(dt_nodelabel_path,loco) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_CPUCLK0_PATH),clock-frequency) if SOC_R7KA8D2KFLCAC_CM85 && CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,$(DT_CPUCLK1_PATH),clock-frequency) if SOC_R7KA8D2KFLCAC_CM33 && CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER + +config CORTEX_M_SYSTICK + default n if RENESAS_RA_ULPT_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if RENESAS_RA_ULPT_TIMER + +config PM_DEVICE + default y if PM + +config PM_STATS + default n if PM + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + +config DCACHE + default n + +config CACHE_MANAGEMENT + default n + +endif # SOC_SERIES_RA8D2 diff --git a/soc/renesas/ra/ra8d2/Kconfig.soc b/soc/renesas/ra/ra8d2/Kconfig.soc new file mode 100644 index 0000000000000..4d2c5c3a91520 --- /dev/null +++ b/soc/renesas/ra/ra8d2/Kconfig.soc @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA8D2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA8D2 series + +config SOC_R7KA8D2KFLCAC + bool + select SOC_SERIES_RA8D2 + help + R7KA8D2KFLCAC + +config SOC_R7KA8D2KFLCAC_CM85 + bool + select SOC_R7KA8D2KFLCAC + +config SOC_R7KA8D2KFLCAC_CM33 + bool + select SOC_R7KA8D2KFLCAC + +config SOC_SERIES + default "ra8d2" if SOC_SERIES_RA8D2 + +config SOC + default "r7ka8d2kflcac" if SOC_R7KA8D2KFLCAC diff --git a/soc/renesas/ra/ra8d2/power.c b/soc/renesas/ra/ra8d2/power.c new file mode 100644 index 0000000000000..bc20edd7a814d --- /dev/null +++ b/soc/renesas/ra/ra8d2/power.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +/* Low Power Mode instance control structure */ +static lpm_instance_ctrl_t pm_state_ctrl; + +/* Configuration for Runtime Idle Power State */ +const lpm_cfg_t pm_state_runtime_idle_cfg = { + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U, + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + .ram_retention_cfg.ram_retention = (uint16_t)(0x7F), + .ram_retention_cfg.tcm_retention = true, + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, + .p_extend = NULL, +}; + +/* Configuration for Standby Power State */ +const lpm_cfg_t pm_state_standby_cfg = { + .low_power_mode = LPM_MODE_STANDBY, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U, + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + .ram_retention_cfg.ram_retention = (uint16_t)(0x7F), + .ram_retention_cfg.tcm_retention = true, + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, + .p_extend = NULL, +}; + +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + R_LPM_Open(&pm_state_ctrl, &pm_state_runtime_idle_cfg); + __disable_irq(); + __set_BASEPRI(0); + __ISB(); + + R_LPM_LowPowerModeEnter(&pm_state_ctrl); + __enable_irq(); + __ISB(); + break; + + case PM_STATE_STANDBY: + R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg); + __disable_irq(); + __set_BASEPRI(0); + __ISB(); + + R_LPM_LowPowerModeEnter(&pm_state_ctrl); + __enable_irq(); + __ISB(); + break; + + default: + break; + } +} + +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + __fallthrough; + case PM_STATE_STANDBY: + R_LPM_Close(&pm_state_ctrl); + break; + + default: + break; + } + irq_unlock(0); +} diff --git a/soc/renesas/ra/ra8d2/ram_sections.ld b/soc/renesas/ra/ra8d2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8d2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8d2/sections.ld b/soc/renesas/ra/ra8d2/sections.ld new file mode 100644 index 0000000000000..a83eaad884aab --- /dev/null +++ b/soc/renesas/ra/ra8d2/sections.ld @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)),) +{ + KEEP(*(.option_setting_ofs0)) +} GROUP_LINK_IN(OFS_OFS0_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs2)),) +{ + KEEP(*(.option_setting_ofs2)) +} GROUP_LINK_IN(OFS_OFS2_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +SECTION_DATA_PROLOGUE(.option_setting_sas, DT_REG_ADDR(DT_NODELABEL(option_setting_sas)),) +{ + KEEP(*(.option_setting_sas)) +} GROUP_LINK_IN(OFS_SAS_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sec)),) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_OFS1_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sec)),) +{ + KEEP(*(.option_setting_ofs3_sec)) +} GROUP_LINK_IN(OFS_OFS3_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sel)),) +{ + KEEP(*(.option_setting_ofs1_sel)) +} GROUP_LINK_IN(OFS_OFS1_SEL_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sel)),) +{ + KEEP(*(.option_setting_ofs3_sel)) +} GROUP_LINK_IN(OFS_OFS3_SEL_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_bps_sec)),) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_BPS_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_otp_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_otp_pbps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_otp_pbps_sec)),) +{ + KEEP(*(.option_setting_otp_pbps_sec)) +} GROUP_LINK_IN(OFS_OTP_PBPS_SEC_MEMORY) +#endif diff --git a/soc/renesas/ra/ra8d2/soc.c b/soc/renesas/ra/ra8d2/soc.c new file mode 100644 index 0000000000000..497d94f0150b1 --- /dev/null +++ b/soc/renesas/ra/ra8d2/soc.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA8P1 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "soc.h" + +#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk) + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +#ifdef CONFIG_RUNTIME_NMI +extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[]; +extern void NMI_Handler(void); +#endif /* CONFIG_RUNTIME_NMI */ + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 5; i++) { + g_protect_counters[i] = 0; + } + + SystemCoreClock = BSP_MOCO_HZ; + +#ifdef CONFIG_RUNTIME_NMI + for (uint32_t i = 0; i < 16; i++) { + g_bsp_group_irq_sources[i] = 0; + } + + z_arm_nmi_set_handler(NMI_Handler); +#endif /* CONFIG_RUNTIME_NMI */ + +#ifdef CONFIG_CPU_CORTEX_M85 +#ifdef CONFIG_ICACHE + SCB->CCR = (uint32_t)CCR_CACHE_ENABLE; + barrier_dsync_fence_full(); + barrier_isync_fence_full(); +#endif +#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT) + /* Apply Arm Cortex-M85 errata workarounds for D-Cache + * Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register. + * Set bit 16 in ACTLR to 1. + * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 + * Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0, + * Document ID: SDEN-2236668). + */ + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + ICB->ACTLR |= (1U << 16U); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + + sys_cache_data_enable(); +#endif +#endif /*CONFIG_CPU_CORTEX_M85*/ + +#ifdef CONFIG_CPU_CORTEX_M33 +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif +#endif /*CONFIG_CPU_CORTEX_M33*/ +} diff --git a/soc/renesas/ra/ra8d2/soc.h b/soc/renesas/ra/ra8d2/soc.h new file mode 100644 index 0000000000000..dd9259e4e7d9f --- /dev/null +++ b/soc/renesas/ra/ra8d2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA8D2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA8D2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA8D2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA8D2_SOC_H_ */ From c09d91b7144ffb4f033b5619398ed129d428d4cb Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 22 Oct 2025 14:15:58 +0700 Subject: [PATCH 03/25] dts: arm: renesas: ra: Correct number of port pins for RA8x2 series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the GPIO port "ngpios" for RA8x2 series SoCs to match the values specified in the Hardware User’s Manual (HUM). Signed-off-by: Khoa Tran --- dts/arm/renesas/ra/ra8/ra8x2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/arm/renesas/ra/ra8/ra8x2.dtsi b/dts/arm/renesas/ra/ra8/ra8x2.dtsi index abf35b944cafb..39f873da7349a 100644 --- a/dts/arm/renesas/ra/ra8/ra8x2.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x2.dtsi @@ -220,7 +220,7 @@ port = <11>; gpio-controller; #gpio-cells = <2>; - ngpios = <16>; + ngpios = <8>; status = "disabled"; }; @@ -240,7 +240,7 @@ port = <13>; gpio-controller; #gpio-cells = <2>; - ngpios = <16>; + ngpios = <8>; status = "disabled"; }; From 78db76a5bddc834a50b2b150eb604803ed1f1129 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Thu, 28 Aug 2025 13:11:09 +0700 Subject: [PATCH 04/25] dts: arm: renesas: ra: Add support Renesas r7ka8d2kflcac SoC - Add support Renesas r7ka8d2kflcac SoC. - Move sdram-controller node from r7ka8p1kflcac.dtsi to ra8x2.dtsi since this device node is available for all RA8x2 SoCs Signed-off-by: Khoa Tran --- dts/arm/renesas/ra/ra8/r7ka8d2kflcac.dtsi | 39 + .../renesas/ra/ra8/r7ka8d2kflcac_cm85.dtsi | 10 + dts/arm/renesas/ra/ra8/r7ka8d2xf.dtsi | 815 ++++++++++++++++++ dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi | 8 - dts/arm/renesas/ra/ra8/ra8x2.dtsi | 57 +- soc/renesas/ra/soc.yml | 6 + 6 files changed, 926 insertions(+), 9 deletions(-) create mode 100644 dts/arm/renesas/ra/ra8/r7ka8d2kflcac.dtsi create mode 100644 dts/arm/renesas/ra/ra8/r7ka8d2kflcac_cm85.dtsi create mode 100644 dts/arm/renesas/ra/ra8/r7ka8d2xf.dtsi diff --git a/dts/arm/renesas/ra/ra8/r7ka8d2kflcac.dtsi b/dts/arm/renesas/ra/ra8/r7ka8d2kflcac.dtsi new file mode 100644 index 0000000000000..51a3f2408e4e1 --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8d2kflcac.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + mram-controller@4013c000 { + code_mram_cm85: mram@2000000 { + compatible = "renesas,ra-nv-mram"; + reg = <0x2000000 DT_SIZE_M(1)>; + write-block-size = <1>; + erase-block-size = <32>; + }; + }; + + sram0: memory@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(1664)>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&ioport2 { + gpio-reserved-ranges = <2 4>; +}; + +&ioport3 { + gpio-reserved-ranges = <12 4>; +}; + +&ioport9 { + gpio-reserved-ranges = <0 2>; +}; diff --git a/dts/arm/renesas/ra/ra8/r7ka8d2kflcac_cm85.dtsi b/dts/arm/renesas/ra/ra8/r7ka8d2kflcac_cm85.dtsi new file mode 100644 index 0000000000000..ee99685594981 --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8d2kflcac_cm85.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/delete-node/ &cpu1; diff --git a/dts/arm/renesas/ra/ra8/r7ka8d2xf.dtsi b/dts/arm/renesas/ra/ra8/r7ka8d2xf.dtsi new file mode 100644 index 0000000000000..44f65b81fdd73 --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8d2xf.dtsi @@ -0,0 +1,815 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + lcdif: display-controller@40342000 { + compatible = "renesas,ra-glcdc"; + reg = <0x40342000 0x1454>; + clocks = <&lcdclk MSTPC 4>; + status = "disabled"; + }; + }; + + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + clocks = <&xtal>; + div = <3>; + mul = <250 0>; + status = "disabled"; + + pllp: pllp { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllq: pllq { + compatible = "renesas,ra-cgc-pll-out"; + div = <6>; + freq = <333333333>; + status = "disabled"; + #clock-cells = <0>; + }; + + pllr: pllr { + compatible = "renesas,ra-cgc-pll-out"; + div = <5>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL2 */ + clocks = <&xtal>; + div = <3>; + mul = <300 0>; + status = "disabled"; + + pll2p: pll2p { + compatible = "renesas,ra-cgc-pll-out"; + div = <4>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2q: pll2q { + compatible = "renesas,ra-cgc-pll-out"; + div = <3>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2r: pll2r { + compatible = "renesas,ra-cgc-pll-out"; + div = <5>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + }; + + pclkblock: pclkblock@40203000 { + compatible = "renesas,ra-cgc-pclk-block"; + reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, + <0x4020300c 4>, <0x40203010 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", + "MSTPD", "MSTPE"; + #clock-cells = <0>; + clocks = <&pllp>; + status = "okay"; + + cpuclk0: cpuclk0 { + compatible = "renesas,ra-cgc-pclk"; + clock-frequency = ; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + cpuclk1: cpuclk1 { + compatible = "renesas,ra-cgc-pclk"; + clock-frequency = ; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + mriclk: mriclk { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + mrpclk: mrpclk { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclke: pclke { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk-out-div = <2>; + sdclk = <1>; + #clock-cells = <0>; + status = "okay"; + }; + }; + + bclka: bclka { + compatible = "renesas,ra-cgc-pclk"; + div = <6>; + clocks = <&pll2q>; + #clock-cells = <2>; + status = "disabled"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + div = <1>; + clocks = <&hoco>; + #clock-cells = <2>; + status = "disabled"; + }; + + sciclk: sciclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + spiclk: spiclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllq>; + div = <1>; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <6>; + #clock-cells = <2>; + status = "disabled"; + }; + + gptclk: gptclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2p>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + lcdclk: lcdclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + i3cclk: i3cclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2q>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + clocks = <&pll2r>; + div = <10>; + status = "disabled"; + }; + + usb60clk: u60clk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <8>; + #clock-cells = <2>; + status = "disabled"; + }; + + octaspiclk: octaspiclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllq>; + div = <1>; + #clock-cells = <2>; + status = "disabled"; + }; + + adcclk: adcclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + eswclk: eswclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllp>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + eswphyclk: eswphyclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllp>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + ethphyclk: ethphyclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2q>; + div = <32>; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; + +&ioport0 { + port-irqs = <&port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14 + &port_irq15 &port_irq16 &port_irq27 + &port_irq28 &port_irq29>; + port-irq-names = "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq15", + "port-irq16", + "port-irq27", + "port-irq28", + "port-irq29"; + port-irq6-pins = <0>; + port-irq7-pins = <1>; + port-irq8-pins = <2>; + port-irq9-pins = <4>; + port-irq10-pins = <5>; + port-irq11-pins = <6>; + port-irq12-pins = <8>; + port-irq13-pins = <9 15>; + port-irq14-pins = <10 13>; + port-irq15-pins = <12>; + port-irq16-pins = <11>; + port-irq27-pins = <14>; + port-irq28-pins = <7>; + port-irq29-pins = <3>; +}; + +&ioport1 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq16 &port_irq17 &port_irq19 + &port_irq20 &port_irq23 &port_irq24 + &port_irq27 &port_irq28 &port_irq30 + &port_irq31>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq16", + "port-irq17", + "port-irq19", + "port-irq20", + "port-irq23", + "port-irq24", + "port-irq27", + "port-irq28", + "port-irq30", + "port-irq31"; + port-irq0-pins = <5>; + port-irq1-pins = <1 4>; + port-irq2-pins = <0>; + port-irq16-pins = <3 6>; + port-irq17-pins = <2>; + port-irq19-pins = <11>; + port-irq20-pins = <10>; + port-irq23-pins = <9>; + port-irq24-pins = <8>; + port-irq27-pins = <12>; + port-irq28-pins = <13>; + port-irq30-pins = <14>; + port-irq31-pins = <7 15>; +}; + +&ioport2 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq4 &port_irq20 + &port_irq21 &port_irq23 &port_irq24 + &port_irq25 &port_irq26>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq4", + "port-irq20", + "port-irq21", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26"; + port-irq0-pins = <6>; + port-irq1-pins = <5>; + port-irq2-pins = <3 13>; + port-irq3-pins = <2 8 12>; + port-irq4-pins = <1>; + port-irq20-pins = <15>; + port-irq21-pins = <14>; + port-irq23-pins = <11>; + port-irq24-pins = <10>; + port-irq25-pins = <7 9>; + port-irq26-pins = <4>; +}; + +&ioport3 { + port-irqs = <&port_irq4 &port_irq5 &port_irq6 + &port_irq8 &port_irq9 &port_irq22 + &port_irq23 &port_irq24 &port_irq25 + &port_irq26 &port_irq27 &port_irq28 + &port_irq29>; + port-irq-names = "port-irq4", + "port-irq5", + "port-irq6", + "port-irq8", + "port-irq9", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29"; + port-irq4-pins = <0>; + port-irq5-pins = <2>; + port-irq6-pins = <1>; + port-irq8-pins = <5>; + port-irq9-pins = <4>; + port-irq22-pins = <12>; + port-irq23-pins = <11>; + port-irq24-pins = <10>; + port-irq25-pins = <9>; + port-irq26-pins = <8>; + port-irq27-pins = <7 13>; + port-irq28-pins = <6 14>; + port-irq29-pins = <3 15>; +}; + +&ioport4 { + port-irqs = <&port_irq0 &port_irq4 &port_irq5 + &port_irq6 &port_irq7 &port_irq8 &port_irq9 + &port_irq14 &port_irq15 &port_irq18 &port_irq20 + &port_irq22 &port_irq30 &port_irq31>; + port-irq-names = "port-irq0", + "port-irq4", + "port-irq5", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq14", + "port-irq15", + "port-irq18", + "port-irq20", + "port-irq22", + "port-irq30", + "port-irq31"; + port-irq0-pins = <0>; + port-irq4-pins = <2 11>; + port-irq5-pins = <1 10>; + port-irq6-pins = <9>; + port-irq7-pins = <8>; + port-irq8-pins = <15>; + port-irq9-pins = <14>; + port-irq14-pins = <3>; + port-irq15-pins = <4>; + port-irq18-pins = <13>; + port-irq20-pins = <12>; + port-irq22-pins = <7>; + port-irq30-pins = <5>; + port-irq31-pins = <6>; +}; + +&ioport5 { + port-irqs = <&port_irq1 &port_irq2 &port_irq3 + &port_irq6 &port_irq7 &port_irq8 &port_irq9 + &port_irq10 &port_irq12 &port_irq13 &port_irq14 + &port_irq15 &port_irq24 &port_irq25 &port_irq26 + &port_irq31>; + port-irq-names = "port-irq1", + "port-irq2", + "port-irq3", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq15", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq31"; + port-irq1-pins = <8>; + port-irq2-pins = <9>; + port-irq3-pins = <10>; + port-irq6-pins = <3>; + port-irq7-pins = <4>; + port-irq8-pins = <5>; + port-irq9-pins = <6>; + port-irq10-pins = <7>; + port-irq12-pins = <15>; + port-irq13-pins = <14>; + port-irq14-pins = <12>; + port-irq15-pins = <11>; + port-irq24-pins = <0>; + port-irq25-pins = <1>; + port-irq26-pins = <2>; + port-irq31-pins = <13>; +}; + +&ioport6 { + port-irqs = <&port_irq7 &port_irq16 &port_irq17 + &port_irq18 &port_irq19 &port_irq20 &port_irq22 + &port_irq23 &port_irq24 &port_irq25 &port_irq26 + &port_irq27 &port_irq28 &port_irq29 &port_irq30>; + port-irq-names = "port-irq7", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29", + "port-irq30"; + port-irq7-pins = <15>; + port-irq16-pins = <10>; + port-irq17-pins = <11>; + port-irq18-pins = <12>; + port-irq19-pins = <13>; + port-irq20-pins = <14>; + port-irq22-pins = <8>; + port-irq23-pins = <7>; + port-irq24-pins = <6>; + port-irq25-pins = <5>; + port-irq26-pins = <4>; + port-irq27-pins = <3>; + port-irq28-pins = <2>; + port-irq29-pins = <1 9>; + port-irq30-pins = <0>; +}; + +&ioport7 { + port-irqs = <&port_irq2 &port_irq3 &port_irq7 + &port_irq8 &port_irq10 &port_irq11 &port_irq12 + &port_irq13 &port_irq14 &port_irq16 &port_irq17 + &port_irq18 &port_irq19 &port_irq26>; + port-irq-names = "port-irq2", + "port-irq3", + "port-irq7", + "port-irq8", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq26"; + port-irq2-pins = <12>; + port-irq3-pins = <11>; + port-irq7-pins = <6>; + port-irq8-pins = <7>; + port-irq10-pins = <9>; + port-irq11-pins = <8>; + port-irq12-pins = <15>; + port-irq13-pins = <14>; + port-irq14-pins = <13>; + port-irq16-pins = <0>; + port-irq17-pins = <1 10>; + port-irq18-pins = <2>; + port-irq19-pins = <3 5>; + port-irq26-pins = <4>; +}; + +&ioport8 { + port-irqs = <&port_irq0 &port_irq11 &port_irq12 + &port_irq14 &port_irq15 &port_irq16 + &port_irq18 &port_irq19 &port_irq20 + &port_irq21 &port_irq22 &port_irq23 + &port_irq30>; + port-irq-names = "port-irq0", + "port-irq11", + "port-irq12", + "port-irq14", + "port-irq15", + "port-irq16", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq23", + "port-irq30"; + port-irq0-pins = <6>; + port-irq11-pins = <0 7>; + port-irq12-pins = <1>; + port-irq14-pins = <4>; + port-irq15-pins = <8 13 15>; + port-irq16-pins = <14>; + port-irq18-pins = <2>; + port-irq19-pins = <3>; + port-irq20-pins = <9>; + port-irq21-pins = <10>; + port-irq22-pins = <11>; + port-irq23-pins = <12>; + port-irq30-pins = <5>; +}; + +&ioport9 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq5 &port_irq6 + &port_irq7 &port_irq8 &port_irq9 + &port_irq10 &port_irq11 &port_irq21 + &port_irq30 &port_irq31>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq5", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq21", + "port-irq30", + "port-irq31"; + port-irq0-pins = <2>; + port-irq1-pins = <3>; + port-irq2-pins = <4>; + port-irq3-pins = <13>; + port-irq5-pins = <12>; + port-irq6-pins = <11>; + port-irq7-pins = <10>; + port-irq8-pins = <5 15>; + port-irq9-pins = <6 14>; + port-irq10-pins = <7>; + port-irq11-pins = <8>; + port-irq21-pins = <9>; + port-irq30-pins = <0>; + port-irq31-pins = <1>; +}; + +&ioporta { + port-irqs = <&port_irq4 &port_irq5 &port_irq6 + &port_irq10 &port_irq11 &port_irq12 &port_irq13 + &port_irq14 &port_irq16 &port_irq17 &port_irq18 + &port_irq19 &port_irq20 &port_irq21 &port_irq22 + &port_irq31>; + port-irq-names = "port-irq4", + "port-irq5", + "port-irq6", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq31"; + port-irq4-pins = <10>; + port-irq5-pins = <9>; + port-irq6-pins = <8>; + port-irq10-pins = <11>; + port-irq11-pins = <12>; + port-irq12-pins = <13>; + port-irq13-pins = <14>; + port-irq14-pins = <15>; + port-irq16-pins = <7>; + port-irq17-pins = <6>; + port-irq18-pins = <5>; + port-irq19-pins = <4>; + port-irq20-pins = <3>; + port-irq21-pins = <1>; + port-irq22-pins = <0>; + port-irq31-pins = <2>; +}; + +&ioportb { + port-irqs = <&port_irq0 &port_irq1 &port_irq9 + &port_irq10 &port_irq11 &port_irq12 &port_irq13 + &port_irq15>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq15"; + port-irq0-pins = <6>; + port-irq1-pins = <7>; + port-irq9-pins = <4>; + port-irq10-pins = <0>; + port-irq11-pins = <2>; + port-irq12-pins = <1>; + port-irq13-pins = <3>; + port-irq15-pins = <5>; +}; + +&ioportc { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq4 &port_irq5 &port_irq21 + &port_irq22 &port_irq23 &port_irq24 &port_irq25 + &port_irq26 &port_irq27 &port_irq28 &port_irq29 + &port_irq30>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq4", + "port-irq5", + "port-irq21", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29", + "port-irq30"; + port-irq0-pins = <14>; + port-irq1-pins = <13>; + port-irq2-pins = <12>; + port-irq3-pins = <11>; + port-irq4-pins = <10>; + port-irq5-pins = <9>; + port-irq21-pins = <7>; + port-irq22-pins = <6>; + port-irq23-pins = <5>; + port-irq24-pins = <4>; + port-irq25-pins = <3>; + port-irq26-pins = <2>; + port-irq27-pins = <1>; + port-irq28-pins = <0>; + port-irq29-pins = <8>; + port-irq30-pins = <15>; +}; + +&ioportd { + port-irqs = <&port_irq17 &port_irq18 &port_irq19 + &port_irq20 &port_irq21 &port_irq22 &port_irq23>; + port-irq-names = "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq23"; + port-irq17-pins = <7>; + port-irq18-pins = <6>; + port-irq19-pins = <5>; + port-irq20-pins = <4>; + port-irq21-pins = <2 3>; + port-irq22-pins = <1>; + port-irq23-pins = <0>; +}; diff --git a/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi b/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi index 80b50662bae1f..365ab7a533e68 100644 --- a/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi +++ b/dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi @@ -59,14 +59,6 @@ status = "disabled"; }; - sdram: sdram-controller@40002000 { - compatible = "renesas,ra-sdram"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40002000 0xFFF>; - status = "disabled"; - }; - lcdif: display-controller@40342000 { compatible = "renesas,ra-glcdc"; reg = <0x40342000 0x1454>; diff --git a/dts/arm/renesas/ra/ra8/ra8x2.dtsi b/dts/arm/renesas/ra/ra8/ra8x2.dtsi index 39f873da7349a..690aed5ee933e 100644 --- a/dts/arm/renesas/ra/ra8/ra8x2.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x2.dtsi @@ -95,7 +95,7 @@ status = "okay"; }; - mram: mram-controller@4013c000 { + mram_ctrl: mram-controller@4013c000 { compatible = "renesas,ra-mram-controller"; reg = <0x4013c000 0x4000>; #address-cells = <1>; @@ -728,6 +728,61 @@ status = "disabled"; }; + i2s0: ssie@4025d000 { + compatible = "renesas,ra-i2s-ssie"; + #address-cells = <1>; + #size-cells = <0>; + channel = <0>; + reg = <0x4025d000 0x28>; + clocks = <&pclkb MSTPC 8>; + clock-names = "pclk"; + full-duplex; + status = "disabled"; + }; + + i2s1: ssie@4025d100 { + compatible = "renesas,ra-i2s-ssie"; + #address-cells = <1>; + #size-cells = <0>; + channel = <1>; + reg = <0x4025d100 0x28>; + clocks = <&pclkb MSTPC 7>; + clock-names = "pclk"; + status = "disabled"; + }; + + sdram: sdram-controller@40003c00 { + compatible = "renesas,ra-sdram"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x54>; + status = "disabled"; + }; + + dma0: dma@4000a000 { + compatible = "renesas,ra-dma"; + reg = <0x4000a000 0x34>, <0x4000a800 0xa0>; + reg-names = "channel", "common"; + clocks = <&iclk MSTPA 22>; + dma-channels = <8>; + #dma-cells = <2>; + status = "disabled"; + }; + + crc: crc@40310000 { + compatible = "renesas,ra-crc"; + reg = <0x40310000 0x10>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + + wdt0: wdt@40202600 { + compatible = "renesas,ra-wdt"; + reg = <0x40202600 0x12>; + clocks = <&pclkb 0 0>; + status = "disabled"; + }; + acmphs_global: acmphs_global@40236000 { compatible = "renesas,ra-acmphs-global"; reg = <0x40236000 0x400>; diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index 42ff9d99fc336..31cb6fd04157a 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -85,3 +85,9 @@ family: cpuclusters: - name: cm85 - name: cm33 + - name: ra8d2 + socs: + - name: r7ka8d2kflcac + cpuclusters: + - name: cm85 + - name: cm33 From 6dfd3a9ea882db50fbb202382ea47abd4db479b0 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Fri, 29 Aug 2025 09:07:03 +0700 Subject: [PATCH 05/25] boards: renesas: Add support Renesas ek_ra8d2 board Add support Renesas ek_ra8d2 board Signed-off-by: Khoa Tran Signed-off-by: Khoa Nguyen --- boards/renesas/ek_ra8d2/CMakeLists.txt | 7 + boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2 | 6 + boards/renesas/ek_ra8d2/board.cmake | 11 + boards/renesas/ek_ra8d2/board.yml | 6 + boards/renesas/ek_ra8d2/doc/ek_ra8d2.webp | Bin 0 -> 63480 bytes boards/renesas/ek_ra8d2/doc/index.rst | 233 ++++++++++++++++++ boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi | 165 +++++++++++++ boards/renesas/ek_ra8d2/ek_ra8d2.dtsi | 224 +++++++++++++++++ .../ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts | 213 ++++++++++++++++ .../ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.yaml | 12 + .../ek_ra8d2_r7ka8d2kflcac_cm85_defconfig | 11 + boards/renesas/ek_ra8d2/sdram.ld | 19 ++ 12 files changed, 907 insertions(+) create mode 100644 boards/renesas/ek_ra8d2/CMakeLists.txt create mode 100644 boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2 create mode 100644 boards/renesas/ek_ra8d2/board.cmake create mode 100644 boards/renesas/ek_ra8d2/board.yml create mode 100644 boards/renesas/ek_ra8d2/doc/ek_ra8d2.webp create mode 100644 boards/renesas/ek_ra8d2/doc/index.rst create mode 100644 boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi create mode 100644 boards/renesas/ek_ra8d2/ek_ra8d2.dtsi create mode 100644 boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts create mode 100644 boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.yaml create mode 100644 boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85_defconfig create mode 100644 boards/renesas/ek_ra8d2/sdram.ld diff --git a/boards/renesas/ek_ra8d2/CMakeLists.txt b/boards/renesas/ek_ra8d2/CMakeLists.txt new file mode 100644 index 0000000000000..6e7e11bab968b --- /dev/null +++ b/boards/renesas/ek_ra8d2/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_linker_sources_ifdef(CONFIG_MEMC + SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2 b/boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2 new file mode 100644 index 0000000000000..53c51de3a516a --- /dev/null +++ b/boards/renesas/ek_ra8d2/Kconfig.ek_ra8d2 @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA8D2 + select SOC_R7KA8D2KFLCAC_CM85 if BOARD_EK_RA8D2_R7KA8D2KFLCAC_CM85 + select SOC_R7KA8D2KFLCAC_CM33 if BOARD_EK_RA8D2_R7KA8D2KFLCAC_CM33 diff --git a/boards/renesas/ek_ra8d2/board.cmake b/boards/renesas/ek_ra8d2/board.cmake new file mode 100644 index 0000000000000..09d7be5346f8b --- /dev/null +++ b/boards/renesas/ek_ra8d2/board.cmake @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_R7KA8D2KFLCAC_CM85) + board_runner_args(jlink "--device=R7KA8D2KF_CPU0" "--reset-after-load") +endif() + +board_runner_args(pyocd "--target=R7KA8D2KF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8d2/board.yml b/boards/renesas/ek_ra8d2/board.yml new file mode 100644 index 0000000000000..7df2196f1b7e9 --- /dev/null +++ b/boards/renesas/ek_ra8d2/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_ra8d2 + full_name: RA8D2 Evaluation Kit + vendor: renesas + socs: + - name: r7ka8d2kflcac diff --git a/boards/renesas/ek_ra8d2/doc/ek_ra8d2.webp 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index 0000000000000..54ef9c3d0dcf7 --- /dev/null +++ b/boards/renesas/ek_ra8d2/doc/index.rst @@ -0,0 +1,233 @@ +.. zephyr:board:: ek_ra8d2 + +Overview +******** + +The EK-RA8D2 is an Evaluation Kit for Renesas RA8D2 MCU Group which integrates multiple series of software-compatible +Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient +platform-based product development + +The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® Cortex®-M33 +core running up to 250 MHz with the following features: + +- Up to 1 MB MRAM +- 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM) +- Octal Serial Peripheral Interface (OSPI) +- Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface +- Graphics LCD Controller (GLCDC) +- 2D Drawing Engine (DRW) +- MIPI DSI/CSI interface +- Analog peripherals +- Security and safety features + +**MCU Native Pin Access** + +- 1 GHz Arm® Cortex®-M85 core and 250 MHz Arm® Cortex®-M33 core based RA8D2 MCU in 289 pins, BGA package +- 1 MB MRAM, 2 MB SRAM with ECC +- Native pin access through 2 x 20-pin, and 2 x 40-pin headers (not populated) +- Parallel Graphics Expansion Port +- Camera Expansion Port (present at the underside of the EK-RA8D2 board) +- MIPI Graphics Expansion Port (present at the underside of the EK-RA8D2 board) +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clocks. + Additional low-precision clocks are available internal to the RA8D2 MCU + +**System Control and Ecosystem Access** + +- Four 5 V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD and JTAG) + - Debug in (ETM, SWD, SWO, and JTAG) + - Debug out (SWD, SWO, and JTAG) + +- User LEDs, Status LEDs and switches + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power. + - Debug LED (yellow) indicating the debug connection. + - Ethernet LEDs (amber, yellow, green) + - Two User switches, One Reset switch + +- Five most popular ecosystems expansions + + - Two Seeed Grove® system (I2C/I3C/Analog) connectors (not populated) + - SparkFun® Qwiic® connector (not populated) + - Two Digilent PmodTM (SPI, UART and I2C) connectors + - Arduino™ (Uno R3) connector + - MikroElektronikaTM mikroBUS™ connector (not populated) + +- USB Full Speed Host and Device (USB-C connector) +- MCU boot configuration jumper + +**Special Feature Access** + +- USB High Speed Host and Device (USB-C connector) +- Ethernet (RJ45 RGMII interface) +- 64 MB (512 Mb) External Octo-SPI Flash (present in the MCU Native Pin Access area) +- 64 MB (512 Mb) SDRAM (present in the MCU Native Pin Access area) +- PDM MEMS Microphones (present at the underside of the EK-RA8D2 board) +- Audio CODEC with speaker out connections +- Configuration switches + +Hardware +******** + +Detailed hardware features can be found at: + +- RA8D2 MCU: `RA8D2 Group User's Manual Hardware`_ +- EK-RA8D2 board: `EK-RA8D2 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + + - For using the Camera Expansion Port (J35) in DVP interface, please set switch SW4 as following configuration: + + +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+ + | SW4-1 PMOD1 | SW4-2 PMOD1 | SW4-3 Octo-SPI | SW4-4 Arduino | SW4-5 I3C | SW4-6 MIPI | SW4-7 USBFS | SW4-8 USBHS | + +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+ + | - | - | - | - | OFF | ON | - | - | + +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+ + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``ek_ra8d2`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Here is an example for the :zephyr:code-sample:`hello_world` application on CM85 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ek_ra8d2/r7ka8d2kflcac/cm85 + :goals: flash + +Open a serial terminal, reset the board (Pressing the reset switch SW3), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx ***** + Hello World! ek_ra8d2/r7ka8d2kflcac/cm85 + +Flashing +======== + +Program can be flashed to EK-RA8D2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/ + +To flash the program to board + +1. Connect to J-Link OB via USB port to host PC + +2. Make sure J-Link OB jumper is in default configuration as described in `EK-RA8D2 - User's Manual`_ + +3. Execute west command + + .. code-block:: console + + west flash -r jlink + +MCUboot bootloader +================== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ek_ra8d2/r7ka8d2kflcac/cm85 + :goals: build flash + :west-args: --sysbuild + :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y + +By default, Sysbuild creates MCUboot and user application images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + | └── zephyr + │ ├── zephyr.elf + │ ├── zephyr.hex + │ ├── zephyr.bin + │ ├── zephyr.signed.bin + │ └── zephyr.signed.hex + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ ├── zephyr.hex + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option, MCUboot will be rebuilt and reflashed + every time the pristine build is used. + +To only flash the user application in the subsequent builds, Use: + +.. code-block:: console + + $ west flash --domain hello_world + +For more information about the system build please read the :ref:`sysbuild` documentation. + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting MCUboot v2.2.0-171-g8513be710e5e *** + *** Using Zephyr OS build v4.2.0-6343-g2ce9ea10e7df *** + I: Starting bootloader + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Boot source: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Bootloader chainload address offset: 0x10000 + I: Image version: v0.0.0 + I: Jumping to the first image slot + *** Booting Zephyr OS build v4.2.0-6343-g2ce9ea10e7df *** + Hello World! ek_ra8d2/r7ka8d2kflcac/cm85 + +References +********** +- `EK-RA8D2 Website`_ +- `RA8D2 MCU group Website`_ + +.. _EK-RA8D2 Website: + https://www.renesas.com/en/design-resources/boards-kits/ek-ra8d2 + +.. _RA8D2 MCU group Website: + https://www.renesas.com/en/products/ra8d2 + +.. _EK-RA8D2 - User's Manual: + https://www.renesas.com/en/document/mat/ek-ra8d2-v1-users-manual + +.. _RA8D2 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/ra8d2-group-users-manual-hardware diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi b/boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi new file mode 100644 index 0000000000000..107eae94f06a9 --- /dev/null +++ b/boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* TX8 RX8 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + sci7_default: sci7_default { + group1 { + /* TX7 RX7 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISO1 MOSI1 SSLB0 */ + psels = , + , + ; + drive-strength = "high"; + }; + + group2 { + /* RSPCK1 */ + psels = ; + drive-strength = "highspeed-high"; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = , + ; + drive-strength = "medium"; + }; + }; + + pwm12_default: pwm12_default { + group1 { + /* GTIOC12A */ + psels = ; + drive-strength = "medium"; + }; + }; + + ceu_default: ceu_default { + group1 { + psels = , /* VIO_D0 */ + , /* VIO_D1 */ + , /* VIO_D2 */ + , /* VIO_D3 */ + , /* VIO_D4 */ + , /* VIO_D5 */ + , /* VIO_D6 */ + , /* VIO_D7 */ + , /* VIO_CLK */ + , /* VIO_HD */ + ; /* VIO_VD */ + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* VBUS */ + drive-strength = "high"; + }; + }; + + usbfs_default: usbfs_default { + group1 { + psels = , /* USB_DM */ + , /* USB_DP */ + ; /* VBUS */ + drive-strength = "high"; + }; + }; + + sdram_default: sdram_default { + group1 { + psels = , /* SDRAM_A2 */ + , /* SDRAM_A3 */ + , /* SDRAM_A4 */ + , /* SDRAM_A5 */ + , /* SDRAM_A6 */ + , /* SDRAM_A7 */ + , /* SDRAM_A8 */ + , /* SDRAM_A9 */ + , /* SDRAM_A10 */ + , /* SDRAM_A11 */ + , /* SDRAM_A12 */ + , /* SDRAM_A13 */ + , /* SDRAM_A14 */ + , /* SDRAM_A15 */ + , /* SDRAM_A16 */ + , /* SDRAM_CAS */ + , /* SDRAM_CKE */ + , /* SDRAM_DQ0 */ + , /* SDRAM_DQ1 */ + , /* SDRAM_DQ2 */ + , /* SDRAM_DQ3 */ + , /* SDRAM_DQ4 */ + , /* SDRAM_DQ5 */ + , /* SDRAM_DQ6 */ + , /* SDRAM_DQ7 */ + , /* SDRAM_DQ8 */ + , /* SDRAM_DQ9 */ + , /* SDRAM_DQ10 */ + , /* SDRAM_DQ11 */ + , /* SDRAM_DQ12 */ + , /* SDRAM_DQ13 */ + , /* SDRAM_DQ14 */ + , /* SDRAM_DQ15 */ + , /* SDRAM_DQ16 */ + , /* SDRAM_DQ17 */ + , /* SDRAM_DQ18 */ + , /* SDRAM_DQ19 */ + , /* SDRAM_DQ20 */ + , /* SDRAM_DQ21 */ + , /* SDRAM_DQ22 */ + , /* SDRAM_DQ23 */ + , /* SDRAM_DQ24 */ + , /* SDRAM_DQ25 */ + , /* SDRAM_DQ26 */ + , /* SDRAM_DQ27 */ + , /* SDRAM_DQ28 */ + , /* SDRAM_DQ29 */ + , /* SDRAM_DQ30 */ + , /* SDRAM_DQ31 */ + , /* SDRAM_DQM0 */ + , /* SDRAM_DQM1 */ + , /* SDRAM_DQM2 */ + , /* SDRAM_DQM3 */ + , /* SDRAM_RAS */ + , /* SDRAM_CS */ + ; /* SDRAM_WE */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDRAM_CLK */ + drive-strength = "highspeed-high"; + }; + }; +}; diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi b/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi new file mode 100644 index 0000000000000..a795d560ffc5f --- /dev/null +++ b/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "ek_ra8d2-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport3 3 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioporta 7 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + status = "disabled"; + }; + + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + status = "disabled"; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 4 0>, /* AN */ + <1 0 &ioport2 1 0>, /* RST */ + <2 0 &ioport1 3 0>, /* CS */ + <3 0 &ioport1 2 0>, /* SCK */ + <4 0 &ioport1 0 0>, /* MISO */ + <5 0 &ioport1 1 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport8 10 0>, /* PWM */ + <7 0 &ioportd 1 0>, /* INT */ + <8 0 &ioport8 8 0>, /* RX */ + <9 0 &ioport8 9 0>, /* TX */ + <10 0 &ioport5 12 0>, /* SCL */ + <11 0 &ioport5 11 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arducam_ffc_40pin_connector: arducam-ffc-40pin-connector { + compatible = "arducam,ffc-40pin-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0x0 0x3f>; + gpio-map = ; + }; + + sdram1: sdram@68000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x68000000 DT_SIZE_M(64)>; + zephyr,memory-region = "SDRAM"; + status = "okay"; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&pll { + status = "okay"; + + pllp: pllp { + status = "okay"; + }; + + pllq: pllq { + status = "okay"; + }; + + pllr: pllr { + status = "okay"; + }; +}; + +&pll2 { + status = "okay"; + + pll2p { + status = "okay"; + }; + + pll2q { + status = "okay"; + }; + + pll2r { + status = "okay"; + }; +}; + +&subclk { + status = "okay"; +}; + +&sciclk { + status = "okay"; +}; + +&lcdclk { + status = "okay"; +}; + +&gptclk { + status = "okay"; +}; + +&uclk { + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport7 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&ioport8 { + status = "okay"; +}; + +&ioportd { + status = "okay"; +}; + +&usbfs { + pinctrl-0 = <&usbfs_default>; + pinctrl-names = "default"; + maximum-speed = "full-speed"; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&sdram { + pinctrl-0 = <&sdram_default>; + pinctrl-names = "default"; + status = "okay"; + auto-refresh-interval = ; + auto-refresh-count = ; + precharge-cycle-count = ; + multiplex-addr-shift = "9-bit"; + edian-mode = "little-endian"; + continuous-access; + bus-width = "32-bit"; + + bank@0 { + reg = <0>; + renesas,ra-sdram-timing = ; + }; +}; diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts new file mode 100644 index 0000000000000..2aad05ce741eb --- /dev/null +++ b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ek_ra8d2.dtsi" +#include + +/ { + model = "Renesas EK-RA8D2"; + compatible = "renesas,ra8d2", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_mram_cm85; + zephyr,flash-controller = &mram_ctrl; + zephyr,code-partition = &slot0_partition; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + zephyr,crc = &crc; + }; + + aliases { + led0 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdt0; + }; +}; + +&button0 { + status = "okay"; +}; + +&button1 { + status = "okay"; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart7: uart { + current-speed = <115200>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + interrupts = <12 1>, <13 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + interrupts = <14 1>, <15 1>, <16 1>, <17 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; +}; + +&port_irq12 { + interrupts = <18 1>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <19 1>; + status = "okay"; +}; + +&ulpt0 { + interrupts = <20 1>; + interrupt-names = "ulpti"; + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&ulpt1 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&port_irq12 { + interrupts = <21 1>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <22 1>; + status = "okay"; +}; + +&crc { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12_default>; + interrupts = <23 1>, <24 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + + cam_clock: pwmclock { + compatible = "pwm-clock"; + status = "disabled"; + #clock-cells = <1>; + pwms = <&pwm12 0 PWM_KHZ(12000) PWM_POLARITY_NORMAL>; + }; +}; + +&ceu { + pinctrl-0 = <&ceu_default>; + pinctrl-names = "default"; + interrupts = <25 1>; + interrupt-names = "ceui"; + clocks = <&pclka MSTPC 16>, <&cam_clock 0>; + clock-names = "pclk", "cam-xclk"; + burst-transfer = <256>; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + interrupts = <26 1>; + interrupt-names = "usbhs-ir"; + status = "okay"; + + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&code_mram_cm85 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(472)>; + }; + + slot1_partition: partition@86000 { + label = "image-1"; + reg = <0x86000 DT_SIZE_K(472)>; + }; + + storage_partition: partition@fc000 { + label = "storage"; + reg = <0xfc000 DT_SIZE_K(16)>; + }; + }; +}; + +zephyr_lcdif: &lcdif {}; + +mikrobus_serial: &uart7 {}; + +mikrobus_i2c: &iic1 {}; + +mikrobus_spi: &spi1 {}; + +arducam_ffc_40pin_i2c: &iic1 {}; + +arducam_ffc_40pin_dvp_interface: &ceu {}; + +arducam_ffc_40pin_dvp_xclk: &cam_clock {}; diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.yaml b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.yaml new file mode 100644 index 0000000000000..bb353d08952a4 --- /dev/null +++ b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra8d2/r7ka8d2kflcac/cm85 +name: Renesas EK-RA8D2 +type: mcu +arch: arm +ram: 1664 +flash: 1024 +toolchain: + - zephyr +supported: + - gpio + - uart +vendor: renesas diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85_defconfig b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85_defconfig new file mode 100644 index 0000000000000..2f9e7c584905b --- /dev/null +++ b/boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra8d2/sdram.ld b/boards/renesas/ek_ra8d2/sdram.ld new file mode 100644 index 0000000000000..44d2efd360ccb --- /dev/null +++ b/boards/renesas/ek_ra8d2/sdram.ld @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) + +SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) +{ + __SDRAM_Start = .; + KEEP(*(.sdram*)) +#ifdef CONFIG_LVGL + KEEP(*(.lvgl_buf*)) +#endif + __SDRAM_End = .; +} GROUP_LINK_IN(SDRAM) + +#endif From 05237f22ea0488e055f57e03222ba364e0bcb586 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Thu, 9 Oct 2025 21:07:44 +0700 Subject: [PATCH 06/25] boards: shields: Add support ArduCam CU450 OV5640 for ek_ra8d2 Add support ArduCam CU450 OV5640 shield for Renesas ek_ra8d2 board Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 boards/shields/arducam_cu450_ov5640/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/boards/shields/arducam_cu450_ov5640/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/boards/shields/arducam_cu450_ov5640/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..755468328f221 --- /dev/null +++ b/boards/shields/arducam_cu450_ov5640/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pwm12 { + status = "okay"; +}; + +&arducam_ffc_40pin_i2c { + clock-frequency = ; +}; + +&arducam_ffc_40pin_dvp_xclk { + clock-frequency = ; + status = "okay"; +}; + +&arducam_ffc_40pin_dvp_interface { + swap-8bits; + swap-16bits; + swap-32bits; + + port { + dvp_ffc40_ep_in: endpoint { + hsync-sample = <1>; + vsync-sample = <1>; + }; + }; +}; From 1f56fa8f7e113bf71b9e91b431451c156a59b965 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Tue, 23 Sep 2025 17:14:58 +0700 Subject: [PATCH 07/25] boards: shields: Add support rtklcdpar1s00001be for ek_ra8d2 Add support rtklcdpar1s00001be display shield for Renesas RA ek_ra8d2 board Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.defconfig | 24 +++++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 93 +++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.defconfig create mode 100644 boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.defconfig b/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.defconfig new file mode 100644 index 0000000000000..353b6d14c712a --- /dev/null +++ b/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA8D2 + +if DISPLAY + +config MEMC + default y + +config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION + default ".sdram" + depends on RENESAS_RA_GLCDC + +endif # DISPLAY + +if LVGL + +config LV_Z_VDB_CUSTOM_SECTION + default y + +endif # LVGL + +endif # BOARD_EK_RA8D2 diff --git a/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..b1e178eb899a7 --- /dev/null +++ b/boards/shields/rtklcdpar1s00001be/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + renesas_parallel_graphics_connector: parallel-graphics-connector { + compatible = "renesas,ra-parallel-graphics-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &ioport5 14 0>, /* DISP_BLEN */ + <2 0 &ioport5 11 0>, /* IIC_SDA */ + <3 0 &ioport1 11 0>, /* DISP_INT */ + <4 0 &ioport5 12 0>, /* IIC_SCL */ + <6 0 &ioport6 6 0>; /* DISP_RST */ + }; +}; + +&port_irq19 { + interrupts = <90 1>; + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&pinctrl { + glcdc_default: glcdc_default { + group1 { + psels = , /* LCDC_TCON0 */ + , /* LCDC_TCON1 */ + , /* LCDC_TCON2 */ + , /* LCDC_TCON3 */ + , /* LCDC_DATA00 */ + , /* LCDC_DATA01 */ + , /* LCDC_DATA02 */ + , /* LCDC_DATA03 */ + , /* LCDC_DATA04 */ + , /* LCDC_DATA05 */ + , /* LCDC_DATA06 */ + , /* LCDC_DATA07 */ + , /* LCDC_DATA08 */ + , /* LCDC_DATA09 */ + , /* LCDC_DATA10 */ + , /* LCDC_DATA11 */ + , /* LCDC_DATA12 */ + , /* LCDC_DATA13 */ + , /* LCDC_DATA14 */ + , /* LCDC_DATA15 */ + , /* LCDC_DATA16 */ + , /* LCDC_DATA17 */ + , /* LCDC_DATA18 */ + , /* LCDC_DATA19 */ + , /* LCDC_DATA20 */ + , /* LCDC_DATA21 */ + , /* LCDC_DATA22 */ + , /* LCDC_DATA23 */ + ; /* LCDC_EXTCLK */ + drive-strength = "medium"; + }; + + group2 { + /* LCDC_CLK */ + psels = ; + drive-strength = "high"; + }; + }; +}; + +&zephyr_lcdif { + interrupts = <71 1>; + interrupt-names = "line"; + pinctrl-0 = <&glcdc_default>; + pinctrl-names = "default"; + output-pin-hsync = "TCON_PIN_1"; + output-pin-vsync = "TCON_PIN_0"; + output-pin-de = "TCON_PIN_2"; +}; + +&iic1 { + clock-frequency = ; +}; From 69b3777da30f6202ddb093698d4f887bd17df08d Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 16:15:22 +0700 Subject: [PATCH 08/25] samples: drivers: counter: Add support for alarm on ek_ra8d2 Add support for sample app alarm on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 samples/drivers/counter/alarm/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/samples/drivers/counter/alarm/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/samples/drivers/counter/alarm/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..2326dcf2a423e --- /dev/null +++ b/samples/drivers/counter/alarm/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <95 1>, <94 1>; + interrupt-names = "agti", "agtcmai"; + renesas,prescaler = <4>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; From d3f4d6fa0945c6dc9fa5e723c00c026947156e15 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Tue, 23 Sep 2025 14:39:11 +0700 Subject: [PATCH 09/25] samples: drivers: i2s: Add sample support for Renesas ek_ra8d2 Add support for i2s sample app on Renesas RA ek_ra8d2: - samples/drivers/i2s/output Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 4 ++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 58 +++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..7f81a35b58584 --- /dev/null +++ b/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 diff --git a/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..9e2a8501f2eb6 --- /dev/null +++ b/samples/drivers/i2s/output/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-tx = &i2s1; + }; +}; + +&pinctrl { + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + drive-strength = "medium"; + }; + }; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <93 1>, <92 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(2822400) PWM_POLARITY_NORMAL>; + }; +}; From 1d3bd22dd3aa07615126f48229881d5228adce17 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:08:01 +0700 Subject: [PATCH 10/25] samples: subsys: fs: Add tests support for Renesas ek_ra8d2 board Add tests support for Renesas ek_ra8d2 boards: - samples/subsys/fs Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 samples/subsys/fs/fs_sample/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/samples/subsys/fs/fs_sample/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/samples/subsys/fs/fs_sample/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..a9cf3d3c753d0 --- /dev/null +++ b/samples/subsys/fs/fs_sample/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; From 68401b63c79cfd487e49041827c003169232d4d3 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:17:31 +0700 Subject: [PATCH 11/25] samples: modules: lvgl: demos: add support for ek_ra8d2 Add support for ek_ra8d2/r7ka8d2kflcac/cm85 running on rtklcdpar1s00001be display shield Signed-off-by: Khoa Tran --- .../lvgl/demos/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 7 +++++++ samples/modules/lvgl/demos/sample.yaml | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 samples/modules/lvgl/demos/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf diff --git a/samples/modules/lvgl/demos/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/samples/modules/lvgl/demos/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..e5e710f1cfb73 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LV_Z_MEM_POOL_SIZE=245760 +CONFIG_LV_DRAW_LAYER_SIMPLE_BUF_SIZE=49152 +CONFIG_MAIN_STACK_SIZE=8192 +CONFIG_IDLE_STACK_SIZE=1024 diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml index 04e0ac3382bf5..1faa12e1593d6 100644 --- a/samples/modules/lvgl/demos/sample.yaml +++ b/samples/modules/lvgl/demos/sample.yaml @@ -79,7 +79,9 @@ tests: tags: - shield sample.modules.lvgl.demos.rtklcdpar1s00001be: - platform_allow: ek_ra8p1/r7ka8p1kflcac/cm85 + platform_allow: + - ek_ra8p1/r7ka8p1kflcac/cm85 + - ek_ra8d2/r7ka8d2kflcac/cm85 harness: console harness_config: fixture: fixture_display From 2799b3cd50952383d6689c735ab0f329abe596a8 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 13:03:24 +0700 Subject: [PATCH 12/25] tests: drivers: i2c: Add support for i2c_api on ek_ra8d2 Add support for test app "i2c_api" on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 4 ++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 16 ++++++++ ...ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.conf | 4 ++ ...ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.overlay | 38 +++++++++++++++++++ tests/drivers/i2c/i2c_api/testcase.yaml | 1 + 5 files changed, 63 insertions(+) create mode 100644 tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.conf create mode 100644 tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.overlay diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..3b626dd7fad28 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SENSOR_GY271_QMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..7ce912036360c --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &iic1; + gy271 = &iic1; + }; +}; + +&iic1 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.conf new file mode 100644 index 0000000000000..3b626dd7fad28 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SENSOR_GY271_QMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.overlay new file mode 100644 index 0000000000000..b3182d9d2460e --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85_sci_b_i2c.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &i2c0; + gy271 = &i2c0; + }; +}; + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + drive-open-drain; + }; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "rxi", "txi", "tei"; + status = "okay"; + + i2c0: i2c { + sda-output-delay = <300>; + noise-filter-clock-select = <1>; + bit-rate-modulation; + status = "okay"; + }; +}; diff --git a/tests/drivers/i2c/i2c_api/testcase.yaml b/tests/drivers/i2c/i2c_api/testcase.yaml index 1f31eeea5e53f..44c47e4d9ded9 100644 --- a/tests/drivers/i2c/i2c_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_api/testcase.yaml @@ -28,6 +28,7 @@ tests: - ek_ra8p1/r7ka8p1kflcac/cm85 - ek_ra8p1/r7ka8p1kflcac/cm33 - mck_ra8t2/r7ka8t2lfecac/cm85 + - ek_ra8d2/r7ka8d2kflcac/cm85 extra_args: - DTC_OVERLAY_FILE="./boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}_sci_b_i2c.overlay" - CONF_FILE="./prj.conf ./boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}_sci_b_i2c.conf" From 5dce48784275dc92359ac41dc08c4dfd9e8ccb5a Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 15:18:39 +0700 Subject: [PATCH 13/25] tests: drivers: uart: Add support for uart_async_api on ek_ra8d2 Add support for test app "uart_async_api" on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/uart/uart_async_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..9dcf49056b26e --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +dut: &uart7 { + current-speed = <115200>; + status = "okay"; +}; From dd19d494a289532236f21bd4648a74713ca37699 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 15:22:17 +0700 Subject: [PATCH 14/25] tests: drivers: spi: Add support for spi_loopback on ek_ra8d2 Add support for test app "spi_loopback" on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 6 +++++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 22 +++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..9c7b8ccf32d37 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI_LOOPBACK_MODE_LOOP=y +CONFIG_SPI_B_INTERRUPT=y +CONFIG_SPI_B_RA_DTC=y diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..9257a82974c0a --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi1 { + rx-dtc; + tx-dtc; + status = "okay"; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; From f3b4c3107d949522193055c625177ac459e22271 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 15:45:48 +0700 Subject: [PATCH 15/25] tests: drivers: pwm: Add pwm tests support for ek_ra8d2 Add support for test apps on Renesas ek_ra8d2: - tests/drivers/pwm/pwm_api - tests/drivers/pwm/pwm_loopback Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 10 ++++++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 34 +++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 tests/drivers/pwm/pwm_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/drivers/pwm/pwm_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/pwm/pwm_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..8722f5559af65 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pwm-test = &pwm1; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..abf9690ac4bd1 --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + /* first index must be a 32-Bit timer */ + pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, + <&pwm10 0 0 PWM_POLARITY_NORMAL>; + }; +}; + +&pinctrl { + pwm10_default: pwm10_default { + group1 { + /* GTIOC2A */ + psels = ; + drive-strength = "medium"; + }; + }; +}; + +&pwm10{ + pinctrl-0 = <&pwm10_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; From f1a9497e1aab3effe67559f33f6e127af0a8f0e8 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 16:09:10 +0700 Subject: [PATCH 16/25] tests: drivers: comparator: Add support gpio_loopback on ek_ra8d2 Add support for test app "gpio_loopback" on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 tests/drivers/comparator/gpio_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..923e6fcab13d8 --- /dev/null +++ b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + test-comp = &acmphs2; + }; + + zephyr,user { + test-gpios = <&ioport0 14 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + acmphs2_ivcmp0: acmphs2_ivcmp0 { + group1 { + /* CH2 IVCMP0 */ + psels = ; + renesas,analog-enable; + }; + }; +}; + +&acmphs_global { + status = "okay"; + + acmphs2 { + pinctrl-0 = <&acmphs2_ivcmp0>; + pinctrl-names = "default"; + interrupts = <95 1>; + interrupt-names = "hs"; + reference-input-source = "ivref2"; + compare-input-source = "ivcmp0"; + noise-filter = <1>; + status = "okay"; + }; +}; From 5e7b782249438737ee9765843e7a437476a69187 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 16:25:52 +0700 Subject: [PATCH 17/25] tests: drivers: counter: Add test support for Renesas ek_ra8d2 Add support for test app on Renesas ek_ra8d2: - tests/drivers/counter/counter_basic_api Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/counter/counter_basic_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..82b9544b14e2c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <95 1>, <94 1>; + interrupt-names = "agti", "agtcmai"; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <0>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; From 24845d4e23571edb6e0bf0a4227ba00c6ba47432 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Tue, 23 Sep 2025 14:33:25 +0700 Subject: [PATCH 18/25] tests: drivers: i2s: Add tests support for Renesas ek_ra8d2 Add support for i2s tests app on Renesas RA ek_ra8d2: - tests/drivers/i2s/i2s_api - tests/drivers/i2s/i2s_speed Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 6 ++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 79 +++++++++++++++++++ .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 11 +++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 79 +++++++++++++++++++ 4 files changed, 175 insertions(+) create mode 100644 tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..8d938df796d10 --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 +CONFIG_I2S_TEST_USE_GPIO_LOOPBACK=y +CONFIG_I2S_TEST_SEPARATE_DEVICES=y diff --git a/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..94fc0a7141864 --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-node0 = &i2s1; + i2s-node1 = &i2s0; + }; +}; + +&pinctrl { + ssie0_default: ssie0_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_TX */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + drive-strength = "medium"; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&ssie0_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <92 1>, <91 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <90 1>, <89 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(512000) PWM_POLARITY_NORMAL>; + }; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..70e94e25598a1 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 +CONFIG_I2S_TEST_USE_GPIO_LOOPBACK=y +CONFIG_I2S_TEST_SEPARATE_DEVICES=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_8000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_16000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_32000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_48000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_96000=y diff --git a/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..7b5c19dd40cef --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-node0 = &i2s1; + i2s-node1 = &i2s0; + }; +}; + +&pinctrl { + ssie0_default: ssie0_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_TX */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + drive-strength = "medium"; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&ssie0_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <92 1>, <91 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <90 1>, <89 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(2822400) PWM_POLARITY_NORMAL>; + }; +}; From 7df9bdbc7539ed138011663b3a080125019ed553 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Tue, 23 Sep 2025 14:40:34 +0700 Subject: [PATCH 19/25] tests: drivers: dma: Add test support dma driver on ek_ra8d2 This commit adds testing support for dma driver on ek_ra8d2: - tests/drivers/dma/chan_blen_transfer - tests/drivers/dma/loop_transfer Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 11 +++++++++++ .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/drivers/dma/loop_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..2caebf0e9eb87 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma0 { + status = "okay"; + interrupts = <95 1>, <94 1>; + interrupt-names = "ch0", "ch1"; +}; diff --git a/tests/drivers/dma/loop_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/dma/loop_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..d3afbdb4c6197 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma0 { + status = "okay"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "ch0", "ch1", "ch2"; +}; From c2721157052b15b48bc10c754a3a75c4e426dfa0 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Tue, 23 Sep 2025 17:18:39 +0700 Subject: [PATCH 20/25] tests: drivers: display: Add support display_read_write on ek_ra8d2 Add support test app display_read_write for Renesas RA ek_ra8d2 board Signed-off-by: Khoa Tran --- .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 tests/drivers/display/display_read_write/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf diff --git a/tests/drivers/display/display_read_write/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/drivers/display/display_read_write/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..94daff98cab0b --- /dev/null +++ b/tests/drivers/display/display_read_write/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_DISPLAY_BUFFER_USE_GENERIC_SECTION=y +CONFIG_DISPLAY_BUFFER_SECTION=".sdram" +CONFIG_DISPLAY_BUFFER_ALIGNMENT=64 From 9d925bf73ceda7f74854ccf3a06b3de23b3b5ae8 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:04:05 +0700 Subject: [PATCH 21/25] tests: drivers: sdhc: Add tests support for Renesas ek_ra8d2 board Add tests support for Renesas ek_ra8d2 boards Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 tests/drivers/sdhc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/sdhc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/sdhc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..b64255fd34d57 --- /dev/null +++ b/tests/drivers/sdhc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; From 795efc922ef80d8b118c0941a2847ea4ec9c8567 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:05:50 +0700 Subject: [PATCH 22/25] tests: drivers: disk: Add tests support for Renesas ek_ra8d2 board Add tests support for Renesas ek_ra8d2 boards: - tests/drivers/disk/disk_access - tests/drivers/disk/disk_performance Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 38 ++++++++++++++++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 44 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 tests/drivers/disk/disk_access/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/drivers/disk/disk_performance/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/drivers/disk/disk_access/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/disk/disk_access/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..a9cf3d3c753d0 --- /dev/null +++ b/tests/drivers/disk/disk_access/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/tests/drivers/disk/disk_performance/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/drivers/disk/disk_performance/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..b64255fd34d57 --- /dev/null +++ b/tests/drivers/disk/disk_performance/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; From 495c150cfef6f0ff96c5fc1206a47fa0e32ec6e2 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:04:56 +0700 Subject: [PATCH 23/25] tests: subsys: sd: Add tests support for Renesas ek_ra8d2 board Add tests support for Renesas ek_ra8d2 boards: - tests/subsys/sd/sdmmc Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 tests/subsys/sd/sdmmc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/subsys/sd/sdmmc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/subsys/sd/sdmmc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..b64255fd34d57 --- /dev/null +++ b/tests/subsys/sd/sdmmc/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; From c3df6117842e7c548da9cb790b9331951a7d6290 Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Mon, 6 Oct 2025 17:06:51 +0700 Subject: [PATCH 24/25] tests: subsys: fs: Add tests support for Renesas ek_ra8d2 board Add tests support for Renesas ek_ra8d2 boards: - tests/subsys/fs/ext2 - tests/subsys/fs/fat_fs_api Signed-off-by: Khoa Tran --- .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 48 +++++++++++++++++++ .../boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf | 7 +++ .../ek_ra8d2_r7ka8d2kflcac_cm85.overlay | 44 +++++++++++++++++ 3 files changed, 99 insertions(+) create mode 100644 tests/subsys/fs/ext2/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay create mode 100644 tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf create mode 100644 tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay diff --git a/tests/subsys/fs/ext2/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/subsys/fs/ext2/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..efe22b15bf9a5 --- /dev/null +++ b/tests/subsys/fs/ext2/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + + partition { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size_cells = <1>; + + slot1_partition: partition@0 { + reg = <0x00000000 0x800000>; + }; + }; + }; +}; diff --git a/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf b/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf new file mode 100644 index 0000000000000..0238ff6b3c6af --- /dev/null +++ b/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.conf @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_DISK_DRIVER_RAM=n +CONFIG_DISK_DRIVER_FLASH=n +CONFIG_FS_FATFS_HAS_RTC=n diff --git a/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay b/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay new file mode 100644 index 0000000000000..b64255fd34d57 --- /dev/null +++ b/tests/subsys/fs/fat_fs_api/boards/ek_ra8d2_r7ka8d2kflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; From 5948c119ff00607b33b1d6a2a8a9c82364f71bfe Mon Sep 17 00:00:00 2001 From: Khoa Tran Date: Wed, 3 Sep 2025 16:12:20 +0700 Subject: [PATCH 25/25] tests: subsys: pm: Add support for power_mgmt_soc on ek_ra8d2 Add support for test app power_mgmt_soc on Renesas ek_ra8d2 Signed-off-by: Khoa Tran --- tests/subsys/pm/power_mgmt_soc/testcase.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml index 147b4f813e42c..75ce4f7592e3a 100644 --- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml +++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml @@ -26,6 +26,7 @@ tests: - mck_ra8t1 - ek_ra8p1/r7ka8p1kflcac/cm85 - mck_ra8t2/r7ka8t2lfecac/cm85 + - ek_ra8d2/r7ka8d2kflcac/cm85 tags: pm integration_platforms: - mec15xxevb_assy6853