diff --git a/arch/riscv/custom/CMakeLists.txt b/arch/riscv/custom/CMakeLists.txt index fab46a8142a6c..ee166d7615a43 100644 --- a/arch/riscv/custom/CMakeLists.txt +++ b/arch/riscv/custom/CMakeLists.txt @@ -6,4 +6,5 @@ add_subdirectory_ifdef(CONFIG_DT_HAS_OPENHWGROUP_CVA6_ENABLED openhwgroup/cva6) add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei) add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy) add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy) +add_subdirectory_ifdef(CONFIG_DT_HAS_SPINALHDL_VEXRISCV_ENABLED vexriscv) add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead) diff --git a/arch/riscv/custom/Kconfig b/arch/riscv/custom/Kconfig index e14abc77280d4..24b2b820fa088 100644 --- a/arch/riscv/custom/Kconfig +++ b/arch/riscv/custom/Kconfig @@ -7,6 +7,12 @@ rsource "andes/Kconfig" endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED +if DT_HAS_SPINALHDL_VEXRISCV_ENABLED + +rsource "vexriscv/Kconfig" + +endif # DT_HAS_SPINALHDL_VEXRISCV_ENABLED + if DT_HAS_XUANTIE_E907_ENABLED rsource "thead/Kconfig" diff --git a/arch/riscv/custom/vexriscv/CMakeLists.txt b/arch/riscv/custom/vexriscv/CMakeLists.txt new file mode 100644 index 0000000000000..6e708a5df562c --- /dev/null +++ b/arch/riscv/custom/vexriscv/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_VEXRISCV_CACHE cache_vexriscv.c) diff --git a/arch/riscv/custom/vexriscv/Kconfig b/arch/riscv/custom/vexriscv/Kconfig new file mode 100644 index 0000000000000..18caf790dcd54 --- /dev/null +++ b/arch/riscv/custom/vexriscv/Kconfig @@ -0,0 +1,9 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config RISCV_CUSTOM_CSR_VEXRISCV_CACHE + bool + default y + depends on ARCH_CACHE + help + This option enables cache support for VexRiscv family of CPUs. diff --git a/arch/riscv/custom/vexriscv/cache_vexriscv.c b/arch/riscv/custom/vexriscv/cache_vexriscv.c new file mode 100644 index 0000000000000..20b4e0911f876 --- /dev/null +++ b/arch/riscv/custom/vexriscv/cache_vexriscv.c @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef CONFIG_DCACHE +void arch_dcache_enable(void) +{ + /* Nothing */ +} + +void arch_dcache_disable(void) +{ + /* Nothing */ +} + +int arch_dcache_invd_all(void) +{ + /* Invalidate whole data cache instruction: 0x500F + * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin + */ + __asm__ volatile(".insn 0x500F\n"); + + return 0; +} + +int arch_dcache_invd_range(void *addr, size_t size) +{ + /* Invalidate cache line instruction: 0x500f | (rs1 << 15) + * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin + */ + __asm__ volatile( + "mv a0, %1\n" + "j 2f\n" + "3:\n" + ".insn 0x5500F\n" /* 0x500f | (a0 << 15) */ + "add a0, a0, %0\n" + "2:\n" + "bltu a0, %2, 3b\n" + : : "r"(CONFIG_DCACHE_LINE_SIZE), + "r"((unsigned int)(addr) & ~((CONFIG_DCACHE_LINE_SIZE) - 1UL)), + "r"((unsigned int)(addr) + (size)) + : "a0"); + + return 0; +} + + +int arch_dcache_flush_all(void) +{ + /* VexRiscv cache is write-through */ + return 0; +} + +int arch_dcache_flush_range(void *addr __unused, size_t size __unused) +{ + return 0; +} + +int arch_dcache_flush_and_invd_all(void) +{ + return arch_dcache_invd_all(); +} + +int arch_dcache_flush_and_invd_range(void *addr, size_t size) +{ + return arch_dcache_invd_range(addr, size); +} +#endif /* CONFIG_DCACHE */ + +#ifdef CONFIG_ICACHE +void arch_icache_enable(void) +{ + /* Nothing */ +} + +void arch_icache_disable(void) +{ + /* Nothing */ +} + +int arch_icache_flush_all(void) +{ + __asm__ volatile("fence.i\n"); + + return 0; +} + +int arch_icache_invd_all(void) +{ + return arch_icache_flush_all(); +} + +int arch_icache_invd_range(void *addr_in __unused, size_t size __unused) +{ + return arch_icache_flush_all(); +} + +int arch_icache_flush_and_invd_all(void) +{ + return arch_icache_flush_all(); +} + +int arch_icache_flush_range(void *addr __unused, size_t size __unused) +{ + return arch_icache_flush_all(); +} + +int arch_icache_flush_and_invd_range(void *addr __unused, size_t size __unused) +{ + return arch_icache_flush_all(); +} +#endif /* CONFIG_ICACHE */ + +void arch_cache_init(void) +{ + /* Nothing */ +} diff --git a/dts/bindings/cpu/litex,vexriscv-standard.yaml b/dts/bindings/cpu/litex,vexriscv-standard.yaml index 86de7c7a9c008..420e927f473c9 100644 --- a/dts/bindings/cpu/litex,vexriscv-standard.yaml +++ b/dts/bindings/cpu/litex,vexriscv-standard.yaml @@ -6,4 +6,10 @@ description: VexRiscv core with the standard configuration as used by LiteX compatible: "litex,vexriscv-standard" -include: riscv,cpus.yaml +include: spinalhdl,vexriscv.yaml + +properties: + i-cache-line-size: + default: 32 + d-cache-line-size: + default: 32 diff --git a/dts/bindings/cpu/spinalhdl,vexriscv.yaml b/dts/bindings/cpu/spinalhdl,vexriscv.yaml new file mode 100644 index 0000000000000..62901fc03def2 --- /dev/null +++ b/dts/bindings/cpu/spinalhdl,vexriscv.yaml @@ -0,0 +1,8 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +description: VexRiscv core + +compatible: "spinalhdl,vexriscv" + +include: riscv,cpus.yaml diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index f9b987895f8c0..7401f71b2c6c3 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -657,6 +657,7 @@ solomon Solomon Systech Limited sony Sony Corporation spansion Spansion Inc. sparkfun SparkFun Electronics +spinalhdl SpinalHDL sprd Spreadtrum Communications Inc. sqn Sequans Communications sst Silicon Storage Technology, Inc. diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index 33f7bd03fc286..78a561ba77309 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -22,7 +22,7 @@ cpu0: cpu@0 { clock-frequency = <100000000>; - compatible = "litex,vexriscv-standard", "riscv"; + compatible = "litex,vexriscv-standard", "spinalhdl,vexriscv", "riscv"; device_type = "cpu"; reg = <0>; riscv,isa = "rv32im_zicsr_zifencei"; diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig index 6a684f5c4ca9a..5543d09bbe724 100644 --- a/soc/litex/litex_vexriscv/Kconfig +++ b/soc/litex/litex_vexriscv/Kconfig @@ -8,6 +8,9 @@ config SOC_LITEX_VEXRISCV select RISCV_ISA_EXT_M select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI + # There are varriants of the Vexriscv without cache, be able to set it + select CPU_HAS_ICACHE if $(dt_node_int_prop_int,/cpus/cpu@0,i-cache-line-size) > 0 + select CPU_HAS_DCACHE if $(dt_node_int_prop_int,/cpus/cpu@0,d-cache-line-size) > 0 imply XIP if SOC_LITEX_VEXRISCV