diff --git a/boards/renesas/ek_ra8m2/Kconfig.ek_ra8m2 b/boards/renesas/ek_ra8m2/Kconfig.ek_ra8m2 new file mode 100644 index 0000000000000..9208a1dd6a41a --- /dev/null +++ b/boards/renesas/ek_ra8m2/Kconfig.ek_ra8m2 @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA8M2 + select SOC_R7KA8M2JFLCAC_CM85 if BOARD_EK_RA8M2_R7KA8M2JFLCAC_CM85 + select SOC_R7KA8M2JFLCAC_CM33 if BOARD_EK_RA8M2_R7KA8M2JFLCAC_CM33 diff --git a/boards/renesas/ek_ra8m2/board.cmake b/boards/renesas/ek_ra8m2/board.cmake new file mode 100644 index 0000000000000..a9194849ebeec --- /dev/null +++ b/boards/renesas/ek_ra8m2/board.cmake @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_R7KA8M2JFLCAC_CM85) + board_runner_args(jlink "--device=R7KA8M2JF_CPU0" "--reset-after-load") +endif() + +board_runner_args(pyocd "--target=R7KA8M2JF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8m2/board.yml b/boards/renesas/ek_ra8m2/board.yml new file mode 100644 index 0000000000000..7573d24fc291f --- /dev/null +++ b/boards/renesas/ek_ra8m2/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_ra8m2 + full_name: RA8M2 Evaluation Kit + vendor: renesas + socs: + - name: r7ka8m2jflcac diff --git a/boards/renesas/ek_ra8m2/doc/ek_ra8m2.webp b/boards/renesas/ek_ra8m2/doc/ek_ra8m2.webp new file mode 100644 index 0000000000000..6cf238dbaaf3c Binary files /dev/null and b/boards/renesas/ek_ra8m2/doc/ek_ra8m2.webp differ diff --git a/boards/renesas/ek_ra8m2/doc/index.rst b/boards/renesas/ek_ra8m2/doc/index.rst new file mode 100644 index 0000000000000..9a1a938d4ff1d --- /dev/null +++ b/boards/renesas/ek_ra8m2/doc/index.rst @@ -0,0 +1,214 @@ +.. zephyr:board:: ek_ra8m2 + +Overview +******** + +The EK-RA8M2 is an Evaluation Kit for Renesas RA8M2 MCU Group which integrates multiple series of software-compatible +Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient +platform-based product development. + +The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® +Cortex®-M33 core running up to 250 MHz with the following features: + +- Up to 1 MB MRAM +- 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM) +- Octal Serial Peripheral Interface (OSPI) +- Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface +- Analog peripherals +- Security and safety features + +**MCU Native Pin Access** + +- 1 GHz Arm® Cortex®-M85 core and 250 MHz Arm® Cortex®-M33 core based RA8M2 MCU 289 pins, BGA package +- 1 MB MRAM, 2 MB SRAM with ECC +- Native pin access through 5 x 20-pin, and 3 x 40-pin headers (not populated) +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA8M2 MCU oscillator and sub-clock oscillator crystals, providing precision + 24.000 MHz and 32,768 Hz reference clocks. Additional low-precision clocks are available internal to + the RA8M2 MCU +- RTC Backup battery connector J36 (not populated) + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (USB-C connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD and JTAG) + - Debug in (ETM, SWD, SWO, and JTAG) + - Debug out (SWD, SWO, and JTAG) + +- User LEDs, Status LEDs and Switches + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User Switches + - One Reset Switch + +- Five most popular ecosystems expansions + + - Two Seeed Grove® system (I2C/I3C/Analog) connectors (not populated) + - SparkFun® Qwiic® connector (not populated) + - Two Digilent PmodTM (SPI, UART, and I2C) connectors + - Arduino™ (UNO R3) connector + - MikroElektronikaTM mikroBUS connector (not populated) + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RGMII interface) +- USB High Speed Host and Device (USB-C connector) +- 64 MB (512 Mb) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M2 board) +- RS485 / MODBUS (3.5mm pitch 4-pin terminal block) +- CAN FD (3-pin header) +- Configuration Switches + +Hardware +******** + +Detailed hardware features can be found at: + +- RA8M2 MCU: `RA8M2 Group User's Manual Hardware`_ +- EK-RA8M2 board: `EK-RA8M2 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +Applications for the ``ek_ra8m2`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Here is an example for the :zephyr:code-sample:`hello_world` application on CM85 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ek_ra8m2/r7ka8m2jflcac/cm85 + :goals: flash + +Open a serial terminal, reset the board (press the reset switch SW3), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx ***** + Hello World! ek_ra8m2/r7ka8m2jflcac/cm85 + +Flashing +======== + +Program can be flashed to EK-RA8M2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/ + +To flash the program to board + +1. Connect to J-Link OB via USB port to host PC + +2. Make sure J-Link OB jumper is in default configuration as described in `EK-RA8M2 - User's Manual`_ + +3. Execute west command + + .. code-block:: console + + west flash -r jlink + +MCUboot bootloader +================== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ek_ra8m2/r7ka8m2jflcac/cm85 + :goals: build flash + :west-args: --sysbuild + :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y + +By default, Sysbuild creates MCUboot and user application images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + | └── zephyr + │ ├── zephyr.elf + │ ├── zephyr.hex + │ ├── zephyr.bin + │ ├── zephyr.signed.bin + │ └── zephyr.signed.hex + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ ├── zephyr.hex + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option, MCUboot will be rebuilt and reflashed + every time the pristine build is used. + +To only flash the user application in the subsequent builds, Use: + +.. code-block:: console + + $ west flash --domain hello_world + +For more information about the system build please read the :ref:`sysbuild` documentation. + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting MCUboot v2.2.0-171-g8513be710e5e *** + *** Using Zephyr OS build v4.2.0-6183-gdd720e2f0dc5 *** + I: Starting bootloader + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Boot source: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Image index: 0, Swap type: none + I: Bootloader chainload address offset: 0x10000 + I: Image version: v0.0.0 + I: Jumping to the first image slot + *** Booting Zephyr OS build v4.2.0-6183-gdd720e2f0dc5 *** + Hello World! ek_ra8m2/r7ka8m2jflcac/cm85 + +References +********** +- `EK-RA8M2 Website`_ +- `RA8M2 MCU group Website`_ + +.. _EK-RA8M2 Website: + https://www.renesas.com/en/design-resources/boards-kits/ek-ra8m2 + +.. _RA8M2 MCU group Website: + https://www.renesas.com/en/products/ra8m2 + +.. _EK-RA8M2 - User's Manual: + https://www.renesas.com/en/document/mat/ek-ra8m2-v1-users-manual + +.. _RA8M2 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/ra8m2-group-users-manual-hardware diff --git a/boards/renesas/ek_ra8m2/ek_ra8m2-pinctrl.dtsi b/boards/renesas/ek_ra8m2/ek_ra8m2-pinctrl.dtsi new file mode 100644 index 0000000000000..155183cb49fb1 --- /dev/null +++ b/boards/renesas/ek_ra8m2/ek_ra8m2-pinctrl.dtsi @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* TX8 RX8 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + sci7_default: sci7_default { + group1 { + /* TX7 RX7 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISOB MOSIB SSLB0 */ + psels = , + , + ; + drive-strength = "high"; + }; + + group2 { + /* RSPCKB */ + psels = ; + drive-strength = "highspeed-high"; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A */ + psels = ; + }; + + group2 { + /* GTIOC1B */ + psels = ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = , + ; + drive-strength = "medium"; + }; + }; + + canfd1_default: canfd1_default { + group1 { + /* CRX1 CTX1 */ + psels = , + ; + drive-strength = "low"; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* VBUS */ + drive-strength = "high"; + }; + }; + + usbfs_default: usbfs_default { + group1 { + psels = , /* USB_DM */ + , /* USB_DP */ + ; /* VBUS */ + drive-strength = "high"; + }; + }; +}; diff --git a/boards/renesas/ek_ra8m2/ek_ra8m2.dtsi b/boards/renesas/ek_ra8m2/ek_ra8m2.dtsi new file mode 100644 index 0000000000000..df59880e79a98 --- /dev/null +++ b/boards/renesas/ek_ra8m2/ek_ra8m2.dtsi @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "ek_ra8m2-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport3 3 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioporta 7 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + status = "disabled"; + }; + + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + status = "disabled"; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 4 0>, /* AN */ + <1 0 &ioport1 11 0>, /* RST */ + <2 0 &ioport4 14 0>, /* CS */ + <3 0 &ioport4 15 0>, /* SCK */ + <4 0 &ioport7 9 0>, /* MISO */ + <5 0 &ioport7 8 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport8 10 0>, /* PWM */ + <7 0 &ioport0 10 0>, /* INT */ + <8 0 &ioportc 4 0>, /* RX */ + <9 0 &ioportc 3 0>, /* TX */ + <10 0 &ioport4 0 0>, /* SCL */ + <11 0 &ioport4 1 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + transceiver0: can-phy0 { + compatible = "microchip,mcp2562fd", "can-transceiver-gpio"; + standby-gpios = <&ioport9 7 GPIO_ACTIVE_LOW>; + max-bitrate = <5000000>; + #phy-cells = <0>; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; + + pllp: pllp { + status = "okay"; + }; + + pllq: pllq { + status = "okay"; + }; + + pllr: pllr { + status = "okay"; + }; +}; + +&pll2 { + status = "okay"; + + pll2p { + status = "okay"; + }; + + pll2q { + status = "okay"; + }; + + pll2r { + status = "okay"; + }; +}; + +&sciclk { + status = "okay"; +}; + +&canfdclk { + status = "okay"; +}; + +&gptclk { + status = "okay"; +}; + +&uclk { + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport7 { + status = "okay"; +}; + +&ioport8 { + status = "okay"; +}; + +&ioport9 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&ioportc { + status = "okay"; +}; + +&ioportd { + status = "okay"; +}; + +&usbfs { + pinctrl-0 = <&usbfs_default>; + pinctrl-names = "default"; + maximum-speed = "full-speed"; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; diff --git a/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.dts b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.dts new file mode 100644 index 0000000000000..7a099ab8dd402 --- /dev/null +++ b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.dts @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ek_ra8m2.dtsi" + +/ { + model = "Renesas EK-RA8M2"; + compatible = "renesas,ra8m2", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_mram_cm85; + zephyr,flash-controller = &mram_ctrl; + zephyr,code-partition = &slot0_partition; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + zephyr,canbus = &canfd1; + zephyr,crc = &crc; + }; + + aliases { + led0 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdt0; + }; +}; + +&button0 { + status ="okay"; +}; + +&button1 { + status ="okay"; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart7: uart { + current-speed = <115200>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; +}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + interrupts = <12 1>, <13 1>, <14 1>, <15 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; +}; + +&canfd_global { + interrupts = <16 1>, <17 1>; + interrupt-names = "rxf", "glerr"; + status = "okay"; + + canfd1 { + pinctrl-0 = <&canfd1_default>; + pinctrl-names = "default"; + interrupts = <18 1>, <19 1>, <20 11>; + interrupt-names = "err", "tx", "rx"; + phys = <&transceiver0>; + rx-max-filters = <16>; + status = "okay"; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + interrupts = <23 1>, <24 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq12 { + interrupts = <25 1>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <26 1>; + status = "okay"; +}; + +&ulpt0 { + interrupts = <27 1>; + interrupt-names = "ulpti"; + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&ulpt1 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&crc { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + interrupts = <28 1>; + interrupt-names = "usbhs-ir"; + status = "okay"; + + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&code_mram_cm85 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(472)>; + }; + + slot1_partition: partition@86000 { + label = "image-1"; + reg = <0x86000 DT_SIZE_K(472)>; + }; + + storage_partition: partition@fc000 { + label = "storage"; + reg = <0xfc000 DT_SIZE_K(16)>; + }; + }; +}; + +mikrobus_serial: &uart7 {}; + +mikrobus_spi: &spi1 {}; diff --git a/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.yaml b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.yaml new file mode 100644 index 0000000000000..13f3d15b53e9c --- /dev/null +++ b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra8m2/r7ka8m2jflcac/cm85 +name: Renesas EK-RA8M2 +type: mcu +arch: arm +ram: 1664 +flash: 1024 +toolchain: + - zephyr +supported: + - gpio + - uart +vendor: renesas diff --git a/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85_defconfig b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85_defconfig new file mode 100644 index 0000000000000..2f9e7c584905b --- /dev/null +++ b/boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/dts/arm/renesas/ra/ra8/r7ka8m2jflcac.dtsi b/dts/arm/renesas/ra/ra8/r7ka8m2jflcac.dtsi new file mode 100644 index 0000000000000..d351dc993f618 --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8m2jflcac.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + mram-controller@4013c000 { + code_mram_cm85: mram@2000000 { + compatible = "renesas,ra-nv-mram"; + reg = <0x2000000 DT_SIZE_M(1)>; + write-block-size = <1>; + erase-block-size = <32>; + }; + }; + + sram0: memory@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(1664)>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra8/r7ka8m2jflcac_cm85.dtsi b/dts/arm/renesas/ra/ra8/r7ka8m2jflcac_cm85.dtsi new file mode 100644 index 0000000000000..089bed507f32d --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8m2jflcac_cm85.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/delete-node/ &cpu1; diff --git a/dts/arm/renesas/ra/ra8/r7ka8m2xf.dtsi b/dts/arm/renesas/ra/ra8/r7ka8m2xf.dtsi new file mode 100644 index 0000000000000..9c956d0d5c700 --- /dev/null +++ b/dts/arm/renesas/ra/ra8/r7ka8m2xf.dtsi @@ -0,0 +1,805 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + clocks = <&xtal>; + div = <3>; + mul = <250 0>; + status = "disabled"; + + pllp: pllp { + compatible = "renesas,ra-cgc-pll-out"; + div = <2>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pllq: pllq { + compatible = "renesas,ra-cgc-pll-out"; + div = <6>; + freq = <333333333>; + status = "disabled"; + #clock-cells = <0>; + }; + + pllr: pllr { + compatible = "renesas,ra-cgc-pll-out"; + div = <5>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + }; + + pll2: pll2 { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL2 */ + clocks = <&xtal>; + div = <3>; + mul = <300 0>; + status = "disabled"; + + pll2p: pll2p { + compatible = "renesas,ra-cgc-pll-out"; + div = <4>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2q: pll2q { + compatible = "renesas,ra-cgc-pll-out"; + div = <3>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + + pll2r: pll2r { + compatible = "renesas,ra-cgc-pll-out"; + div = <5>; + freq = ; + status = "disabled"; + #clock-cells = <0>; + }; + }; + + pclkblock: pclkblock@40203000 { + compatible = "renesas,ra-cgc-pclk-block"; + reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, + <0x4020300c 4>, <0x40203010 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", + "MSTPD", "MSTPE"; + #clock-cells = <0>; + clocks = <&pllp>; + status = "okay"; + + cpuclk0: cpuclk0 { + compatible = "renesas,ra-cgc-pclk"; + clock-frequency = ; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + cpuclk1: cpuclk1 { + compatible = "renesas,ra-cgc-pclk"; + clock-frequency = ; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + mriclk: mriclk { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + mrpclk: mrpclk { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + div = <16>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + pclke: pclke { + compatible = "renesas,ra-cgc-pclk"; + div = <4>; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + div = <8>; + #clock-cells = <2>; + status = "okay"; + + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk-out-div = <2>; + sdclk = <1>; + #clock-cells = <0>; + status = "okay"; + }; + }; + + bclka: bclka { + compatible = "renesas,ra-cgc-pclk"; + div = <6>; + clocks = <&pll2q>; + #clock-cells = <2>; + status = "disabled"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + div = <1>; + clocks = <&hoco>; + #clock-cells = <2>; + status = "disabled"; + }; + + sciclk: sciclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + spiclk: spiclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllq>; + div = <1>; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdclk: canfdclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <6>; + #clock-cells = <2>; + status = "disabled"; + }; + + gptclk: gptclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2p>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + i3cclk: i3cclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2q>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + clocks = <&pll2r>; + div = <10>; + status = "disabled"; + }; + + usb60clk: u60clk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <8>; + #clock-cells = <2>; + status = "disabled"; + }; + + octaspiclk: octaspiclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllq>; + div = <1>; + #clock-cells = <2>; + status = "disabled"; + }; + + adcclk: adcclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2r>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + eswclk: eswclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllp>; + div = <4>; + #clock-cells = <2>; + status = "disabled"; + }; + + eswphyclk: eswphyclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pllp>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + ethphyclk: ethphyclk { + compatible = "renesas,ra-cgc-pclk"; + clocks = <&pll2q>; + div = <32>; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; + +&ioport0 { + port-irqs = <&port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14 + &port_irq15 &port_irq16 &port_irq27 + &port_irq28 &port_irq29>; + port-irq-names = "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq15", + "port-irq16", + "port-irq27", + "port-irq28", + "port-irq29"; + port-irq6-pins = <0>; + port-irq7-pins = <1>; + port-irq8-pins = <2>; + port-irq9-pins = <4>; + port-irq10-pins = <5>; + port-irq11-pins = <6>; + port-irq12-pins = <8>; + port-irq13-pins = <9 15>; + port-irq14-pins = <10 13>; + port-irq15-pins = <12>; + port-irq16-pins = <11>; + port-irq27-pins = <14>; + port-irq28-pins = <7>; + port-irq29-pins = <3>; +}; + +&ioport1 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq16 &port_irq17 &port_irq19 + &port_irq20 &port_irq23 &port_irq24 + &port_irq27 &port_irq28 &port_irq30 + &port_irq31>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq16", + "port-irq17", + "port-irq19", + "port-irq20", + "port-irq23", + "port-irq24", + "port-irq27", + "port-irq28", + "port-irq30", + "port-irq31"; + port-irq0-pins = <5>; + port-irq1-pins = <1 4>; + port-irq2-pins = <0>; + port-irq16-pins = <3 6>; + port-irq17-pins = <2>; + port-irq19-pins = <11>; + port-irq20-pins = <10>; + port-irq23-pins = <9>; + port-irq24-pins = <8>; + port-irq27-pins = <12>; + port-irq28-pins = <13>; + port-irq30-pins = <14>; + port-irq31-pins = <7 15>; +}; + +&ioport2 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq4 &port_irq20 + &port_irq21 &port_irq23 &port_irq24 + &port_irq25 &port_irq26>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq4", + "port-irq20", + "port-irq21", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26"; + port-irq0-pins = <6>; + port-irq1-pins = <5>; + port-irq2-pins = <3 13>; + port-irq3-pins = <2 8 12>; + port-irq4-pins = <1>; + port-irq20-pins = <15>; + port-irq21-pins = <14>; + port-irq23-pins = <11>; + port-irq24-pins = <10>; + port-irq25-pins = <7 9>; + port-irq26-pins = <4>; +}; + +&ioport3 { + port-irqs = <&port_irq4 &port_irq5 &port_irq6 + &port_irq8 &port_irq9 &port_irq22 + &port_irq23 &port_irq24 &port_irq25 + &port_irq26 &port_irq27 &port_irq28 + &port_irq29>; + port-irq-names = "port-irq4", + "port-irq5", + "port-irq6", + "port-irq8", + "port-irq9", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29"; + port-irq4-pins = <0>; + port-irq5-pins = <2>; + port-irq6-pins = <1>; + port-irq8-pins = <5>; + port-irq9-pins = <4>; + port-irq22-pins = <12>; + port-irq23-pins = <11>; + port-irq24-pins = <10>; + port-irq25-pins = <9>; + port-irq26-pins = <8>; + port-irq27-pins = <7 13>; + port-irq28-pins = <6 14>; + port-irq29-pins = <3 15>; +}; + +&ioport4 { + port-irqs = <&port_irq0 &port_irq4 &port_irq5 + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15 + &port_irq18 &port_irq20 &port_irq22 + &port_irq30 &port_irq31>; + port-irq-names = "port-irq0", + "port-irq4", + "port-irq5", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq14", + "port-irq15", + "port-irq18", + "port-irq20", + "port-irq22", + "port-irq30", + "port-irq31"; + port-irq0-pins = <0>; + port-irq4-pins = <2 11>; + port-irq5-pins = <1 10>; + port-irq6-pins = <9>; + port-irq7-pins = <8>; + port-irq8-pins = <15>; + port-irq9-pins = <14>; + port-irq14-pins = <3>; + port-irq15-pins = <4>; + port-irq18-pins = <13>; + port-irq20-pins = <12>; + port-irq22-pins = <7>; + port-irq30-pins = <5>; + port-irq31-pins = <6>; +}; + +&ioport5 { + port-irqs = <&port_irq1 &port_irq2 &port_irq3 + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq10 &port_irq12 + &port_irq13 &port_irq14 &port_irq15 + &port_irq24 &port_irq25 &port_irq26 + &port_irq31>; + port-irq-names = "port-irq1", + "port-irq2", + "port-irq3", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq15", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq31"; + port-irq1-pins = <8>; + port-irq2-pins = <9>; + port-irq3-pins = <10>; + port-irq6-pins = <3>; + port-irq7-pins = <4>; + port-irq8-pins = <5>; + port-irq9-pins = <6>; + port-irq10-pins = <7>; + port-irq12-pins = <15>; + port-irq13-pins = <14>; + port-irq14-pins = <12>; + port-irq15-pins = <11>; + port-irq24-pins = <0>; + port-irq25-pins = <1>; + port-irq26-pins = <2>; + port-irq31-pins = <13>; +}; + +&ioport6 { + port-irqs = <&port_irq7 &port_irq16 &port_irq17 + &port_irq18 &port_irq19 &port_irq20 + &port_irq22 &port_irq23 &port_irq24 + &port_irq25 &port_irq26 &port_irq27 + &port_irq28 &port_irq29 &port_irq30>; + port-irq-names = "port-irq7", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29", + "port-irq30"; + port-irq7-pins = <15>; + port-irq16-pins = <10>; + port-irq17-pins = <11>; + port-irq18-pins = <12>; + port-irq19-pins = <13>; + port-irq20-pins = <14>; + port-irq22-pins = <8>; + port-irq23-pins = <7>; + port-irq24-pins = <6>; + port-irq25-pins = <5>; + port-irq26-pins = <4>; + port-irq27-pins = <3>; + port-irq28-pins = <2>; + port-irq29-pins = <1 9>; + port-irq30-pins = <0>; +}; + +&ioport7 { + port-irqs = <&port_irq2 &port_irq3 &port_irq7 + &port_irq8 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14 + &port_irq16 &port_irq17 &port_irq18 + &port_irq19 &port_irq26>; + port-irq-names = "port-irq2", + "port-irq3", + "port-irq7", + "port-irq8", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq26"; + port-irq2-pins = <12>; + port-irq3-pins = <11>; + port-irq7-pins = <6>; + port-irq8-pins = <7>; + port-irq10-pins = <9>; + port-irq11-pins = <8>; + port-irq12-pins = <15>; + port-irq13-pins = <14>; + port-irq14-pins = <13>; + port-irq16-pins = <0>; + port-irq17-pins = <1 10>; + port-irq18-pins = <2>; + port-irq19-pins = <3 5>; + port-irq26-pins = <4>; +}; + +&ioport8 { + port-irqs = <&port_irq0 &port_irq11 &port_irq12 + &port_irq14 &port_irq15 &port_irq16 + &port_irq18 &port_irq19 &port_irq20 + &port_irq21 &port_irq22 &port_irq23 + &port_irq30>; + port-irq-names = "port-irq0", + "port-irq11", + "port-irq12", + "port-irq14", + "port-irq15", + "port-irq16", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq23", + "port-irq30"; + port-irq0-pins = <6>; + port-irq11-pins = <0 7>; + port-irq12-pins = <1>; + port-irq14-pins = <4>; + port-irq15-pins = <8 13 15>; + port-irq16-pins = <14>; + port-irq18-pins = <2>; + port-irq19-pins = <3>; + port-irq20-pins = <9>; + port-irq21-pins = <10>; + port-irq22-pins = <11>; + port-irq23-pins = <12>; + port-irq30-pins = <5>; +}; + +&ioport9 { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq5 &port_irq6 + &port_irq7 &port_irq8 &port_irq9 + &port_irq10 &port_irq11 &port_irq21 + &port_irq30 &port_irq31>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq5", + "port-irq6", + "port-irq7", + "port-irq8", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq21", + "port-irq30", + "port-irq31"; + port-irq0-pins = <2>; + port-irq1-pins = <3>; + port-irq2-pins = <4>; + port-irq3-pins = <13>; + port-irq5-pins = <12>; + port-irq6-pins = <11>; + port-irq7-pins = <10>; + port-irq8-pins = <5 15>; + port-irq9-pins = <6 14>; + port-irq10-pins = <7>; + port-irq11-pins = <8>; + port-irq21-pins = <9>; + port-irq30-pins = <0>; + port-irq31-pins = <1>; +}; + +&ioporta { + port-irqs = <&port_irq4 &port_irq5 &port_irq6 + &port_irq10 &port_irq11 &port_irq12 + &port_irq13 &port_irq14 &port_irq16 + &port_irq17 &port_irq18 &port_irq19 + &port_irq20 &port_irq21 &port_irq22 + &port_irq31>; + port-irq-names = "port-irq4", + "port-irq5", + "port-irq6", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq14", + "port-irq16", + "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq31"; + port-irq4-pins = <10>; + port-irq5-pins = <9>; + port-irq6-pins = <8>; + port-irq10-pins = <11>; + port-irq11-pins = <12>; + port-irq12-pins = <13>; + port-irq13-pins = <14>; + port-irq14-pins = <15>; + port-irq16-pins = <7>; + port-irq17-pins = <6>; + port-irq18-pins = <5>; + port-irq19-pins = <4>; + port-irq20-pins = <3>; + port-irq21-pins = <1>; + port-irq22-pins = <0>; + port-irq31-pins = <2>; +}; + +&ioportb { + port-irqs = <&port_irq0 &port_irq1 &port_irq9 + &port_irq10 &port_irq11 &port_irq12 + &port_irq13 &port_irq15>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq9", + "port-irq10", + "port-irq11", + "port-irq12", + "port-irq13", + "port-irq15"; + port-irq0-pins = <6>; + port-irq1-pins = <7>; + port-irq9-pins = <4>; + port-irq10-pins = <0>; + port-irq11-pins = <2>; + port-irq12-pins = <1>; + port-irq13-pins = <3>; + port-irq15-pins = <5>; +}; + +&ioportc { + port-irqs = <&port_irq0 &port_irq1 &port_irq2 + &port_irq3 &port_irq4 &port_irq5 + &port_irq21 &port_irq22 &port_irq23 + &port_irq24 &port_irq25 &port_irq26 + &port_irq27 &port_irq28 &port_irq29 + &port_irq30>; + port-irq-names = "port-irq0", + "port-irq1", + "port-irq2", + "port-irq3", + "port-irq4", + "port-irq5", + "port-irq21", + "port-irq22", + "port-irq23", + "port-irq24", + "port-irq25", + "port-irq26", + "port-irq27", + "port-irq28", + "port-irq29", + "port-irq30"; + port-irq0-pins = <14>; + port-irq1-pins = <13>; + port-irq2-pins = <12>; + port-irq3-pins = <11>; + port-irq4-pins = <10>; + port-irq5-pins = <9>; + port-irq21-pins = <7>; + port-irq22-pins = <6>; + port-irq23-pins = <5>; + port-irq24-pins = <4>; + port-irq25-pins = <3>; + port-irq26-pins = <2>; + port-irq27-pins = <1>; + port-irq28-pins = <0>; + port-irq29-pins = <8>; + port-irq30-pins = <15>; +}; + +&ioportd { + port-irqs = <&port_irq17 &port_irq18 &port_irq19 + &port_irq20 &port_irq21 &port_irq22 + &port_irq23>; + port-irq-names = "port-irq17", + "port-irq18", + "port-irq19", + "port-irq20", + "port-irq21", + "port-irq22", + "port-irq23"; + port-irq17-pins = <7>; + port-irq18-pins = <6>; + port-irq19-pins = <5>; + port-irq20-pins = <4>; + port-irq21-pins = <2 3>; + port-irq22-pins = <1>; + port-irq23-pins = <0>; +}; diff --git a/samples/boards/renesas/comparator/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/samples/boards/renesas/comparator/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..30a65dd86b1a7 --- /dev/null +++ b/samples/boards/renesas/comparator/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sample-comp = &acmphs0; + }; +}; + +&pinctrl { + acmphs0_ivcmp3: acmphs0_ivcmp3 { + group1 { + /* CH0 IVCMP3 */ + psels = ; + renesas,analog-enable; + }; + }; +}; + +&acmphs_global { + status = "okay"; + + acmphs0 { + pinctrl-0 = <&acmphs0_ivcmp3>; + pinctrl-names = "default"; + interrupts = <90 12>; + interrupt-names = "hs"; + reference-input-source = "ivref2"; + compare-input-source = "ivcmp3"; + noise-filter = <1>; + status = "okay"; + }; +}; diff --git a/samples/drivers/counter/alarm/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/samples/drivers/counter/alarm/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..74b2108738f53 --- /dev/null +++ b/samples/drivers/counter/alarm/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <94 1>, <95 1>; + interrupt-names = "agti", "agtcmai"; + renesas,prescaler = <4>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; diff --git a/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..7f81a35b58584 --- /dev/null +++ b/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 diff --git a/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..ed6f6035a670c --- /dev/null +++ b/samples/drivers/i2s/output/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-tx = &i2s1; + }; +}; + +&pinctrl { + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + }; + }; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <93 1>, <92 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(2822400) PWM_POLARITY_NORMAL>; + }; +}; diff --git a/samples/modules/lvgl/demos/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/samples/modules/lvgl/demos/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay new file mode 100644 index 0000000000000..5207a4a73fd69 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&code_mram_cm85 { + reg = <0x2000000 DT_SIZE_K(950)>; +}; + +&code_mram_cm33 { + reg = <0x20ed800 DT_SIZE_K(74)>; +}; diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml index 1faa12e1593d6..cad7f82724899 100644 --- a/samples/modules/lvgl/demos/sample.yaml +++ b/samples/modules/lvgl/demos/sample.yaml @@ -87,7 +87,7 @@ tests: fixture: fixture_display extra_args: - SHIELD=rtklcdpar1s00001be - - DTC_OVERLAY_FILE=rtklcdpar1s00001be.overlay + - EXTRA_DTC_OVERLAY_FILE=rtklcdpar1s00001be.overlay extra_configs: - CONFIG_LV_DEMO_MUSIC_LANDSCAPE=y tags: diff --git a/samples/subsys/fs/fs_sample/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/samples/subsys/fs/fs_sample/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..377247abb30ad --- /dev/null +++ b/samples/subsys/fs/fs_sample/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/soc/renesas/ra/ra8m2/CMakeLists.txt b/soc/renesas/ra/ra8m2/CMakeLists.txt new file mode 100644 index 0000000000000..7f3c66c46e472 --- /dev/null +++ b/soc/renesas/ra/ra8m2/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_sources_ifdef(CONFIG_PM + power.c +) + +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8m2/Kconfig b/soc/renesas/ra/ra8m2/Kconfig new file mode 100644 index 0000000000000..3c5c5dd352a2e --- /dev/null +++ b/soc/renesas/ra/ra8m2/Kconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA8M2 + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select FPU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select HAS_SWO + select XIP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL + select HAS_RENESAS_RA_FSP + select SOC_EARLY_INIT_HOOK + select HAS_PM + +config SOC_R7KA8M2JFLCAC_CM85 + select CPU_CORTEX_M85 + select GPIO_RA_HAS_VBTICTLR + +config SOC_R7KA8M2JFLCAC_CM33 + select CPU_CORTEX_M33 + select SOC_RA_SECOND_CORE_BUILD diff --git a/soc/renesas/ra/ra8m2/Kconfig.defconfig b/soc/renesas/ra/ra8m2/Kconfig.defconfig new file mode 100644 index 0000000000000..0547398a333e7 --- /dev/null +++ b/soc/renesas/ra/ra8m2/Kconfig.defconfig @@ -0,0 +1,42 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA8M2 + +config NUM_IRQS + default 96 + +DT_CPUCLK0_PATH := $(dt_nodelabel_path,cpuclk0) +DT_CPUCLK1_PATH := $(dt_nodelabel_path,cpuclk1) +DT_LOCO_PATH := $(dt_nodelabel_path,loco) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_CPUCLK0_PATH),clock-frequency) if SOC_R7KA8M2JFLCAC_CM85 && CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,$(DT_CPUCLK1_PATH),clock-frequency) if SOC_R7KA8M2JFLCAC_CM33 && CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER + +config CORTEX_M_SYSTICK + default n if RENESAS_RA_ULPT_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if RENESAS_RA_ULPT_TIMER + +config PM_DEVICE + default y if PM + +config PM_STATS + default n if PM + +config BUILD_OUTPUT_HEX + default y + +config CLOCK_CONTROL + default y + +config DCACHE + default n + +config CACHE_MANAGEMENT + default n + +endif # SOC_SERIES_RA8M2 diff --git a/soc/renesas/ra/ra8m2/Kconfig.soc b/soc/renesas/ra/ra8m2/Kconfig.soc new file mode 100644 index 0000000000000..2ebcfa0b44d8f --- /dev/null +++ b/soc/renesas/ra/ra8m2/Kconfig.soc @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA8M2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA8M2 series + +config SOC_R7KA8M2JFLCAC + bool + select SOC_SERIES_RA8M2 + help + R7KA8M2JFLCAC + +config SOC_R7KA8M2JFLCAC_CM85 + bool + select SOC_R7KA8M2JFLCAC + +config SOC_R7KA8M2JFLCAC_CM33 + bool + select SOC_R7KA8M2JFLCAC + +config SOC_SERIES + default "ra8m2" if SOC_SERIES_RA8M2 + +config SOC + default "r7ka8m2jflcac" if SOC_R7KA8M2JFLCAC diff --git a/soc/renesas/ra/ra8m2/power.c b/soc/renesas/ra/ra8m2/power.c new file mode 100644 index 0000000000000..bc20edd7a814d --- /dev/null +++ b/soc/renesas/ra/ra8m2/power.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +/* Low Power Mode instance control structure */ +static lpm_instance_ctrl_t pm_state_ctrl; + +/* Configuration for Runtime Idle Power State */ +const lpm_cfg_t pm_state_runtime_idle_cfg = { + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U, + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + .ram_retention_cfg.ram_retention = (uint16_t)(0x7F), + .ram_retention_cfg.tcm_retention = true, + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, + .p_extend = NULL, +}; + +/* Configuration for Standby Power State */ +const lpm_cfg_t pm_state_standby_cfg = { + .low_power_mode = LPM_MODE_STANDBY, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U, + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + .ram_retention_cfg.ram_retention = (uint16_t)(0x7F), + .ram_retention_cfg.tcm_retention = true, + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, + .p_extend = NULL, +}; + +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + R_LPM_Open(&pm_state_ctrl, &pm_state_runtime_idle_cfg); + __disable_irq(); + __set_BASEPRI(0); + __ISB(); + + R_LPM_LowPowerModeEnter(&pm_state_ctrl); + __enable_irq(); + __ISB(); + break; + + case PM_STATE_STANDBY: + R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg); + __disable_irq(); + __set_BASEPRI(0); + __ISB(); + + R_LPM_LowPowerModeEnter(&pm_state_ctrl); + __enable_irq(); + __ISB(); + break; + + default: + break; + } +} + +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + __fallthrough; + case PM_STATE_STANDBY: + R_LPM_Close(&pm_state_ctrl); + break; + + default: + break; + } + irq_unlock(0); +} diff --git a/soc/renesas/ra/ra8m2/ram_sections.ld b/soc/renesas/ra/ra8m2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8m2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8m2/sections.ld b/soc/renesas/ra/ra8m2/sections.ld new file mode 100644 index 0000000000000..a83eaad884aab --- /dev/null +++ b/soc/renesas/ra/ra8m2/sections.ld @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)),) +{ + KEEP(*(.option_setting_ofs0)) +} GROUP_LINK_IN(OFS_OFS0_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs2)),) +{ + KEEP(*(.option_setting_ofs2)) +} GROUP_LINK_IN(OFS_OFS2_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +SECTION_DATA_PROLOGUE(.option_setting_sas, DT_REG_ADDR(DT_NODELABEL(option_setting_sas)),) +{ + KEEP(*(.option_setting_sas)) +} GROUP_LINK_IN(OFS_SAS_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sec)),) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_OFS1_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sec)),) +{ + KEEP(*(.option_setting_ofs3_sec)) +} GROUP_LINK_IN(OFS_OFS3_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sel)),) +{ + KEEP(*(.option_setting_ofs1_sel)) +} GROUP_LINK_IN(OFS_OFS1_SEL_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sel)),) +{ + KEEP(*(.option_setting_ofs3_sel)) +} GROUP_LINK_IN(OFS_OFS3_SEL_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_bps_sec)),) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_BPS_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_otp_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_otp_pbps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_otp_pbps_sec)),) +{ + KEEP(*(.option_setting_otp_pbps_sec)) +} GROUP_LINK_IN(OFS_OTP_PBPS_SEC_MEMORY) +#endif diff --git a/soc/renesas/ra/ra8m2/soc.c b/soc/renesas/ra/ra8m2/soc.c new file mode 100644 index 0000000000000..db67c004f9e34 --- /dev/null +++ b/soc/renesas/ra/ra8m2/soc.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA8M2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "soc.h" + +#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk) + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +#ifdef CONFIG_RUNTIME_NMI +extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[]; +extern void NMI_Handler(void); +#endif /* CONFIG_RUNTIME_NMI */ + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + + for (uint32_t i = 0; i < 5; i++) { + g_protect_counters[i] = 0; + } + + SystemCoreClock = BSP_MOCO_HZ; + +#ifdef CONFIG_RUNTIME_NMI + for (uint32_t i = 0; i < 16; i++) { + g_bsp_group_irq_sources[i] = 0; + } + + z_arm_nmi_set_handler(NMI_Handler); +#endif /* CONFIG_RUNTIME_NMI */ + +#ifdef CONFIG_CPU_CORTEX_M85 +#ifdef CONFIG_ICACHE + SCB->CCR = (uint32_t)CCR_CACHE_ENABLE; + barrier_dsync_fence_full(); + barrier_isync_fence_full(); +#endif +#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT) + /* Apply Arm Cortex-M85 errata workarounds for D-Cache + * Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register. + * Set bit 16 in ACTLR to 1. + * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 + * Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0, + * Document ID: SDEN-2236668). + */ + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + ICB->ACTLR |= (1U << 16U); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + + sys_cache_data_enable(); +#endif +#endif /*CONFIG_CPU_CORTEX_M85*/ + +#ifdef CONFIG_CPU_CORTEX_M33 +#if FSP_PRIV_TZ_USE_SECURE_REGS + /* Disable protection using PRCR register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Initialize peripherals to secure mode for flat projects */ + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + + R_CPSCU->ICUSARG = 0; + R_CPSCU->ICUSARH = 0; + R_CPSCU->ICUSARI = 0; + + /* Enable protection using PRCR register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif +#endif /*CONFIG_CPU_CORTEX_M33*/ +} diff --git a/soc/renesas/ra/ra8m2/soc.h b/soc/renesas/ra/ra8m2/soc.h new file mode 100644 index 0000000000000..a494b8509f692 --- /dev/null +++ b/soc/renesas/ra/ra8m2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA8M2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA8M2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA8M2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA8M2_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index 31cb6fd04157a..e3f60cf7468eb 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -91,3 +91,9 @@ family: cpuclusters: - name: cm85 - name: cm33 + - name: ra8m2 + socs: + - name: r7ka8m2jflcac + cpuclusters: + - name: cm85 + - name: cm33 diff --git a/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..47c2885592319 --- /dev/null +++ b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + test-comp = &acmphs0; + }; + + zephyr,user { + test-gpios = <&ioport0 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + acmphs0_ivcmp0: acmphs0_ivcmp0 { + group1 { + /* CH0 IVCMP3 */ + psels = ; + renesas,analog-enable; + }; + }; +}; + +&acmphs_global { + status = "okay"; + + acmphs0 { + pinctrl-0 = <&acmphs0_ivcmp0>; + pinctrl-names = "default"; + interrupts = <95 1>; + interrupt-names = "hs"; + reference-input-source = "ivref2"; + compare-input-source = "ivcmp3"; + noise-filter = <1>; + status = "okay"; + }; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/counter/counter_basic_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..82b9544b14e2c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&agt0 { + interrupts = <95 1>, <94 1>; + interrupt-names = "agti", "agtcmai"; + renesas,count-source = "AGT_CLOCK_LOCO"; + renesas,prescaler = <0>; + status = "okay"; + + counter0: counter { + status = "okay"; + }; +}; diff --git a/tests/drivers/disk/disk_access/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/disk/disk_access/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..377247abb30ad --- /dev/null +++ b/tests/drivers/disk/disk_access/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/tests/drivers/disk/disk_performance/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/disk/disk_performance/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..377247abb30ad --- /dev/null +++ b/tests/drivers/disk/disk_performance/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..2caebf0e9eb87 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma0 { + status = "okay"; + interrupts = <95 1>, <94 1>; + interrupt-names = "ch0", "ch1"; +}; diff --git a/tests/drivers/dma/loop_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/dma/loop_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..d3afbdb4c6197 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma0 { + status = "okay"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "ch0", "ch1", "ch2"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..3b626dd7fad28 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SENSOR_GY271_QMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..7ce912036360c --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &iic1; + gy271 = &iic1; + }; +}; + +&iic1 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.conf new file mode 100644 index 0000000000000..3b626dd7fad28 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SENSOR_GY271_QMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.overlay new file mode 100644 index 0000000000000..d770a0b7120d0 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85_sci_b_i2c.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &i2c0; + gy271 = &i2c0; + }; +}; + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* SDA0 SCL0*/ + psels = , + ; + drive-strength = "medium"; + drive-open-drain; + }; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + interrupts = <95 1>, <94 1>, <93 1>; + interrupt-names = "rxi", "txi", "tei"; + status = "okay"; + + i2c0: i2c { + sda-output-delay = <300>; + noise-filter-clock-select = <1>; + bit-rate-modulation; + status = "okay"; + }; +}; diff --git a/tests/drivers/i2c/i2c_api/testcase.yaml b/tests/drivers/i2c/i2c_api/testcase.yaml index 44c47e4d9ded9..da17a5645d16b 100644 --- a/tests/drivers/i2c/i2c_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_api/testcase.yaml @@ -29,6 +29,7 @@ tests: - ek_ra8p1/r7ka8p1kflcac/cm33 - mck_ra8t2/r7ka8t2lfecac/cm85 - ek_ra8d2/r7ka8d2kflcac/cm85 + - ek_ra8m2/r7ka8m2jflcac/cm85 extra_args: - DTC_OVERLAY_FILE="./boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}_sci_b_i2c.overlay" - CONF_FILE="./prj.conf ./boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}_sci_b_i2c.conf" diff --git a/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..8d938df796d10 --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 +CONFIG_I2S_TEST_USE_GPIO_LOOPBACK=y +CONFIG_I2S_TEST_SEPARATE_DEVICES=y diff --git a/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..45703f6d03fe1 --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-node0 = &i2s1; + i2s-node1 = &i2s0; + }; +}; + +&pinctrl { + ssie0_default: ssie0_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_TX */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&ssie0_default>; + pinctrl-names = "default"; + interrupts = <93 1>, <94 1>, <95 1>; + interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <91 1>, <92 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <89 1>, <90 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(512000) PWM_POLARITY_NORMAL>; + }; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..70e94e25598a1 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_I2S_INIT_PRIORITY=52 +CONFIG_I2S_TEST_USE_GPIO_LOOPBACK=y +CONFIG_I2S_TEST_SEPARATE_DEVICES=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_8000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_16000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_32000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_48000=y +CONFIG_I2S_TEST_SKIP_SAMPLERATE_96000=y diff --git a/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..65134cc09ea77 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + i2s-node0 = &i2s1; + i2s-node1 = &i2s0; + }; +}; + +&pinctrl { + ssie0_default: ssie0_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_TX */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + ssie1_default: ssie1_default { + group1 { + /* SSI_BCK SSI_LRCK SSI_DATA */ + psels = , + , + ; + drive-strength = "high"; + }; + }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&ssie0_default>; + pinctrl-names = "default"; + interrupts = <93 1>, <94 1>, <95 1>; + interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&i2s1 { + pinctrl-0 = <&ssie1_default>; + pinctrl-names = "default"; + interrupts = <91 1>, <92 1>; + interrupt-names = "ssi_rt", "ssi_if"; + status = "okay"; + clocks = <&pclkb MSTPC 7>, <&ssi_internal_clock 0>; + clock-names = "pclk", "audio-clock"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + interrupts = <89 1>, <90 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + ssi_internal_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(2822400) PWM_POLARITY_NORMAL>; + }; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/pwm/pwm_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..99ff55cf7d241 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pwm-test = &pwm1; + }; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..8ed114e45d99b --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + /* first index must be a 32-Bit timer */ + pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, + <&pwm10 0 0 PWM_POLARITY_NORMAL>; + }; +}; + +&pinctrl { + pwm10_default: pwm10_default { + group1 { + /* GTIOC10A */ + psels = ; + }; + }; +}; + +&pwm10 { + pinctrl-0 = <&pwm10_default>; + pinctrl-names = "default"; + interrupts = <94 1>, <95 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; diff --git a/tests/drivers/sdhc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/sdhc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..7b7863d0b0101 --- /dev/null +++ b/tests/drivers/sdhc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..9c7b8ccf32d37 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI_LOOPBACK_MODE_LOOP=y +CONFIG_SPI_B_INTERRUPT=y +CONFIG_SPI_B_RA_DTC=y diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..d9abde113c3d8 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + +&spi1 { + rx-dtc; + tx-dtc; + status = "okay"; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..9dcf49056b26e --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +dut: &uart7 { + current-speed = <115200>; + status = "okay"; +}; diff --git a/tests/subsys/fs/ext2/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/subsys/fs/ext2/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..accc354e83458 --- /dev/null +++ b/tests/subsys/fs/ext2/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + + partition { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size_cells = <1>; + + slot1_partition: partition@0 { + reg = <0x00000000 0x800000>; + }; + }; + }; +}; diff --git a/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf b/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf new file mode 100644 index 0000000000000..0238ff6b3c6af --- /dev/null +++ b/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.conf @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_DISK_DRIVER_RAM=n +CONFIG_DISK_DRIVER_FLASH=n +CONFIG_FS_FATFS_HAS_RTC=n diff --git a/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..377247abb30ad --- /dev/null +++ b/tests/subsys/fs/fat_fs_api/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml index 135b4ba977beb..4f17ce2010a64 100644 --- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml +++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml @@ -28,6 +28,7 @@ tests: - ek_ra8p1/r7ka8p1kflcac/cm85 - mck_ra8t2/r7ka8t2lfecac/cm85 - ek_ra8d2/r7ka8d2kflcac/cm85 + - ek_ra8m2/r7ka8m2jflcac/cm85 tags: pm integration_platforms: - mec15xxevb_assy6853 diff --git a/tests/subsys/sd/sdmmc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay b/tests/subsys/sd/sdmmc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay new file mode 100644 index 0000000000000..7b7863d0b0101 --- /dev/null +++ b/tests/subsys/sd/sdmmc/boards/ek_ra8m2_r7ka8m2jflcac_cm85.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &sdhc1; + }; +}; + +&pinctrl { + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; + +&sdhc1 { + pinctrl-0 = <&sdhc1_default>; + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <95 1>, <94 1>, <93 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +};