From f39c6209ba18131fc3e9f6fe28174a53712a8129 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 21 Oct 2025 12:05:43 +0200 Subject: [PATCH] riscv: remove unneeded select ATOMIC_OPERATIONS_BUILTIN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When RISCV_ISA_EXT_A is enabled, ATOMIC_OPERATIONS_BUILTIN automaticly enabled, we don't need to do it at the soc level again. Signed-off-by: Fin Maaß --- soc/andestech/ae350/Kconfig | 1 - soc/egis/et171/Kconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig index da4cc0193889c..031bc0756c717 100644 --- a/soc/andestech/ae350/Kconfig +++ b/soc/andestech/ae350/Kconfig @@ -19,7 +19,6 @@ config SOC_SERIES_ANDES_AE350 select CPU_HAS_ANDES_PMA select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT - select ATOMIC_OPERATIONS_BUILTIN select SOC_EARLY_INIT_HOOK if RISCV_CUSTOM_CSR_ANDES_PMA select SOC_PER_CORE_INIT_HOOK if RISCV_CUSTOM_CSR_ANDES_PMA imply XIP diff --git a/soc/egis/et171/Kconfig b/soc/egis/et171/Kconfig index 2d78bc2d8bfc6..88ec3b2d11fac 100644 --- a/soc/egis/et171/Kconfig +++ b/soc/egis/et171/Kconfig @@ -13,7 +13,6 @@ config SOC_EGIS_ET171 select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI - select ATOMIC_OPERATIONS_BUILTIN select CPU_HAS_FPU select CPU_HAS_DCACHE select CPU_HAS_ICACHE