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zerbinazerbina
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test
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‎.github/workflows/build-and-test.yml‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,10 +80,6 @@ jobs:
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revision: 2025.07.25
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overlay-triplets: ${{ github.workspace }}/tools/vcpkg/triplets
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83-
- name: Install dependencies (Windows)
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if: runner.os == 'Windows'
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run: vcpkg install pcre sqlite3
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- name: Set Xcode version (macOS M1)
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if: runner.os == 'macOS' && runner.arch == 'ARM64'
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uses: maxim-lobanov/setup-xcode@v1

‎compiler/backend/mir2cg.nim‎

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1698,18 +1698,11 @@ proc magicToCgir(c; env; tree; n; dest: Expr, stmts, bu) =
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of mSizeOf:
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let typ = argt(0)
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let desc = env.types.headerFor(typ, Canonical)
1701-
if desc.size(env.types) >= 0:
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wrapAsgn:
1703-
^c.genInt(env, desc.size(env.types), env.types.sizeType, bu)
1704-
else:
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wrapAsgn Sizeof(^env.types.sizeType, typ)
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wrapAsgn Sizeof(^env.types.sizeType, typ)
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of mAlignOf:
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let typ = argt(0)
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let desc = env.types.headerFor(typ, Canonical)
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if desc.size(env.types) >= 0:
1710-
wrapAsgn ^c.genInt(env, desc.align, tree[n].typ, bu)
1711-
else:
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wrapAsgn Alignof(^env.types.sizeType, typ)
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wrapAsgn Alignof(^env.types.sizeType, typ)
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of mOffsetOf:
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let
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typ = argt(0)

‎tests/arc/thard_alignment.nim‎

Lines changed: 130 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,138 @@
11
discard """
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disabled: "arm64"
3-
matrix: "-d:useMalloc --passC:\"-fsanitize=undefined -fsanitize-undefined-trap-on-error\""
3+
matrix: "-d:test1;-d:test2;-d:test3;-d:test4"
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output: "y"
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"""
66

7-
{.passC: "-march=native".}
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when defined(test1):
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{.passC: "-mavx".}
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elif defined(test2):
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{.passC: "-mavx", passC: "-mbmi".}
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elif defined(test3):
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{.passC: "-mavx", passC: "-mbmi", passC: "-mbmi2".}
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elif defined(test3):
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{.passC: "-mavx", passC: "-mbmi", passC: "-mbmi2", pass: "-mlzcnt".}
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# ported from Microsoft documentation of __cpuid and __cpuidex
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type Rep = object
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nIds: int
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nExIds: int
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isIntel, isAMD: bool
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f_1_ECX: set[0..31]
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f_1_EDX: set[0..31]
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f_7_EBX: set[0..31]
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f_7_ECX: set[0..31]
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f_81_ECX: set[0..31]
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f_81_EDX: set[0..31]
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proc cpuid(x: array[4, cint], a: cint) {.header: "intrin.h", importc: "__cpuid".}
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proc cpuidex(x: array[4, cint], a: cint, b: cint) {.header: "intrin.h", importc: "__cpuidex".}
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proc read(): Rep =
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var cpui: array[4, cint]
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cpuid(cpui, 0)
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result.nIds = int cpui[0]
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var data: seq[array[4, cint]]
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for i in 0..<result.nIds:
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cpuidex(cpui, cint(i), 0);
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data.add(cpui)
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var vendor: array[32, char]
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copyMem(addr vendor[0], addr data[0][1], 4)
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copyMem(addr vendor[4], addr data[0][3], 4)
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copyMem(addr vendor[8], addr data[0][2], 4)
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if cast[cstring](addr vendor) == "GenuineIntel":
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result.isIntel = true
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elif cast[cstring](addr vendor) == "AuthenticAMD":
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result.isAMD = true
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if result.nIds >= 1:
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result.f_1_ECX = cast[set[0..31]](data[1][2])
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result.f_1_EDX = cast[set[0..31]](data[1][3])
54+
55+
if result.nIds >= 7:
56+
result.f_7_EBX = cast[set[0..31]](data[7][1])
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result.f_7_ECX = cast[set[0..31]](data[7][2])
58+
59+
cpuid(cpui, cast[cint](0x80000000));
60+
result.nExIds = cpui[0];
61+
62+
var extdata: seq[array[4, cint]]
63+
for i in 0x80000000..<result.nExIds:
64+
cpuidex(cpui, cint(i), 0)
65+
extdata.add(cpui)
66+
67+
if result.nExIds >= 0x80000001:
68+
result.f_81_ECX = cast[set[0..31]](extdata[1][2])
69+
result.f_81_EDX = cast[set[0..31]](extdata[1][3])
70+
71+
var x = read()
72+
73+
template show(name: untyped, val, bit: untyped) =
74+
echo astToStr(name), " = ", bit in val
75+
76+
template show(name: untyped, val: untyped) =
77+
echo astToStr(name), " = ", val
78+
79+
show SSE3, x.f_1_ECX, 0
80+
show PCLMULQDQ, x.f_1_ECX, 1
81+
show MONITOR, x.f_1_ECX, 3
82+
show SSSE3, x.f_1_ECX, 9
83+
show FMA, x.f_1_ECX, 12
84+
show CMPXCHG16B, x.f_1_ECX, 13
85+
show SSE41, x.f_1_ECX, 19
86+
show SSE42, x.f_1_ECX, 20
87+
show MOVBE, x.f_1_ECX, 22
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show POPCNT, x.f_1_ECX, 23
89+
show AES, x.f_1_ECX, 25
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show XSAVE, x.f_1_ECX, 26
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show OSXSAVE, x.f_1_ECX, 27
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show AVX, x.f_1_ECX, 28
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show F16C, x.f_1_ECX, 29
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show RDRAND, x.f_1_ECX, 30
95+
96+
show MSR, x.f_1_EDX, 5
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show CX8, x.f_1_EDX, 8
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show SEP, x.f_1_EDX, 11
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show CMOV, x.f_1_EDX, 15
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show CLFSH, x.f_1_EDX, 19
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show MMX, x.f_1_EDX, 23
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show FXSR, x.f_1_EDX, 24
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show SSE, x.f_1_EDX, 25
104+
show SSE2, x.f_1_EDX, 26
105+
106+
show FSGSBASE, x.f_7_EBX, 0
107+
show BMI1, x.f_7_EBX, 3
108+
show HLE, x.isIntel and 4 in x.f_7_EBX
109+
show AVX2, x.f_7_EBX, 5
110+
show BMI2, x.f_7_EBX, 8
111+
show ERMS, x.f_7_EBX, 9
112+
show INVPCID, x.f_7_EBX, 10
113+
show RTM, x.isIntel and 11 in x.f_7_EBX
114+
show AVX512F, x.f_7_EBX, 16
115+
show RDSEED, x.f_7_EBX, 18
116+
show ADX, x.f_7_EBX, 19
117+
show AVX512PF, x.f_7_EBX, 26
118+
show AVX512ER, x.f_7_EBX, 27
119+
show AVX512CD, x.f_7_EBX, 28
120+
show SHA, x.f_7_EBX, 29
121+
122+
show PREFETCHWT1, x.f_7_ECX, 0
123+
124+
show LAHF, x.f_81_ECX, 0
125+
show LZCNT, x.isIntel and 5 in x.f_81_ECX
126+
show ABM, x.isAMD and 5 in x.f_81_ECX
127+
show SSE4a, x.isAMD and 6 in x.f_81_ECX
128+
show XOP, x.isAMD and 11 in x.f_81_ECX
129+
show TBM, x.isAMD and 11 in x.f_81_ECX
130+
131+
show SYSCALL, x.isIntel and 11 in x.f_81_EDX
132+
show MMXEXT, x.isAMD and 22 in x.f_81_EDX
133+
show RDTSCP, x.isIntel and 27 in x.f_81_EDX
134+
show "3DNOWEXT", x.isAMD and 30 in x.f_81_EDX
135+
show "3DNOW", x.isAMD and 31 in x.f_81_EDX
8136

9137
proc isAlignedCheck(p: pointer, alignment: int) =
10138
doAssert (cast[uint](p) and uint(alignment - 1)) == 0

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