Wrong triggering of ddt_walk_o signal

[mhayat-10xe]

I wrote an assertion that states:

if there is a ddt_walk_o signal high then in the past cycle ddtc_miss_q(sva internal signal) must be high too.

Here is a counter-example of the assertion failure, first DC is loaded, and then in the 10th cycle we have an IODIR.INVAL_DDT(flush_ddtc_i == 1 and flush_dv_i == 0) command that flushes all DDT entries. Now, in the 12th cycle when req_trans_i is 0, ddt_walk must be low, but ddt_walk is wrongly triggered.