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stage2-wasm: clz fix
1 parent a429d04 commit 15bc2ab

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2 files changed

+12
-3
lines changed

2 files changed

+12
-3
lines changed

src/arch/wasm/CodeGen.zig

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6272,11 +6272,21 @@ fn airClz(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
62726272

62736273
switch (wasm_bits) {
62746274
32 => {
6275-
try cg.emitWValue(operand);
6275+
if (int_info.signedness == .signed) {
6276+
const mask = ~@as(u32, 0) >> @intCast(32 - int_info.bits);
6277+
_ = try cg.binOp(operand, .{ .imm32 = mask }, ty, .@"and");
6278+
} else {
6279+
try cg.emitWValue(operand);
6280+
}
62766281
try cg.addTag(.i32_clz);
62776282
},
62786283
64 => {
6279-
try cg.emitWValue(operand);
6284+
if (int_info.signedness == .signed) {
6285+
const mask = ~@as(u64, 0) >> @intCast(64 - int_info.bits);
6286+
_ = try cg.binOp(operand, .{ .imm64 = mask }, ty, .@"and");
6287+
} else {
6288+
try cg.emitWValue(operand);
6289+
}
62806290
try cg.addTag(.i64_clz);
62816291
try cg.addTag(.i32_wrap_i64);
62826292
},

test/behavior/math.zig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,6 @@ test "@clz" {
6565
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
6666
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
6767
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
68-
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
6968
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
7069
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
7170

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