@@ -297,7 +297,7 @@ pub fn fromWindowsContext(ctx: *const std.os.windows.CONTEXT) Native {
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};
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}
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- pub const X86 = struct {
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+ const X86 = struct {
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/// The first 8 registers here intentionally match the order of registers in the x86 instruction
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/// encoding. This order is inherited by the PUSHA instruction and the DWARF register mappings,
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/// among other things.
@@ -356,7 +356,7 @@ pub const X86 = struct {
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}
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};
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- pub const X86_64 = struct {
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+ const X86_64 = struct {
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/// The order here intentionally matches the order of the DWARF register mappings. It's unclear
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/// where those mappings actually originated from---the ordering of the first 4 registers seems
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/// quite unusual---but it is currently convenient for us to match DWARF.
@@ -426,7 +426,7 @@ pub const X86_64 = struct {
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}
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};
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- pub const Arm = struct {
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+ const Arm = struct {
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/// The numbered general-purpose registers R0 - R15.
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r : [16 ]u32 ,
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@@ -480,7 +480,7 @@ pub const Arm = struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const Aarch64 = extern struct {
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+ const Aarch64 = extern struct {
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/// The numbered general-purpose registers X0 - X30.
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x : [31 ]u64 ,
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sp : u64 ,
@@ -542,7 +542,7 @@ pub const Aarch64 = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const Hexagon = extern struct {
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+ const Hexagon = extern struct {
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/// The numbered general-purpose registers r0 - r31.
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r : [32 ]u32 ,
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pc : u32 ,
@@ -610,7 +610,7 @@ pub const Hexagon = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const LoongArch = extern struct {
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+ const LoongArch = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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r : [32 ]Gpr ,
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pc : Gpr ,
@@ -712,7 +712,7 @@ pub const LoongArch = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const Mips = extern struct {
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+ const Mips = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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r : [32 ]Gpr ,
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pc : Gpr ,
@@ -834,7 +834,7 @@ pub const Mips = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const Powerpc = extern struct {
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+ const Powerpc = extern struct {
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/// The numbered general-purpose registers r0 - r31.
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r : [32 ]Gpr ,
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pc : Gpr ,
@@ -990,7 +990,7 @@ pub const Powerpc = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const Riscv = extern struct {
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+ const Riscv = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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r : [32 ]Gpr ,
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pc : Gpr ,
@@ -1096,7 +1096,7 @@ pub const Riscv = extern struct {
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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- pub const S390x = extern struct {
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+ const S390x = extern struct {
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/// The numbered general-purpose registers r0 - r15.
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r : [16 ]u64 ,
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/// The program counter.
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