Update previously missed relaxed SIMD ops

dcodeIO · dcodeIO · commit 46948f8f655f · 2025-04-22T02:01:29.000+02:00
diff --git a/index.d.ts b/index.d.ts
@@ -458,10 +458,10 @@ declare module binaryen {
     XorVec128,
     AndNotVec128,
     BitselectVec128,
-    RelaxedFmaVecF32x4,
-    RelaxedFmsVecF32x4,
-    RelaxedFmaVecF64x2,
-    RelaxedFmsVecF64x2,
+    RelaxedMaddVecF32x4,
+    RelaxedNmaddVecF32x4,
+    RelaxedMaddVecF64x2,
+    RelaxedNmaddVecF64x2,
     LaneselectI8x16,
     LaneselectI16x8,
     LaneselectI32x4,
