Merge pull request #14 from UTOSS/boris/sv2v

Integrate `sv2v`

Author: TheDeepestSpace

.devcontainer/Dockerfile

@@ -24,5 +24,18 @@ RUN umask 022 && \
     tar zxf - -C /usr/local --strip-components=1 && \
     chmod 755 /usr/local/bin
 
+# install sv2v
+ARG SV2V_VERSION=0.0.13
+ARG SV2V_ZIP_NAME=sv2v-Linux.zip
+ARG SV2V_ZIP_URL=https://github.com/zachjs/sv2v/releases/download/v${SV2V_VERSION}/${SV2V_ZIP_NAME}
+ARG SV2V_ZIP_HASH="552799a1d76cd177b9b4cc63a3e77823a3d2a6eb4ec006569288abeff28e1ff8 ${SV2V_ZIP_NAME}"
+RUN mkdir /tmp/sv2v && \
+    cd /tmp/sv2v && \
+    wget ${SV2V_ZIP_URL} && \
+    echo ${SV2V_ZIP_HASH} | sha256sum -c && \
+    unzip ${SV2V_ZIP_NAME} && \
+    chmod +x sv2v-Linux/sv2v && sudo cp sv2v-Linux/sv2v /usr/local/bin && \
+    cd .. && rm -r /tmp/sv2v
+
 # Install LibreLane
 RUN /ttsetup/venv/bin/pip install librelane==2.4.2

.github/actions/install-sv2v/action.yaml

@@ -0,0 +1,21 @@
+name: 'Install sv2v'
+description: 'Install sv2v SystemVerilog to Verilog converter'
+runs:
+  using: 'composite'
+  steps:
+    - name: Install sv2v
+      shell: bash
+      run: |
+        SV2V_VERSION=0.0.13
+        SV2V_ZIP_NAME=sv2v-Linux.zip
+        SV2V_ZIP_URL=https://github.com/zachjs/sv2v/releases/download/v${SV2V_VERSION}/${SV2V_ZIP_NAME}
+        SV2V_ZIP_HASH="552799a1d76cd177b9b4cc63a3e77823a3d2a6eb4ec006569288abeff28e1ff8 ${SV2V_ZIP_NAME}"
+
+        mkdir /tmp/sv2v
+        cd /tmp/sv2v
+        wget ${SV2V_ZIP_URL}
+        echo ${SV2V_ZIP_HASH} | sha256sum -c
+        unzip ${SV2V_ZIP_NAME}
+        chmod +x sv2v-Linux/sv2v
+        sudo cp sv2v-Linux/sv2v /usr/local/bin
+        rm -rf /tmp/sv2v

.github/workflows/docs.yaml

@@ -13,5 +13,11 @@ jobs:
         with:
           submodules: recursive
 
+      - name: Install sv2v
+        uses: ./.github/actions/install-sv2v
+
+      - name: sv2v
+        run: make sv2v
+
       - name: Build docs
         uses: TinyTapeout/tt-gds-action/docs@ttsky25b

.github/workflows/gds.yaml

@@ -21,23 +21,23 @@ jobs:
         with:
           script: |
             const comment = `👋 Hello! Before merging this PR, you can use the \`run-gds\` label to start the GDS workflow.
-            
+
             ⚠️ **Important:** The GDS workflow takes a long time (~1 hour) and consumes significant CI runtime quota.
-            
+
             **Before running the GDS workflow:**
             1. Make sure you've run the hardening command locally first:
                \`\`\`bash
                ./tt/tt_tool.py --harden
                \`\`\`
             2. Verify that the hardening command succeeded without errors
-            
+
             **To run the GDS workflow:**
             - Add the \`run-gds\` label to this PR
             - The workflow will run automatically
             - It will also re-run on subsequent pushes while the label remains attached
-            
+
             📚 For more information about the hardening command, see the [TinyTapeout GDS Action](https://github.com/TinyTapeout/tt-gds-action/blob/0d3300e15eda42ae3a24a2bd36433bdd20b32a9f/action.yml#L101-L103).`;
-            
+
             github.rest.issues.createComment({
               issue_number: context.issue.number,
               owner: context.repo.owner,
@@ -55,6 +55,12 @@ jobs:
         with:
           submodules: recursive
 
+      - name: Install sv2v
+        uses: ./.github/actions/install-sv2v
+
+      - name: sv2v
+        run: make sv2v
+
       - name: Build GDS
         uses: TinyTapeout/tt-gds-action@ttsky25b
         with:

.github/workflows/test.yaml

@@ -23,6 +23,12 @@ jobs:
         shell: bash
         run: pip install -r test/requirements.txt
 
+      - name: Install sv2v
+        uses: ./.github/actions/install-sv2v
+
+      - name: sv2v
+        run: make sv2v
+
       - name: Run tests
         run: |
           cd test

.gitignore

@@ -1,5 +1,6 @@
 .DS_Store
 .idea
+*.sv2v.v
 *.vcd
 *.fst
 *.fst.hier

.submodules/utoss-risc-v

@@ -0,0 +1,26 @@
+# Convert SystemVerilog (.sv) files to Verilog (.v) using sv2v
+
+SV_FILES := $(shell find src/ -follow -name "*.sv" -type f 2>/dev/null | grep -v '/src/src')
+INCLUDE_FLAGS := -I src/utoss-risc-v/
+DEFINE_FLAGS := -DUTOSS_RISCV_HARDENING
+V_FILES := $(SV_FILES:.sv=.sv2v.v)
+
+.PHONY: sv2v tt clean help
+
+sv2v:
+	@mkdir -p .sv2v_temp
+	@sv2v $(INCLUDE_FLAGS) $(DEFINE_FLAGS) $(SV_FILES) -w .sv2v_temp
+	@for svfile in $(SV_FILES); do \
+		module_name=$$(basename "$$svfile" .sv); \
+		if [ -f ".sv2v_temp/$$module_name.v" ]; then \
+			mv ".sv2v_temp/$$module_name.v" "$$(dirname "$$svfile")/$$module_name.sv2v.v"; \
+		fi; \
+	done
+	@rm -rf .sv2v_temp
+
+tt: sv2v
+	./tt/tt_tool.py --create-user-config
+	./tt/tt_tool.py --harden
+
+clean:
+	@rm -f $(V_FILES)

Makefile

@@ -8,7 +8,7 @@ project:
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "4x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "8x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_utoss_riscv"
@@ -17,19 +17,16 @@ project:
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "tt_um_utoss_riscv.sv"
-    - "MA.sv"
-    - "utoss-risc-v/src/ALU_ALUdecoder/ALU.v"
-    - "utoss-risc-v/src/ALU_ALUdecoder/ALUdecoder.sv"
-    - "utoss-risc-v/src/ControlFSM.sv"
-    - "utoss-risc-v/src/fetch.sv"
-    - "utoss-risc-v/src/Instruction_Decode/Instruction_Decode.sv"
-    - "utoss-risc-v/src/Instruction_Decode/MemoryLoader.sv"
-    - "utoss-risc-v/src/Instruction_Decode/RegisterFile.v"
-    - "utoss-risc-v/src/params.svh"
-    - "utoss-risc-v/src/types.svh"
-    - "utoss-risc-v/src/utils.svh"
-    - "utoss-risc-v/src/utoss_riscv.sv"
+    - "tt_um_utoss_riscv.sv2v.v"
+    - "MA.sv2v.v"
+    - "utoss-risc-v/src/ALU_ALUdecoder/ALU.sv2v.v"
+    - "utoss-risc-v/src/ALU_ALUdecoder/ALUdecoder.sv2v.v"
+    - "utoss-risc-v/src/ControlFSM.sv2v.v"
+    - "utoss-risc-v/src/fetch.sv2v.v"
+    - "utoss-risc-v/src/Instruction_Decode/Instruction_Decode.sv2v.v"
+    - "utoss-risc-v/src/Instruction_Decode/MemoryLoader.sv2v.v"
+    - "utoss-risc-v/src/Instruction_Decode/registerFile.v"
+    - "utoss-risc-v/src/utoss_riscv.sv2v.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).

info.yaml

@@ -6,7 +6,7 @@ SIM ?= icarus
 FST ?= -fst # Use more efficient FST format
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = tt_um_utoss_riscv.sv MA.sv utoss-risc-v/src/ALU_ALUdecoder/ALU.v utoss-risc-v/src/ALU_ALUdecoder/ALUdecoder.sv utoss-risc-v/src/ControlFSM.sv utoss-risc-v/src/fetch.sv utoss-risc-v/src/Instruction_Decode/Instruction_Decode.sv utoss-risc-v/src/Instruction_Decode/MemoryLoader.sv utoss-risc-v/src/Instruction_Decode/RegisterFile.v utoss-risc-v/src/params.svh utoss-risc-v/src/types.svh utoss-risc-v/src/utils.svh utoss-risc-v/src/utoss_riscv.sv
+PROJECT_SOURCES = tt_um_utoss_riscv.sv MA.sv utoss-risc-v/src/ALU_ALUdecoder/ALU.sv utoss-risc-v/src/ALU_ALUdecoder/ALUdecoder.sv utoss-risc-v/src/ControlFSM.sv utoss-risc-v/src/fetch.sv utoss-risc-v/src/Instruction_Decode/Instruction_Decode.sv utoss-risc-v/src/Instruction_Decode/MemoryLoader.sv utoss-risc-v/src/Instruction_Decode/registerFile.v utoss-risc-v/src/params.svh utoss-risc-v/src/types.svh utoss-risc-v/src/utils.svh utoss-risc-v/src/utoss_riscv.sv
 COMPILE_ARGS += -DUTOSS_RISCV_HARDENING
 
 ifneq ($(GATES),yes)