Step 0 - Transfer the contents of Analysis_Script folder to the Verilog_Design folder
Step 1- Install requirements from requirements.txt
pip install -r requirements.txt
Step 2- Generate the Value Change Dump (Output VCDs also present in vcd)
iverilog -D DUMPFILE="alu_clean.vcd" -o sim_clean.vvp alu_clean.v alu_tb.v
iverilog -D DUMPFILE="alu_clean.vcd" -o sim_clean.vvp alu_clean.v alu_tb.v
Step 3 - Analyse the VCD files using analyze_vcd.py script
python3 analyze_vcd.py alu_clean.vcd alu_trojan.vcd
