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raiden00placassis
raiden00pl
authored and
acassis
committed
!arch/arm/src/stm32: unify the timer input clock board options
Replace the divergent board conventions for the timer input clock frequency with a single uniform convention provided by every board: - STM32_APBx_TIMn_CLKIN and BOARD_TIMn_FREQUENCY -> STM32_TIMn_CLKIN - STM32_APBx_LPTIMn_CLKIN, BOARD_LPTIMn_FREQUENCY and STM32_LPTIMn_FREQUENCY -> STM32_LPTIMn_CLKIN - STM32_APB1_THRTIM1_CLKIN and BOARD_HRTIM1_FREQUENCY -> STM32_HRTIM1_CLKIN All STM32 consumers (tim/lptim/pwm/adc/dac/capture/sdadc/dfsdm/ pulsecount) updated to match; the timer input clock is now bus-agnostic in the drivers. Boards that carried the same timer clock in more than one convention now define STM32_TIMn_CLKIN exactly once, derived from the APB bus clock (PCLKx with the x2 doubler when the APB prescaler is greater than 1), instead of redefining it with a second, sometimes different, value. BREAKING CHANGE: The timer input-clock board macros STM32_APBx_TIMn_CLKIN, BOARD_TIMn_FREQUENCY, STM32_APBx_LPTIMn_CLKIN, BOARD_LPTIMn_FREQUENCY, STM32_LPTIMn_FREQUENCY, STM32_APB1_THRTIM1_CLKIN and BOARD_HRTIM1_FREQUENCY are removed in favor of STM32_TIMn_CLKIN, STM32_LPTIMn_CLKIN and STM32_HRTIM1_CLKIN. Out-of-tree boards must define the new macros (drop the APB bus from the name, keep the value), and out-of-tree drivers referencing the old names must be updated. Signed-off-by: raiden00pl <raiden00@railab.me>
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134 files changed

Lines changed: 1607 additions & 2763 deletions

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‎Documentation/guides/stm32_ports.rst‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,24 @@ prefix replace is safe)::
135135
STM32WL5_ -> STM32_
136136
STM32N6_ -> STM32_
137137

138+
Board timer input clock unified to ``STM32_TIMn_CLKIN``
139+
-------------------------------------------------------
140+
141+
The board-provided timer input clock frequency macros were unified to a
142+
single convention: every board defines ``STM32_TIMn_CLKIN`` for the TIM
143+
peripherals, ``STM32_LPTIMn_CLKIN`` for the LPTIM peripherals and
144+
``STM32_HRTIM1_CLKIN`` for HRTIM. The APB bus is no longer encoded in the
145+
macro name. Update out-of-tree board headers and drivers (drop the bus
146+
from the name, keep the value)::
147+
148+
STM32_APBx_TIMn_CLKIN -> STM32_TIMn_CLKIN
149+
BOARD_TIMn_FREQUENCY -> STM32_TIMn_CLKIN
150+
STM32_APBx_LPTIMn_CLKIN -> STM32_LPTIMn_CLKIN
151+
BOARD_LPTIMn_FREQUENCY -> STM32_LPTIMn_CLKIN
152+
STM32_LPTIMn_FREQUENCY -> STM32_LPTIMn_CLKIN
153+
STM32_APB1_THRTIM1_CLKIN -> STM32_HRTIM1_CLKIN
154+
BOARD_HRTIM1_FREQUENCY -> STM32_HRTIM1_CLKIN
155+
138156
Public API names unified to ``stm32_*``
139157
---------------------------------------
140158

‎arch/arm/src/common/stm32/stm32_adc_m0_v1.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -94,19 +94,19 @@
9494
#if defined(CONFIG_STM32_TIM1_ADC1)
9595
# define ADC1_HAVE_TIMER 1
9696
# define ADC1_TIMER_BASE STM32_TIM1_BASE
97-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
97+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
9898
#elif defined(CONFIG_STM32_TIM2_ADC1)
9999
# define ADC1_HAVE_TIMER 1
100100
# define ADC1_TIMER_BASE STM32_TIM2_BASE
101-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
101+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN
102102
#elif defined(CONFIG_STM32_TIM3_ADC1)
103103
# define ADC1_HAVE_TIMER 1
104104
# define ADC1_TIMER_BASE STM32_TIM3_BASE
105-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
105+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
106106
#elif defined(CONFIG_STM32_TIM15_ADC1)
107107
# define ADC1_HAVE_TIMER 1
108108
# define ADC1_TIMER_BASE STM32_TIM15_BASE
109-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN
109+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN
110110
#else
111111
# undef ADC1_HAVE_TIMER
112112
#endif

‎arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h‎

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -352,47 +352,47 @@
352352
#if defined(CONFIG_STM32_TIM1_ADC1)
353353
# define ADC1_HAVE_TIMER 1
354354
# define ADC1_TIMER_BASE STM32_TIM1_BASE
355-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
355+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
356356
#elif defined(CONFIG_STM32_TIM2_ADC1)
357357
# define ADC1_HAVE_TIMER 1
358358
# define ADC1_TIMER_BASE STM32_TIM2_BASE
359-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
359+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN
360360
#elif defined(CONFIG_STM32_TIM3_ADC1)
361361
# define ADC1_HAVE_TIMER 1
362362
# define ADC1_TIMER_BASE STM32_TIM3_BASE
363-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
363+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
364364
#elif defined(CONFIG_STM32_TIM4_ADC1)
365365
# define ADC1_HAVE_TIMER 1
366366
# define ADC1_TIMER_BASE STM32_TIM4_BASE
367-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
367+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN
368368
#elif defined(CONFIG_STM32_TIM5_ADC1)
369369
# define ADC1_HAVE_TIMER 1
370370
# define ADC1_TIMER_BASE STM32_TIM5_BASE
371-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
371+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN
372372
#elif defined(CONFIG_STM32_TIM6_ADC1)
373373
# define ADC1_HAVE_TIMER 1
374374
# define ADC1_TIMER_BASE STM32_TIM6_BASE
375-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
375+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN
376376
#elif defined(CONFIG_STM32_TIM7_ADC1)
377377
# define ADC1_HAVE_TIMER 1
378378
# define ADC1_TIMER_BASE STM32_TIM7_BASE
379-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN
379+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN
380380
#elif defined(CONFIG_STM32_TIM8_ADC1)
381381
# define ADC1_HAVE_TIMER 1
382382
# define ADC1_TIMER_BASE STM32_TIM8_BASE
383-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
383+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN
384384
#elif defined(CONFIG_STM32_TIM9_ADC1)
385385
# define ADC1_HAVE_TIMER 1
386386
# define ADC1_TIMER_BASE STM32_TIM9_BASE
387-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM9_CLKIN
387+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM9_CLKIN
388388
#elif defined(CONFIG_STM32_TIM10_ADC1)
389389
# define ADC1_HAVE_TIMER 1
390390
# define ADC1_TIMER_BASE STM32_TIM10_BASE
391-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN
391+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM10_CLKIN
392392
#elif defined(CONFIG_STM32_TIM15_ADC1)
393393
# define ADC1_HAVE_TIMER 1
394394
# define ADC1_TIMER_BASE STM32_TIM15_BASE
395-
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
395+
# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN
396396
#else
397397
# undef ADC1_HAVE_TIMER
398398
#endif
@@ -417,35 +417,35 @@
417417
#if defined(CONFIG_STM32_TIM1_ADC2)
418418
# define ADC2_HAVE_TIMER 1
419419
# define ADC2_TIMER_BASE STM32_TIM1_BASE
420-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
420+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
421421
#elif defined(CONFIG_STM32_TIM2_ADC2)
422422
# define ADC2_HAVE_TIMER 1
423423
# define ADC2_TIMER_BASE STM32_TIM2_BASE
424-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
424+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN
425425
#elif defined(CONFIG_STM32_TIM3_ADC2)
426426
# define ADC2_HAVE_TIMER 1
427427
# define ADC2_TIMER_BASE STM32_TIM3_BASE
428-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
428+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
429429
#elif defined(CONFIG_STM32_TIM4_ADC2)
430430
# define ADC2_HAVE_TIMER 1
431431
# define ADC2_TIMER_BASE STM32_TIM4_BASE
432-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
432+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN
433433
#elif defined(CONFIG_STM32_TIM5_ADC2)
434434
# define ADC2_HAVE_TIMER 1
435435
# define ADC2_TIMER_BASE STM32_TIM5_BASE
436-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
436+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN
437437
#elif defined(CONFIG_STM32_TIM6_ADC2)
438438
# define ADC2_HAVE_TIMER 1
439439
# define ADC2_TIMER_BASE STM32_TIM6_BASE
440-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
440+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN
441441
#elif defined(CONFIG_STM32_TIM8_ADC2)
442442
# define ADC2_HAVE_TIMER 1
443443
# define ADC2_TIMER_BASE STM32_TIM8_BASE
444-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
444+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN
445445
#elif defined(CONFIG_STM32_TIM15_ADC2)
446446
# define ADC2_HAVE_TIMER 1
447447
# define ADC2_TIMER_BASE STM32_TIM15_BASE
448-
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
448+
# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN
449449
#else
450450
# undef ADC2_HAVE_TIMER
451451
#endif
@@ -470,39 +470,39 @@
470470
#if defined(CONFIG_STM32_TIM1_ADC3)
471471
# define ADC3_HAVE_TIMER 1
472472
# define ADC3_TIMER_BASE STM32_TIM1_BASE
473-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
473+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
474474
#elif defined(CONFIG_STM32_TIM2_ADC3)
475475
# define ADC3_HAVE_TIMER 1
476476
# define ADC3_TIMER_BASE STM32_TIM2_BASE
477-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
477+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN
478478
#elif defined(CONFIG_STM32_TIM3_ADC3)
479479
# define ADC3_HAVE_TIMER 1
480480
# define ADC3_TIMER_BASE STM32_TIM3_BASE
481-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
481+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
482482
#elif defined(CONFIG_STM32_TIM4_ADC3)
483483
# define ADC3_HAVE_TIMER 1
484484
# define ADC3_TIMER_BASE STM32_TIM4_BASE
485-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
485+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN
486486
#elif defined(CONFIG_STM32_TIM5_ADC3)
487487
# define ADC3_HAVE_TIMER 1
488488
# define ADC3_TIMER_BASE STM32_TIM5_BASE
489-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
489+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN
490490
#elif defined(CONFIG_STM32_TIM7_ADC3)
491491
# define ADC3_HAVE_TIMER 1
492492
# define ADC3_TIMER_BASE STM32_TIM7_BASE
493-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN
493+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN
494494
#elif defined(CONFIG_STM32_TIM8_ADC3)
495495
# define ADC3_HAVE_TIMER 1
496496
# define ADC3_TIMER_BASE STM32_TIM8_BASE
497-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
497+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN
498498
#elif defined(CONFIG_STM32_TIM15_ADC3)
499499
# define ADC3_HAVE_TIMER 1
500500
# define ADC3_TIMER_BASE STM32_TIM15_BASE
501-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
501+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN
502502
#elif defined(CONFIG_STM32_TIM20_ADC3)
503503
# define ADC3_HAVE_TIMER 1
504504
# define ADC3_TIMER_BASE STM32_TIM20_BASE
505-
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN
505+
# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM20_CLKIN
506506
#else
507507
# undef ADC3_HAVE_TIMER
508508
#endif
@@ -520,39 +520,39 @@
520520
#if defined(CONFIG_STM32_TIM1_ADC4)
521521
# define ADC4_HAVE_TIMER 1
522522
# define ADC4_TIMER_BASE STM32_TIM1_BASE
523-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
523+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
524524
#elif defined(CONFIG_STM32_TIM2_ADC4)
525525
# define ADC4_HAVE_TIMER 1
526526
# define ADC4_TIMER_BASE STM32_TIM2_BASE
527-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
527+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN
528528
#elif defined(CONFIG_STM32_TIM3_ADC4)
529529
# define ADC4_HAVE_TIMER 1
530530
# define ADC4_TIMER_BASE STM32_TIM3_BASE
531-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
531+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
532532
#elif defined(CONFIG_STM32_TIM4_ADC4)
533533
# define ADC4_HAVE_TIMER 1
534534
# define ADC4_TIMER_BASE STM32_TIM4_BASE
535-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
535+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN
536536
#elif defined(CONFIG_STM32_TIM5_ADC4)
537537
# define ADC4_HAVE_TIMER 1
538538
# define ADC4_TIMER_BASE STM32_TIM5_BASE
539-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
539+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN
540540
#elif defined(CONFIG_STM32_TIM7_ADC4)
541541
# define ADC4_HAVE_TIMER 1
542542
# define ADC4_TIMER_BASE STM32_TIM7_BASE
543-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN
543+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN
544544
#elif defined(CONFIG_STM32_TIM8_ADC4)
545545
# define ADC4_HAVE_TIMER 1
546546
# define ADC4_TIMER_BASE STM32_TIM8_BASE
547-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
547+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN
548548
#elif defined(CONFIG_STM32_TIM15_ADC4)
549549
# define ADC4_HAVE_TIMER 1
550550
# define ADC4_TIMER_BASE STM32_TIM15_BASE
551-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
551+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN
552552
#elif defined(CONFIG_STM32_TIM20_ADC4)
553553
# define ADC4_HAVE_TIMER 1
554554
# define ADC4_TIMER_BASE STM32_TIM20_BASE
555-
# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN
555+
# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM20_CLKIN
556556
#else
557557
# undef ADC4_HAVE_TIMER
558558
#endif

‎arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -645,62 +645,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev,
645645
{
646646
#ifdef CONFIG_STM32_TIM1
647647
case STM32_TIM1_BASE:
648-
freqin = STM32_APB2_TIM1_CLKIN;
648+
freqin = STM32_TIM1_CLKIN;
649649
break;
650650
#endif
651651
#ifdef CONFIG_STM32_TIM2
652652
case STM32_TIM2_BASE:
653-
freqin = STM32_APB1_TIM2_CLKIN;
653+
freqin = STM32_TIM2_CLKIN;
654654
break;
655655
#endif
656656
#ifdef CONFIG_STM32_TIM3
657657
case STM32_TIM3_BASE:
658-
freqin = STM32_APB1_TIM3_CLKIN;
658+
freqin = STM32_TIM3_CLKIN;
659659
break;
660660
#endif
661661
#ifdef CONFIG_STM32_TIM4
662662
case STM32_TIM4_BASE:
663-
freqin = STM32_APB1_TIM4_CLKIN;
663+
freqin = STM32_TIM4_CLKIN;
664664
break;
665665
#endif
666666
#ifdef CONFIG_STM32_TIM5
667667
case STM32_TIM5_BASE:
668-
freqin = STM32_APB1_TIM5_CLKIN;
668+
freqin = STM32_TIM5_CLKIN;
669669
break;
670670
#endif
671671
#ifdef CONFIG_STM32_TIM8
672672
case STM32_TIM8_BASE:
673-
freqin = STM32_APB2_TIM8_CLKIN;
673+
freqin = STM32_TIM8_CLKIN;
674674
break;
675675
#endif
676676
#ifdef CONFIG_STM32_TIM9
677677
case STM32_TIM9_BASE:
678-
freqin = STM32_APB2_TIM9_CLKIN;
678+
freqin = STM32_TIM9_CLKIN;
679679
break;
680680
#endif
681681
#ifdef CONFIG_STM32_TIM10
682682
case STM32_TIM10_BASE:
683-
freqin = STM32_APB2_TIM10_CLKIN;
683+
freqin = STM32_TIM10_CLKIN;
684684
break;
685685
#endif
686686
#ifdef CONFIG_STM32_TIM11
687687
case STM32_TIM11_BASE:
688-
freqin = STM32_APB2_TIM11_CLKIN;
688+
freqin = STM32_TIM11_CLKIN;
689689
break;
690690
#endif
691691
#ifdef CONFIG_STM32_TIM12
692692
case STM32_TIM12_BASE:
693-
freqin = STM32_APB1_TIM12_CLKIN;
693+
freqin = STM32_TIM12_CLKIN;
694694
break;
695695
#endif
696696
#ifdef CONFIG_STM32_TIM13
697697
case STM32_TIM13_BASE:
698-
freqin = STM32_APB1_TIM13_CLKIN;
698+
freqin = STM32_TIM13_CLKIN;
699699
break;
700700
#endif
701701
#ifdef CONFIG_STM32_TIM14
702702
case STM32_TIM14_BASE:
703-
freqin = STM32_APB1_TIM14_CLKIN;
703+
freqin = STM32_TIM14_CLKIN;
704704
break;
705705
#endif
706706

‎arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1359,44 +1359,44 @@ static int dac_timinit(struct stm32_chan_s *chan)
13591359
#ifdef NEED_TIM2
13601360
case 2:
13611361
setbits = RCC_APB1ENR_TIM2EN;
1362-
pclk = BOARD_TIM2_FREQUENCY;
1362+
pclk = STM32_TIM2_CLKIN;
13631363
break;
13641364
#endif
13651365
#ifdef NEED_TIM3
13661366
case 3:
13671367
setbits = RCC_APB1ENR_TIM3EN;
1368-
pclk = BOARD_TIM3_FREQUENCY;
1368+
pclk = STM32_TIM3_CLKIN;
13691369
break;
13701370
#endif
13711371
#ifdef NEED_TIM4
13721372
case 4:
13731373
setbits = RCC_APB1ENR_TIM4EN;
1374-
pclk = BOARD_TIM4_FREQUENCY;
1374+
pclk = STM32_TIM4_CLKIN;
13751375
break;
13761376
#endif
13771377
#ifdef NEED_TIM5
13781378
case 5:
13791379
setbits = RCC_APB1ENR_TIM5EN;
1380-
pclk = BOARD_TIM5_FREQUENCY;
1380+
pclk = STM32_TIM5_CLKIN;
13811381
break;
13821382
#endif
13831383
#ifdef NEED_TIM6
13841384
case 6:
13851385
setbits = RCC_APB1ENR_TIM6EN;
1386-
pclk = BOARD_TIM6_FREQUENCY;
1386+
pclk = STM32_TIM6_CLKIN;
13871387
break;
13881388
#endif
13891389
#ifdef NEED_TIM7
13901390
case 7:
13911391
setbits = RCC_APB1ENR_TIM7EN;
1392-
pclk = BOARD_TIM7_FREQUENCY;
1392+
pclk = STM32_TIM7_CLKIN;
13931393
break;
13941394
#endif
13951395
#ifdef NEED_TIM8
13961396
case 8:
13971397
regaddr = STM32_RCC_APB2ENR;
13981398
setbits = RCC_APB2ENR_TIM8EN;
1399-
pclk = BOARD_TIM8_FREQUENCY;
1399+
pclk = STM32_TIM8_CLKIN;
14001400
break;
14011401
#endif
14021402
default:

‎arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -62,11 +62,7 @@
6262

6363
#define HAVE_CCMR2 1
6464

65-
#ifdef STM32_APB2_TIM1_CLKIN
66-
# define PULSECOUNT_TIM1_CLKIN STM32_APB2_TIM1_CLKIN
67-
#else
68-
# define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN
69-
#endif
65+
#define PULSECOUNT_TIM1_CLKIN STM32_TIM1_CLKIN
7066

7167
#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1
7268
# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT

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