lowered schedule and systolic primitive

[uslumt]

Hello,

I'm very new to heterocl, the lowered schedule in the tutorials dont look like the same structure comparison to below schedule and the documentation in https://heterocl.csl.cornell.edu/doc/tutorials/tutorial_06_memory.html

#map = affine_map<(d0, d1) -> (d0, d1, 0, 0)> module { func.func @top(%arg0: memref<10x100xi32, #map>) -> memref<10x100xi32> attributes {itypes = "s", otypes = "s"} { %0 = memref.alloc() {name = "B"} : memref<10x100xi32> affine.for %arg1 = 0 to 10 { affine.for %arg2 = 0 to 100 { %1 = affine.load %arg0[%arg1, %arg2] {from = "A"} : memref<10x100xi32, #map> %c1_i32 = arith.constant 1 : i32 %2 = arith.extsi %1 : i32 to i33 %3 = arith.extsi %c1_i32 : i32 to i33 %4 = arith.addi %2, %3 : i33 %5 = arith.trunci %4 : i33 to i32 affine.store %5, %0[%arg1, %arg2] {to = "B"} : memref<10x100xi32> } {loop_name = "y"} } {loop_name = "x", op_name = "B"} return %0 : memref<10x100xi32> } }

is it caused by the current version?

Finally I try to use systolic primitive, do you have any tutorial on this ?

Best regards

[chhzh123]

Hi @uslumt, thanks for your interest in our project. Currently we have migrated our backend flow to MLIR, so the intermediate representation also changed. Please refer to this document for the latest information.

Previously we were using AutoSA as the backend for generating systolic arrays, while AutoSA is no longer maintained, so we did not integrate it into our current flow. However, there are some internal efforts in leveraging Heteroflow to generate systolic arrays, and we will make it work soon.